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Commit 0c4c07d0 by Jaydeep Patil Committed by Jim Stichnoth
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[SubZero] Fix code generation for vector type

The patch fixes legalizeToReg issues in vector code generation. The patch also generates JALR for pointer to function and corrects encoding of FP conditional move instruction. R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2468133002 . Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.
parent 67a49b5b
Showing with 917 additions and 678 deletions
src/IceAssemblerMIPS32.cpp
......@@ -645,6 +645,17 @@ void AssemblerMIPS32::jal(const ConstantRelocatable *Target) {
nop();
}
void AssemblerMIPS32::jalr(const Operand *OpRs, const Operand *OpRd) {
IValueT Opcode = 0x00000009;
const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr");
const IValueT Rd =
(OpRd == nullptr) ? 31 : encodeGPRegister(OpRd, "Rd", "jalr");
Opcode |= Rd << 16;
Opcode |= Rs << 21;
emitInst(Opcode);
nop();
}
void AssemblerMIPS32::lui(const Operand *OpRt, const Operand *OpImm,
const RelocOp Reloc) {
IValueT Opcode = 0x3C000000;
......@@ -833,13 +844,13 @@ void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs,
void AssemblerMIPS32::movn_d(const Operand *OpFd, const Operand *OpFs,
const Operand *OpFt) {
static constexpr IValueT Opcode = 0x44000013;
emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d");
emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d");
}
void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs,
const Operand *OpFt) {
static constexpr IValueT Opcode = 0x44000013;
emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
}
void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs,
......
src/IceAssemblerMIPS32.h
......@@ -188,6 +188,8 @@ public:
void jal(const ConstantRelocatable *Target);
void jalr(const Operand *OpRs, const Operand *OpRd);
void lui(const Operand *OpRt, const Operand *OpImm, const RelocOp Reloc);
void ldc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
......
src/IceInstMIPS32.cpp
......@@ -552,7 +552,7 @@ void InstMIPS32Call::emit(const Cfg *Func) const {
CallTarget->emitWithoutPrefix(Func->getTarget());
} else {
Str << "\t"
"jal"
"jalr"
"\t";
getCallTarget()->emit(Func);
}
......@@ -561,11 +561,14 @@ void InstMIPS32Call::emit(const Cfg *Func) const {
void InstMIPS32Call::emitIAS(const Cfg *Func) const {
assert(getSrcSize() == 1);
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
if (const auto *CallTarget =
llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
if (llvm::isa<ConstantInteger32>(getCallTarget())) {
llvm::report_fatal_error("MIPS32Call to ConstantInteger32");
} else if (const auto *CallTarget =
llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
Asm->jal(CallTarget);
} else {
llvm::report_fatal_error("MIPS32Call: Invalid operand");
const Operand *ImplicitRA = nullptr;
Asm->jalr(getCallTarget(), ImplicitRA);
}
}
......
src/IceTargetLoweringMIPS32.cpp
......@@ -3247,12 +3247,15 @@ void TargetMIPS32::lowerCall(const InstCall *Instr) {
if (ReturnReg) {
if (RetVecFloat) {
auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
auto *TBase = legalizeToReg(RetVecFloat);
for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
auto *Var = DestVecOn32->getContainers()[i];
auto *TVar = makeReg(IceType_i32);
OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
Func, IceType_i32, RetVecFloat,
Func, IceType_i32, TBase,
llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
_lw(Var, Mem);
_lw(TVar, Mem);
_mov(Var, TVar);
}
} else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) {
auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
......@@ -3538,7 +3541,8 @@ void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
// Number of elements in each container
uint32_t ElemPerCont =
typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
auto *Src = Src0R->getContainers()[Index / ElemPerCont];
auto *SrcE = legalizeToReg(Src);
// Position of the element in the container
uint32_t PosInCont = Index % ElemPerCont;
if (ElemPerCont == 1) {
......@@ -4050,7 +4054,10 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
uint32_t ElemPerCont =
typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
// Source Element
auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
auto *Src = Src0R->getContainers()[Index / ElemPerCont];
auto *SrcE = Src;
if (ElemPerCont > 1)
SrcE = legalizeToReg(Src);
// Dest is a vector
auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest);
VDest->initVecElement(Func);
......@@ -4067,6 +4074,7 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
auto *TReg3 = makeReg(Src1R->getType());
auto *TReg4 = makeReg(Src1R->getType());
auto *TReg5 = makeReg(Src1R->getType());
auto *TDReg = makeReg(Src1R->getType());
// Position of the element in the container
uint32_t PosInCont = Index % ElemPerCont;
// Load source vector in a temporary vector
......@@ -4089,13 +4097,15 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
_andi(TReg1, Src1R, 0xffff); // Clear upper 16-bits of source
_srl(TReg2, SrcE, 16);
_sll(TReg3, TReg2, 16); // Clear lower 16-bits of element
_or(DstE, TReg1, TReg3);
_or(TDReg, TReg1, TReg3);
_mov(DstE, TDReg);
break;
case 1:
_sll(TReg1, Src1R, 16); // Clear lower 16-bits of source
_sll(TReg2, SrcE, 16);
_srl(TReg3, TReg2, 16); // Clear upper 16-bits of element
_or(DstE, TReg1, TReg3);
_or(TDReg, TReg1, TReg3);
_mov(DstE, TDReg);
break;
default:
llvm::report_fatal_error("InsertElement: Invalid PosInCont");
......@@ -4107,7 +4117,8 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
_andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
_srl(TReg2, SrcE, 8);
_sll(TReg3, TReg2, 8); // Clear bits[7:0] of element
_or(DstE, TReg1, TReg3);
_or(TDReg, TReg1, TReg3);
_mov(DstE, TDReg);
break;
case 1:
_andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
......@@ -4115,7 +4126,8 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
_lui(TReg2, Ctx->getConstantInt32(0xffff));
_ori(TReg3, TReg2, 0x00ff);
_and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element
_or(DstE, TReg5, TReg4);
_or(TDReg, TReg5, TReg4);
_mov(DstE, TDReg);
break;
case 2:
_andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source
......@@ -4123,13 +4135,15 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
_lui(TReg2, Ctx->getConstantInt32(0xff00));
_ori(TReg3, TReg2, 0xffff);
_and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element
_or(DstE, TReg5, TReg4);
_or(TDReg, TReg5, TReg4);
_mov(DstE, TDReg);
break;
case 3:
_srl(TReg1, Src1R, 24); // Position in the destination
_sll(TReg2, SrcE, 8);
_srl(TReg3, TReg2, 8); // Clear bits[31:24] of element
_or(DstE, TReg1, TReg3);
_or(TDReg, TReg1, TReg3);
_mov(DstE, TDReg);
break;
default:
llvm::report_fatal_error("InsertElement: Invalid PosInCont");
......@@ -4746,7 +4760,7 @@ void TargetMIPS32::lowerRet(const InstRet *Instr) {
case IceType_v16i8:
case IceType_v8i16:
case IceType_v4i32: {
auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0);
auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0));
Variable *V0 =
legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0);
Variable *V1 =
......@@ -4762,7 +4776,7 @@ void TargetMIPS32::lowerRet(const InstRet *Instr) {
break;
}
case IceType_v4f32: {
auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0);
auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0));
Reg = getImplicitRet();
auto *RegT = legalizeToReg(Reg);
// Return the vector through buffer in implicit argument a0
......@@ -4806,13 +4820,13 @@ void TargetMIPS32::lowerSelect(const InstSelect *Instr) {
if (DestTy == IceType_i64) {
DestR = llvm::cast<Variable>(loOperand(Dest));
DestHiR = llvm::cast<Variable>(hiOperand(Dest));
SrcTR = legalizeToReg(loOperand(Instr->getTrueOperand()));
SrcTHiR = legalizeToReg(hiOperand(Instr->getTrueOperand()));
SrcFR = legalizeToReg(loOperand(Instr->getFalseOperand()));
SrcFHiR = legalizeToReg(hiOperand(Instr->getFalseOperand()));
SrcTR = legalizeToReg(loOperand(legalizeUndef(Instr->getTrueOperand())));
SrcTHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getTrueOperand())));
SrcFR = legalizeToReg(loOperand(legalizeUndef(Instr->getFalseOperand())));
SrcFHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getFalseOperand())));
} else {
SrcTR = legalizeToReg(Instr->getTrueOperand());
SrcFR = legalizeToReg(Instr->getFalseOperand());
SrcTR = legalizeToReg(legalizeUndef(Instr->getTrueOperand()));
SrcFR = legalizeToReg(legalizeUndef(Instr->getFalseOperand()));
}
Variable *ConditionR = legalizeToReg(Instr->getCondition());
......
tests_lit/llvm2ice_tests/vector-arg.ll
......@@ -560,18 +560,19 @@ entry:
; MIPS32: sw a3,{{.*}}(sp)
; MIPS32: move a2,v0
; MIPS32: move a3,a1
; MIPS32: jal 0 <test_returning_arg0> 494: R_MIPS_26 VectorReturn
; MIPS32: jal 0 <test_returning_arg0> {{.*}} R_MIPS_26 VectorReturn
; MIPS32: nop
; MIPS32: lw v0,0(s0)
; MIPS32: lw v1,4(s0)
; MIPS32: lw a1,8(s0)
; MIPS32: lw a0,8(s0)
; MIPS32: move a1,a0
; MIPS32: lw s0,12(s0)
; MIPS32: addiu a0,sp,32
; MIPS32: sw a1,{{.*}}(sp)
; MIPS32: sw s0,{{.*}}(sp)
; MIPS32: move a2,v0
; MIPS32: move a3,v1
; MIPS32: jal 0 <test_returning_arg0> 4c0: R_MIPS_26 VectorReturn
; MIPS32: jal 0 <test_returning_arg0> {{.*}} R_MIPS_26 VectorReturn
; MIPS32: nop
; MIPS32: move sp,s8
; MIPS32: lw s0,{{.*}}(sp)
......
tests_lit/llvm2ice_tests/vector-cast.ll
......@@ -33,7 +33,8 @@ entry:
; X8632: pcmpgtb
; ARM32: vshl.s8
; ARM32-NEXT: vshr.s8
; MIPS32: andi t2,a0,0xff
; MIPS32: move t2,a0
; MIPS32: andi t2,t2,0xff
; MIPS32: andi t2,t2,0x1
; MIPS32: sll t2,t2,0x1f
; MIPS32: sra t2,t2,0x1f
......@@ -41,7 +42,8 @@ entry:
; MIPS32: srl v0,v0,0x8
; MIPS32: sll v0,v0,0x8
; MIPS32: or t2,t2,v0
; MIPS32: srl v0,a0,0x8
; MIPS32: move v0,a0
; MIPS32: srl v0,v0,0x8
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
......@@ -52,7 +54,8 @@ entry:
; MIPS32: ori t3,t3,0xff
; MIPS32: and t2,t2,t3
; MIPS32: or v0,v0,t2
; MIPS32: srl t2,a0,0x10
; MIPS32: move t2,a0
; MIPS32: srl t2,t2,0x10
; MIPS32: andi t2,t2,0xff
; MIPS32: andi t2,t2,0x1
; MIPS32: sll t2,t2,0x1f
......@@ -71,7 +74,8 @@ entry:
; MIPS32: sll t2,t2,0x8
; MIPS32: srl t2,t2,0x8
; MIPS32: or a0,a0,t2
; MIPS32: andi v0,a1,0xff
; MIPS32: move v0,a1
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
; MIPS32: sra v0,v0,0x1f
......@@ -79,7 +83,8 @@ entry:
; MIPS32: srl v1,v1,0x8
; MIPS32: sll v1,v1,0x8
; MIPS32: or v0,v0,v1
; MIPS32: srl v1,a1,0x8
; MIPS32: move v1,a1
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0x1
; MIPS32: sll v1,v1,0x1f
......@@ -90,7 +95,8 @@ entry:
; MIPS32: ori t2,t2,0xff
; MIPS32: and v0,v0,t2
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a1,0x10
; MIPS32: move v0,a1
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
......@@ -109,7 +115,8 @@ entry:
; MIPS32: sll v0,v0,0x8
; MIPS32: srl v0,v0,0x8
; MIPS32: or a1,a1,v0
; MIPS32: andi v0,a2,0xff
; MIPS32: move v0,a2
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
; MIPS32: sra v0,v0,0x1f
......@@ -117,7 +124,8 @@ entry:
; MIPS32: srl t0,t0,0x8
; MIPS32: sll t0,t0,0x8
; MIPS32: or v0,v0,t0
; MIPS32: srl v1,a2,0x8
; MIPS32: move v1,a2
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0x1
; MIPS32: sll v1,v1,0x1f
......@@ -128,7 +136,8 @@ entry:
; MIPS32: ori t0,t0,0xff
; MIPS32: and v0,v0,t0
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a2,0x10
; MIPS32: move v0,a2
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
......@@ -147,7 +156,8 @@ entry:
; MIPS32: sll v0,v0,0x8
; MIPS32: srl v0,v0,0x8
; MIPS32: or a2,a2,v0
; MIPS32: andi v0,a3,0xff
; MIPS32: move v0,a3
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
; MIPS32: sra v0,v0,0x1f
......@@ -155,7 +165,8 @@ entry:
; MIPS32: srl t1,t1,0x8
; MIPS32: sll t1,t1,0x8
; MIPS32: or v0,v0,t1
; MIPS32: srl v1,a3,0x8
; MIPS32: move v1,a3
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0x1
; MIPS32: sll v1,v1,0x1f
......@@ -166,7 +177,8 @@ entry:
; MIPS32: ori t0,t0,0xff
; MIPS32: and v0,v0,t0
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a3,0x10
; MIPS32: move v0,a3
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
......@@ -201,7 +213,8 @@ entry:
; MIPS32: move v1,zero
; MIPS32: move t0,zero
; MIPS32: move t1,zero
; MIPS32: andi t2,a0,0xffff
; MIPS32: move t2,a0
; MIPS32: andi t2,t2,0xffff
; MIPS32: andi t2,t2,0x1
; MIPS32: sll t2,t2,0x1f
; MIPS32: sra t2,t2,0x1f
......@@ -217,7 +230,8 @@ entry:
; MIPS32: sll t2,t2,0x10
; MIPS32: srl t2,t2,0x10
; MIPS32: or a0,a0,t2
; MIPS32: andi v0,a1,0xffff
; MIPS32: move v0,a1
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
; MIPS32: sra v0,v0,0x1f
......@@ -233,7 +247,8 @@ entry:
; MIPS32: sll v0,v0,0x10
; MIPS32: srl v0,v0,0x10
; MIPS32: or a1,a1,v0
; MIPS32: andi v0,a2,0xffff
; MIPS32: move v0,a2
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
; MIPS32: sra v0,v0,0x1f
......@@ -249,7 +264,8 @@ entry:
; MIPS32: sll v0,v0,0x10
; MIPS32: srl v0,v0,0x10
; MIPS32: or a2,a2,v0
; MIPS32: andi v0,a3,0xffff
; MIPS32: move v0,a3
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0x1
; MIPS32: sll v0,v0,0x1f
; MIPS32: sra v0,v0,0x1f
......@@ -305,14 +321,16 @@ entry:
; X8632: pand
; ARM32: vmov.i8 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
; MIPS32: andi t2,a0,0xff
; MIPS32: move t2,a0
; MIPS32: andi t2,t2,0xff
; MIPS32: andi t2,t2,0x1
; MIPS32: andi t2,t2,0x1
; MIPS32: andi t2,t2,0xff
; MIPS32: srl v0,v0,0x8
; MIPS32: sll v0,v0,0x8
; MIPS32: or t2,t2,v0
; MIPS32: srl v0,a0,0x8
; MIPS32: move v0,a0
; MIPS32: srl v0,v0,0x8
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
......@@ -322,7 +340,8 @@ entry:
; MIPS32: ori t3,t3,0xff
; MIPS32: and t2,t2,t3
; MIPS32: or v0,v0,t2
; MIPS32: srl t2,a0,0x10
; MIPS32: move t2,a0
; MIPS32: srl t2,t2,0x10
; MIPS32: andi t2,t2,0xff
; MIPS32: andi t2,t2,0x1
; MIPS32: andi t2,t2,0x1
......@@ -339,14 +358,16 @@ entry:
; MIPS32: sll t2,t2,0x8
; MIPS32: srl t2,t2,0x8
; MIPS32: or a0,a0,t2
; MIPS32: andi v0,a1,0xff
; MIPS32: move v0,a1
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0xff
; MIPS32: srl v1,v1,0x8
; MIPS32: sll v1,v1,0x8
; MIPS32: or v0,v0,v1
; MIPS32: srl v1,a1,0x8
; MIPS32: move v1,a1
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0x1
; MIPS32: andi v1,v1,0x1
......@@ -356,7 +377,8 @@ entry:
; MIPS32: ori t2,t2,0xff
; MIPS32: and v0,v0,t2
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a1,0x10
; MIPS32: move v0,a1
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
......@@ -373,14 +395,16 @@ entry:
; MIPS32: sll v0,v0,0x8
; MIPS32: srl v0,v0,0x8
; MIPS32: or a1,a1,v0
; MIPS32: andi v0,a2,0xff
; MIPS32: move v0,a2
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0xff
; MIPS32: srl t0,t0,0x8
; MIPS32: sll t0,t0,0x8
; MIPS32: or v0,v0,t0
; MIPS32: srl v1,a2,0x8
; MIPS32: move v1,a2
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0x1
; MIPS32: andi v1,v1,0x1
......@@ -390,7 +414,8 @@ entry:
; MIPS32: ori t0,t0,0xff
; MIPS32: and v0,v0,t0
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a2,0x10
; MIPS32: move v0,a2
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
......@@ -407,14 +432,16 @@ entry:
; MIPS32: sll v0,v0,0x8
; MIPS32: srl v0,v0,0x8
; MIPS32: or a2,a2,v0
; MIPS32: andi v0,a3,0xff
; MIPS32: move v0,a3
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0xff
; MIPS32: srl t1,t1,0x8
; MIPS32: sll t1,t1,0x8
; MIPS32: or v0,v0,t1
; MIPS32: srl v1,a3,0x8
; MIPS32: move v1,a3
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0x1
; MIPS32: andi v1,v1,0x1
......@@ -424,7 +451,8 @@ entry:
; MIPS32: ori t0,t0,0xff
; MIPS32: and v0,v0,t0
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a3,0x10
; MIPS32: move v0,a3
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
......@@ -455,7 +483,8 @@ entry:
; X8632: pand
; ARM32: vmov.i16 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
; MIPS32: andi t2,a0,0xffff
; MIPS32: move t2,a0
; MIPS32: andi t2,t2,0xffff
; MIPS32: andi t2,t2,0x1
; MIPS32: andi t2,t2,0x1
; MIPS32: andi t2,t2,0xffff
......@@ -469,7 +498,8 @@ entry:
; MIPS32: sll t2,t2,0x10
; MIPS32: srl t2,t2,0x10
; MIPS32: or a0,a0,t2
; MIPS32: andi v0,a1,0xffff
; MIPS32: move v0,a1
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0xffff
......@@ -483,7 +513,8 @@ entry:
; MIPS32: sll v0,v0,0x10
; MIPS32: srl v0,v0,0x10
; MIPS32: or a1,a1,v0
; MIPS32: andi v0,a2,0xffff
; MIPS32: move v0,a2
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0xffff
......@@ -497,7 +528,8 @@ entry:
; MIPS32: sll v0,v0,0x10
; MIPS32: srl v0,v0,0x10
; MIPS32: or a2,a2,v0
; MIPS32: andi v0,a3,0xffff
; MIPS32: move v0,a3
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0x1
; MIPS32: andi v0,v0,0xffff
......@@ -547,12 +579,14 @@ entry:
; X8632: pcmpeqb
; X8632: psubb
; X8632: pand
; MIPS32: andi t2,a0,0xff
; MIPS32: move t2,a0
; MIPS32: andi t2,t2,0xff
; MIPS32: andi t2,t2,0xff
; MIPS32: srl v0,v0,0x8
; MIPS32: sll v0,v0,0x8
; MIPS32: or t2,t2,v0
; MIPS32: srl v0,a0,0x8
; MIPS32: move v0,a0
; MIPS32: srl v0,v0,0x8
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: sll v0,v0,0x8
......@@ -560,7 +594,8 @@ entry:
; MIPS32: ori t3,t3,0xff
; MIPS32: and t2,t2,t3
; MIPS32: or v0,v0,t2
; MIPS32: srl t2,a0,0x10
; MIPS32: move t2,a0
; MIPS32: srl t2,t2,0x10
; MIPS32: andi t2,t2,0xff
; MIPS32: andi t2,t2,0xff
; MIPS32: sll t2,t2,0x10
......@@ -573,12 +608,14 @@ entry:
; MIPS32: sll t2,t2,0x8
; MIPS32: srl t2,t2,0x8
; MIPS32: or a0,a0,t2
; MIPS32: andi v0,a1,0xff
; MIPS32: move v0,a1
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: srl v1,v1,0x8
; MIPS32: sll v1,v1,0x8
; MIPS32: or v0,v0,v1
; MIPS32: srl v1,a1,0x8
; MIPS32: move v1,a1
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0xff
; MIPS32: sll v1,v1,0x8
......@@ -586,7 +623,8 @@ entry:
; MIPS32: ori t2,t2,0xff
; MIPS32: and v0,v0,t2
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a1,0x10
; MIPS32: move v0,a1
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: sll v0,v0,0x10
......@@ -599,12 +637,14 @@ entry:
; MIPS32: sll v0,v0,0x8
; MIPS32: srl v0,v0,0x8
; MIPS32: or a1,a1,v0
; MIPS32: andi v0,a2,0xff
; MIPS32: move v0,a2
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: srl t0,t0,0x8
; MIPS32: sll t0,t0,0x8
; MIPS32: or v0,v0,t0
; MIPS32: srl v1,a2,0x8
; MIPS32: move v1,a2
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0xff
; MIPS32: sll v1,v1,0x8
......@@ -612,7 +652,8 @@ entry:
; MIPS32: ori t0,t0,0xff
; MIPS32: and v0,v0,t0
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a2,0x10
; MIPS32: move v0,a2
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: sll v0,v0,0x10
......@@ -625,12 +666,14 @@ entry:
; MIPS32: sll v0,v0,0x8
; MIPS32: srl v0,v0,0x8
; MIPS32: or a2,a2,v0
; MIPS32: andi v0,a3,0xff
; MIPS32: move v0,a3
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: srl t1,t1,0x8
; MIPS32: sll t1,t1,0x8
; MIPS32: or v0,v0,t1
; MIPS32: srl v1,a3,0x8
; MIPS32: move v1,a3
; MIPS32: srl v1,v1,0x8
; MIPS32: andi v1,v1,0xff
; MIPS32: andi v1,v1,0xff
; MIPS32: sll v1,v1,0x8
......@@ -638,7 +681,8 @@ entry:
; MIPS32: ori t0,t0,0xff
; MIPS32: and v0,v0,t0
; MIPS32: or v1,v1,v0
; MIPS32: srl v0,a3,0x10
; MIPS32: move v0,a3
; MIPS32: srl v0,v0,0x10
; MIPS32: andi v0,v0,0xff
; MIPS32: andi v0,v0,0xff
; MIPS32: sll v0,v0,0x10
......@@ -663,7 +707,8 @@ entry:
; X8632: pcmpeqw
; X8632: psubw
; X8632: pand
; MIPS32: andi t2,a0,0xffff
; MIPS32: move t2,a0
; MIPS32: andi t2,t2,0xffff
; MIPS32: andi t2,t2,0xffff
; MIPS32: srl v0,v0,0x10
; MIPS32: sll v0,v0,0x10
......@@ -673,7 +718,8 @@ entry:
; MIPS32: sll t2,t2,0x10
; MIPS32: srl t2,t2,0x10
; MIPS32: or a0,a0,t2
; MIPS32: andi v0,a1,0xffff
; MIPS32: move v0,a1
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0xffff
; MIPS32: srl v1,v1,0x10
; MIPS32: sll v1,v1,0x10
......@@ -683,7 +729,8 @@ entry:
; MIPS32: sll v0,v0,0x10
; MIPS32: srl v0,v0,0x10
; MIPS32: or a1,a1,v0
; MIPS32: andi v0,a2,0xffff
; MIPS32: move v0,a2
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0xffff
; MIPS32: srl t0,t0,0x10
; MIPS32: sll t0,t0,0x10
......@@ -693,7 +740,8 @@ entry:
; MIPS32: sll v0,v0,0x10
; MIPS32: srl v0,v0,0x10
; MIPS32: or a2,a2,v0
; MIPS32: andi v0,a3,0xffff
; MIPS32: move v0,a3
; MIPS32: andi v0,v0,0xffff
; MIPS32: andi v0,v0,0xffff
; MIPS32: srl t1,t1,0x10
; MIPS32: sll t1,t1,0x10
......
tests_lit/llvm2ice_tests/vector-icmp.ll
This source diff could not be displayed because it is too large. You can view the blob instead.
tests_lit/llvm2ice_tests/vector-select.ll
......@@ -29,202 +29,254 @@ entry:
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v16i8
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xff
; MIPS32: andi [[T14:.*]],[[T4]],0xff
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: addiu [[T0:.*]],sp,-20
; MIPS32: sw [[T1:.*]],
; MIPS32: sw [[T2:.*]],
; MIPS32: sw [[T3:.*]],
; MIPS32: sw [[T4:.*]],
; MIPS32: sw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: lw [[T8:.*]],
; MIPS32: lw [[T9:.*]],
; MIPS32: lw [[T10:.*]],
; MIPS32: lw [[T11:.*]],
; MIPS32: lw [[T12:.*]],
; MIPS32: lw [[T13:.*]],
; MIPS32: move [[T14:.*]],zero
; MIPS32: move [[T15:.*]],zero
; MIPS32: move [[T5]],zero
; MIPS32: move [[T4]],zero
; MIPS32: move [[T3]],a0
; MIPS32: andi [[T3]],[[T3]],0xff
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: move [[T2]],[[T6]]
; MIPS32: andi [[T2]],[[T2]],0xff
; MIPS32: move [[T1]],[[T10]]
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: movn [[T1]],[[T2]],[[T3]]
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: or [[T1]],[[T1]],[[T14]]
; MIPS32: move [[T14]],a0
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T8]],a0,0x8
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x8
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: srl [[T13]],[[T4]],0x8
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: movn [[T13]],[[T12]],[[T8]]
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: sll [[T13]],[[T13]],0x8
; MIPS32: lui [[T8]],0xffff
; MIPS32: ori [[T8]],[[T8]],0xff
; MIPS32: and [[T14]],[[T14]],[[T8]]
; MIPS32: or [[T13]],[[T13]],[[T14]]
; MIPS32: srl [[T8]],a0,0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x10
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: srl [[T14]],[[T4]],0x10
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: move [[T3]],[[T6]]
; MIPS32: srl [[T3]],[[T3]],0x8
; MIPS32: andi [[T3]],[[T3]],0xff
; MIPS32: move [[T2]],[[T10]]
; MIPS32: srl [[T2]],[[T2]],0x8
; MIPS32: andi [[T2]],[[T2]],0xff
; MIPS32: movn [[T2]],[[T3]],[[T14]]
; MIPS32: andi [[T2]],[[T2]],0xff
; MIPS32: sll [[T2]],[[T2]],0x8
; MIPS32: lui [[T14]],0xffff
; MIPS32: ori [[T14]],[[T14]],0xff
; MIPS32: and [[T1]],[[T1]],[[T14]]
; MIPS32: or [[T2]],[[T2]],[[T1]]
; MIPS32: move [[T14]],a0
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: move [[T3]],[[T6]]
; MIPS32: srl [[T3]],[[T3]],0x10
; MIPS32: andi [[T3]],[[T3]],0xff
; MIPS32: move [[T1]],[[T10]]
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: movn [[T1]],[[T3]],[[T14]]
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: sll [[T1]],[[T1]],0x10
; MIPS32: lui [[T14]],0xff00
; MIPS32: ori [[T14]],[[T14]],0xffff
; MIPS32: and [[T2]],[[T2]],[[T14]]
; MIPS32: or [[T1]],[[T1]],[[T2]]
; MIPS32: srl [[T16:.*]],a0,0x18
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: srl [[T10]],[[T10]],0x18
; MIPS32: movn [[T10]],[[T6]],[[T16]]
; MIPS32: srl [[T10]],[[T10]],0x18
; MIPS32: sll [[T1]],[[T1]],0x8
; MIPS32: srl [[T1]],[[T1]],0x8
; MIPS32: or [[T10]],[[T10]],[[T1]]
; MIPS32: move [[T6]],a1
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: move [[T14]],[[T11]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: movn [[T14]],[[T12]],[[T8]]
; MIPS32: movn [[T14]],[[T16]],[[T6]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: or [[T14]],[[T14]],[[T15]]
; MIPS32: move [[T6]],a1
; MIPS32: srl [[T6]],[[T6]],0x8
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: srl [[T16]],[[T16]],0x8
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: move [[T15]],[[T11]]
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: movn [[T15]],[[T16]],[[T6]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: lui [[T6]],0xffff
; MIPS32: ori [[T6]],[[T6]],0xff
; MIPS32: and [[T14]],[[T14]],[[T6]]
; MIPS32: or [[T15]],[[T15]],[[T14]]
; MIPS32: move [[T6]],a1
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: move [[T14]],[[T11]]
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: movn [[T14]],[[T16]],[[T6]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: lui [[T8]],0xff00
; MIPS32: ori [[T8]],[[T8]],0xffff
; MIPS32: and [[T13]],[[T13]],[[T8]]
; MIPS32: or [[T14]],[[T14]],[[T13]]
; MIPS32: srl [[T15:.*]],a0,0x18
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x18
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: lui [[T6]],0xff00
; MIPS32: ori [[T6]],[[T6]],0xffff
; MIPS32: and [[T15]],[[T15]],[[T6]]
; MIPS32: or [[T14]],[[T14]],[[T15]]
; MIPS32: srl [[T17:.*]],a1,0x18
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: srl [[T11]],[[T11]],0x18
; MIPS32: movn [[T11]],[[T7]],[[T17]]
; MIPS32: srl [[T11]],[[T11]],0x18
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xff
; MIPS32: andi [[T8]],[[T5]],0xff
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: srl [[T9]],[[T9]],0x8
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T0]],a1,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x8
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T9]],[[T5]],0x8
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: movn [[T9]],[[T15]],[[T0]]
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T8]],[[T8]],[[T0]]
; MIPS32: or [[T9]],[[T9]],[[T8]]
; MIPS32: srl [[T0]],a1,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T8]],[[T5]],0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T9]],[[T9]],[[T0]]
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x18
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x18
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xff
; MIPS32: andi [[T15]],[[T6]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T10]],[[T10]],0x8
; MIPS32: sll [[T10]],[[T10]],0x8
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T0]],a2,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T16]],[[T6]],0x8
; MIPS32: or [[T11]],[[T11]],[[T14]]
; MIPS32: move [[T6]],a2
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: move [[T16]],[[T12]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: srl [[T5]],[[T5]],0x8
; MIPS32: sll [[T5]],[[T5]],0x8
; MIPS32: or [[T16]],[[T16]],[[T5]]
; MIPS32: move [[T6]],a2
; MIPS32: srl [[T6]],[[T6]],0x8
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: srl [[T7]],[[T7]],0x8
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: move [[T17]],[[T12]]
; MIPS32: srl [[T17]],[[T17]],0x8
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: movn [[T17]],[[T7]],[[T6]]
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: sll [[T17]],[[T17]],0x8
; MIPS32: lui [[T6]],0xffff
; MIPS32: ori [[T6]],[[T6]],0xff
; MIPS32: and [[T16]],[[T16]],[[T6]]
; MIPS32: or [[T17]],[[T17]],[[T16]]
; MIPS32: move [[T6]],a2
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: move [[T16]],[[T12]]
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: lui [[T6]],0xff00
; MIPS32: ori [[T6]],[[T6]],0xffff
; MIPS32: and [[T17]],[[T17]],[[T6]]
; MIPS32: or [[T16]],[[T16]],[[T17]]
; MIPS32: srl [[T18:.*]],a2,0x18
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T8]],[[T8]],0x18
; MIPS32: srl [[T12]],[[T12]],0x18
; MIPS32: movn [[T12]],[[T8]],[[T18]]
; MIPS32: srl [[T12]],[[T12]],0x18
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a2,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T15]],[[T6]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T17:.*]],a2,0x18
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x18
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xff
; MIPS32: andi [[T15]],[[T7]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T11]],[[T11]],0x8
; MIPS32: sll [[T11]],[[T11]],0x8
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T0]],a3,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T16]],[[T7]],0x8
; MIPS32: srl [[T16]],[[T16]],0x8
; MIPS32: or [[T12]],[[T12]],[[T16]]
; MIPS32: move [[T6]],a3
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: move [[T16]],[[T13]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: srl [[T4]],[[T4]],0x8
; MIPS32: sll [[T4]],[[T4]],0x8
; MIPS32: or [[T16]],[[T16]],[[T4]]
; MIPS32: move [[T6]],a3
; MIPS32: srl [[T6]],[[T6]],0x8
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: srl [[T7]],[[T7]],0x8
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: move [[T17]],[[T13]]
; MIPS32: srl [[T17]],[[T17]],0x8
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: movn [[T17]],[[T7]],[[T6]]
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: sll [[T17]],[[T17]],0x8
; MIPS32: lui [[T6]],0xffff
; MIPS32: ori [[T6]],[[T6]],0xff
; MIPS32: and [[T16]],[[T16]],[[T6]]
; MIPS32: or [[T17]],[[T17]],[[T16]]
; MIPS32: move [[T6]],a3
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: move [[T16]],[[T13]]
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: lui [[T6]],0xff00
; MIPS32: ori [[T6]],[[T6]],0xffff
; MIPS32: and [[T17]],[[T17]],[[T6]]
; MIPS32: or [[T16]],[[T16]],[[T17]]
; MIPS32: srl [[T19:.*]],a3,0x18
; MIPS32: andi [[T19]],[[T19]],0x1
; MIPS32: srl [[T9]],[[T9]],0x18
; MIPS32: srl [[T13]],[[T13]],0x18
; MIPS32: movn [[T13]],[[T9]],[[T19]]
; MIPS32: srl [[T13]],[[T13]],0x18
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a3,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T15]],[[T7]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T18:.*]],a3,0x18
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x18
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
; MIPS32: srl [[T16]],[[T16]],0x8
; MIPS32: or [[T13]],[[T13]],[[T16]]
; MIPS32: move v0,[[T10]]
; MIPS32: move v1,[[T11]]
; MIPS32: move a0,[[T12]]
; MIPS32: move a1,[[T13]]
; MIPS32: lw [[T5]],
; MIPS32: lw [[T4]],
; MIPS32: lw [[T3]],
; MIPS32: lw [[T2]],
; MIPS32: lw [[T1]],
; MIPS32: addiu [[T0]],sp,20
}
define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1,
......@@ -241,234 +293,286 @@ entry:
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v16i1
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xff
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: andi [[T14:.*]],[[T4]],0xff
; MIPS32: addiu [[T0:.*]],sp,-20
; MIPS32: sw [[T1:.*]],
; MIPS32: sw [[T2:.*]],
; MIPS32: sw [[T3:.*]],
; MIPS32: sw [[T4:.*]],
; MIPS32: sw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: lw [[T8:.*]],
; MIPS32: lw [[T9:.*]],
; MIPS32: lw [[T10:.*]],
; MIPS32: lw [[T11:.*]],
; MIPS32: lw [[T12:.*]],
; MIPS32: lw [[T13:.*]],
; MIPS32: move [[T14:.*]],zero
; MIPS32: move [[T15:.*]],zero
; MIPS32: move [[T5]],zero
; MIPS32: move [[T4]],zero
; MIPS32: move [[T3]],a0
; MIPS32: andi [[T3]],[[T3]],0xff
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: move [[T2]],[[T6]]
; MIPS32: andi [[T2]],[[T2]],0xff
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: move [[T1]],[[T10]]
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: movn [[T1]],[[T2]],[[T3]]
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: or [[T1]],[[T1]],[[T14]]
; MIPS32: move [[T14]],a0
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: move [[T3]],[[T6]]
; MIPS32: srl [[T3]],[[T3]],0x8
; MIPS32: andi [[T3]],[[T3]],0xff
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: move [[T2]],[[T10]]
; MIPS32: srl [[T2]],[[T2]],0x8
; MIPS32: andi [[T2]],[[T2]],0xff
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: movn [[T2]],[[T3]],[[T14]]
; MIPS32: andi [[T2]],[[T2]],0xff
; MIPS32: sll [[T2]],[[T2]],0x8
; MIPS32: lui [[T14]],0xffff
; MIPS32: ori [[T14]],[[T14]],0xff
; MIPS32: and [[T1]],[[T1]],[[T14]]
; MIPS32: or [[T2]],[[T2]],[[T1]]
; MIPS32: move [[T14]],a0
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T8]],a0,0x8
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x8
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: srl [[T13]],[[T4]],0x8
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: movn [[T13]],[[T12]],[[T8]]
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: sll [[T13]],[[T13]],0x8
; MIPS32: lui [[T8]],0xffff
; MIPS32: ori [[T8]],[[T8]],0xff
; MIPS32: and [[T14]],[[T14]],[[T8]]
; MIPS32: or [[T13]],[[T13]],[[T14]]
; MIPS32: srl [[T8]],a0,0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x10
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: srl [[T14]],[[T4]],0x10
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: move [[T3]],[[T6]]
; MIPS32: srl [[T3]],[[T3]],0x10
; MIPS32: andi [[T3]],[[T3]],0xff
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: move [[T1]],[[T10]]
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: movn [[T1]],[[T3]],[[T14]]
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: sll [[T1]],[[T1]],0x10
; MIPS32: lui [[T14]],0xff00
; MIPS32: ori [[T14]],[[T14]],0xffff
; MIPS32: and [[T2]],[[T2]],[[T14]]
; MIPS32: or [[T1]],[[T1]],[[T2]]
; MIPS32: srl [[T16:.*]],a0,0x18
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: srl [[T10]],[[T10]],0x18
; MIPS32: andi [[T10]],[[T10]],0x1
; MIPS32: movn [[T10]],[[T6]],[[T16]]
; MIPS32: srl [[T10]],[[T10]],0x18
; MIPS32: sll [[T1]],[[T1]],0x8
; MIPS32: srl [[T1]],[[T1]],0x8
; MIPS32: or [[T10]],[[T10]],[[T1]]
; MIPS32: move [[T6]],a1
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: move [[T14]],[[T11]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T12]],[[T8]]
; MIPS32: movn [[T14]],[[T16]],[[T6]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: lui [[T8]],0xff00
; MIPS32: ori [[T8]],[[T8]],0xffff
; MIPS32: and [[T13]],[[T13]],[[T8]]
; MIPS32: or [[T14]],[[T14]],[[T13]]
; MIPS32: srl [[T15:.*]],a0,0x18
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x18
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: andi [[T4]],[[T4]],0x1
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: andi [[T8]],[[T5]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: srl [[T9]],[[T9]],0x8
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T0]],a1,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: or [[T14]],[[T14]],[[T15]]
; MIPS32: move [[T6]],a1
; MIPS32: srl [[T6]],[[T6]],0x8
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: srl [[T16]],[[T16]],0x8
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: move [[T15]],[[T11]]
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T9]],[[T5]],0x8
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: andi [[T9]],[[T9]],0x1
; MIPS32: movn [[T9]],[[T15]],[[T0]]
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T8]],[[T8]],[[T0]]
; MIPS32: or [[T9]],[[T9]],[[T8]]
; MIPS32: srl [[T0]],a1,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x10
; MIPS32: movn [[T15]],[[T16]],[[T6]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T8]],[[T5]],0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T9]],[[T9]],[[T0]]
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: lui [[T6]],0xffff
; MIPS32: ori [[T6]],[[T6]],0xff
; MIPS32: and [[T14]],[[T14]],[[T6]]
; MIPS32: or [[T15]],[[T15]],[[T14]]
; MIPS32: move [[T6]],a1
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x18
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: andi [[T5]],[[T5]],0x1
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T6]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T10]],[[T10]],0x8
; MIPS32: sll [[T10]],[[T10]],0x8
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T0]],a2,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T16]],[[T6]],0x8
; MIPS32: move [[T14]],[[T11]]
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T16]],[[T6]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: lui [[T6]],0xff00
; MIPS32: ori [[T6]],[[T6]],0xffff
; MIPS32: and [[T15]],[[T15]],[[T6]]
; MIPS32: or [[T14]],[[T14]],[[T15]]
; MIPS32: srl [[T17:.*]],a1,0x18
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: srl [[T11]],[[T11]],0x18
; MIPS32: andi [[T11]],[[T11]],0x1
; MIPS32: movn [[T11]],[[T7]],[[T17]]
; MIPS32: srl [[T11]],[[T11]],0x18
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: or [[T11]],[[T11]],[[T14]]
; MIPS32: move [[T6]],a2
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: move [[T16]],[[T12]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a2,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T15]],[[T6]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T17:.*]],a2,0x18
; MIPS32: srl [[T5]],[[T5]],0x8
; MIPS32: sll [[T5]],[[T5]],0x8
; MIPS32: or [[T16]],[[T16]],[[T5]]
; MIPS32: move [[T6]],a2
; MIPS32: srl [[T6]],[[T6]],0x8
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: srl [[T7]],[[T7]],0x8
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: move [[T17]],[[T12]]
; MIPS32: srl [[T17]],[[T17]],0x8
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x18
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: movn [[T17]],[[T7]],[[T6]]
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: sll [[T17]],[[T17]],0x8
; MIPS32: lui [[T6]],0xffff
; MIPS32: ori [[T6]],[[T6]],0xff
; MIPS32: and [[T16]],[[T16]],[[T6]]
; MIPS32: or [[T17]],[[T17]],[[T16]]
; MIPS32: move [[T6]],a2
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T7]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T11]],[[T11]],0x8
; MIPS32: sll [[T11]],[[T11]],0x8
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T0]],a3,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T16]],[[T7]],0x8
; MIPS32: move [[T7]],[[T8]]
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: move [[T16]],[[T12]]
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a3,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T15]],[[T7]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T18:.*]],a3,0x18
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: lui [[T6]],0xff00
; MIPS32: ori [[T6]],[[T6]],0xffff
; MIPS32: and [[T17]],[[T17]],[[T6]]
; MIPS32: or [[T16]],[[T16]],[[T17]]
; MIPS32: srl [[T18:.*]],a2,0x18
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x18
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: srl [[T8]],[[T8]],0x18
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T12]],0x18
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: movn [[T12]],[[T8]],[[T18]]
; MIPS32: srl [[T12]],[[T12]],0x18
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: srl [[T16]],[[T16]],0x8
; MIPS32: or [[T12]],[[T12]],[[T16]]
; MIPS32: move [[T6]],a3
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
; MIPS32: move [[T16]],[[T13]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: srl [[T4]],[[T4]],0x8
; MIPS32: sll [[T4]],[[T4]],0x8
; MIPS32: or [[T16]],[[T16]],[[T4]]
; MIPS32: move [[T6]],a3
; MIPS32: srl [[T6]],[[T6]],0x8
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: srl [[T7]],[[T7]],0x8
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: move [[T17]],[[T13]]
; MIPS32: srl [[T17]],[[T17]],0x8
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: movn [[T17]],[[T7]],[[T6]]
; MIPS32: andi [[T17]],[[T17]],0xff
; MIPS32: sll [[T17]],[[T17]],0x8
; MIPS32: lui [[T6]],0xffff
; MIPS32: ori [[T6]],[[T6]],0xff
; MIPS32: and [[T16]],[[T16]],[[T6]]
; MIPS32: or [[T17]],[[T17]],[[T16]]
; MIPS32: move [[T6]],a3
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0xff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: andi [[T7]],[[T7]],0xff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: move [[T16]],[[T13]]
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: lui [[T6]],0xff00
; MIPS32: ori [[T6]],[[T6]],0xffff
; MIPS32: and [[T17]],[[T17]],[[T6]]
; MIPS32: or [[T16]],[[T16]],[[T17]]
; MIPS32: srl [[T19:.*]],a3,0x18
; MIPS32: andi [[T19]],[[T19]],0x1
; MIPS32: srl [[T9]],[[T9]],0x18
; MIPS32: andi [[T9]],[[T9]],0x1
; MIPS32: srl [[T13]],[[T13]],0x18
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: movn [[T13]],[[T9]],[[T19]]
; MIPS32: srl [[T13]],[[T13]],0x18
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: srl [[T16]],[[T16]],0x8
; MIPS32: or [[T13]],[[T13]],[[T16]]
; MIPS32: move v0,[[T10]]
; MIPS32: move v1,[[T11]]
; MIPS32: move a0,[[T12]]
; MIPS32: move a1,[[T13]]
; MIPS32: lw [[T5]],
; MIPS32: lw [[T4]],
; MIPS32: lw [[T3]],
; MIPS32: lw [[T2]],
; MIPS32: lw [[T1]],
; MIPS32: addiu [[T0]],sp,20
}
define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1,
......@@ -485,90 +589,118 @@ entry:
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v8i16
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xffff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xffff
; MIPS32: andi [[T14:.*]],[[T4]],0xffff
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T15:.*]],a0,0x10
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x10
; MIPS32: srl [[T4]],[[T4]],0x10
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: sll [[T4]],[[T4]],0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: addiu [[T0:.*]],sp,-20
; MIPS32: sw [[T1:.*]],
; MIPS32: sw [[T2:.*]],
; MIPS32: sw [[T3:.*]],
; MIPS32: sw [[T4:.*]],
; MIPS32: sw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: lw [[T8:.*]],
; MIPS32: lw [[T9:.*]],
; MIPS32: lw [[T10:.*]],
; MIPS32: lw [[T11:.*]],
; MIPS32: lw [[T12:.*]],
; MIPS32: lw [[T13:.*]],
; MIPS32: move [[T14:.*]],zero
; MIPS32: move [[T15:.*]],zero
; MIPS32: move [[T5]],zero
; MIPS32: move [[T4]],zero
; MIPS32: move [[T3]],a0
; MIPS32: andi [[T3]],[[T3]],0xffff
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: move [[T2]],[[T6]]
; MIPS32: andi [[T2]],[[T2]],0xffff
; MIPS32: move [[T1]],[[T10]]
; MIPS32: andi [[T1]],[[T1]],0xffff
; MIPS32: movn [[T1]],[[T2]],[[T3]]
; MIPS32: andi [[T1]],[[T1]],0xffff
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xffff
; MIPS32: andi [[T8]],[[T5]],0xffff
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xffff
; MIPS32: srl [[T9]],[[T9]],0x10
; MIPS32: sll [[T9]],[[T9]],0x10
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: or [[T1]],[[T1]],[[T14]]
; MIPS32: srl [[T16:.*]],a0,0x10
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: srl [[T5]],[[T5]],0x10
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: sll [[T5]],[[T5]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xffff
; MIPS32: andi [[T15]],[[T6]],0xffff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: srl [[T10]],[[T10]],0x10
; MIPS32: movn [[T10]],[[T6]],[[T16]]
; MIPS32: sll [[T10]],[[T10]],0x10
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T17:.*]],a2,0x10
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x10
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: sll [[T6]],[[T6]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: sll [[T1]],[[T1]],0x10
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: or [[T10]],[[T10]],[[T1]]
; MIPS32: move [[T6]],a1
; MIPS32: andi [[T6]],[[T6]],0xffff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T16]],[[T7]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: move [[T14]],[[T11]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: movn [[T14]],[[T16]],[[T6]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xffff
; MIPS32: andi [[T15]],[[T7]],0xffff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: or [[T14]],[[T14]],[[T15]]
; MIPS32: srl [[T17:.*]],a1,0x10
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: srl [[T11]],[[T11]],0x10
; MIPS32: movn [[T11]],[[T7]],[[T17]]
; MIPS32: sll [[T11]],[[T11]],0x10
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T18:.*]],a3,0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: or [[T11]],[[T11]],[[T14]]
; MIPS32: move [[T6]],a2
; MIPS32: andi [[T6]],[[T6]],0xffff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: andi [[T7]],[[T7]],0xffff
; MIPS32: move [[T16]],[[T12]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: srl [[T5]],[[T5]],0x10
; MIPS32: sll [[T5]],[[T5]],0x10
; MIPS32: or [[T16]],[[T16]],[[T5]]
; MIPS32: srl [[T18:.*]],a2,0x10
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x10
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: sll [[T7]],[[T7]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: srl [[T12]],[[T12]],0x10
; MIPS32: movn [[T12]],[[T8]],[[T18]]
; MIPS32: sll [[T12]],[[T12]],0x10
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: or [[T12]],[[T12]],[[T16]]
; MIPS32: move [[T6]],a3
; MIPS32: andi [[T6]],[[T6]],0xffff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: andi [[T7]],[[T7]],0xffff
; MIPS32: move [[T16]],[[T13]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: srl [[T4]],[[T4]],0x10
; MIPS32: sll [[T4]],[[T4]],0x10
; MIPS32: or [[T16]],[[T16]],[[T4]]
; MIPS32: srl [[T19:.*]],a3,0x10
; MIPS32: andi [[T19]],[[T19]],0x1
; MIPS32: srl [[T9]],[[T9]],0x10
; MIPS32: srl [[T13]],[[T13]],0x10
; MIPS32: movn [[T13]],[[T9]],[[T19]]
; MIPS32: sll [[T13]],[[T13]],0x10
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: or [[T13]],[[T13]],[[T16]]
; MIPS32: move v0,[[T10]]
; MIPS32: move v1,[[T11]]
; MIPS32: move a0,[[T12]]
; MIPS32: move a1,[[T13]]
; MIPS32: lw [[T5]],
; MIPS32: lw [[T4]],
; MIPS32: lw [[T3]],
; MIPS32: lw [[T2]],
; MIPS32: lw [[T1]],
; MIPS32: addiu [[T0]],sp,20
}
define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1,
......@@ -585,106 +717,134 @@ entry:
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v8i1
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xffff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xffff
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: andi [[T14:.*]],[[T4]],0xffff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T15:.*]],a0,0x10
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x10
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T4]],[[T4]],0x10
; MIPS32: andi [[T4]],[[T4]],0x1
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: sll [[T4]],[[T4]],0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: addiu [[T0:.*]],sp,-20
; MIPS32: sw [[T1:.*]],
; MIPS32: sw [[T2:.*]],
; MIPS32: sw [[T3:.*]],
; MIPS32: sw [[T4:.*]],
; MIPS32: sw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: lw [[T8:.*]],
; MIPS32: lw [[T9:.*]],
; MIPS32: lw [[T10:.*]],
; MIPS32: lw [[T11:.*]],
; MIPS32: lw [[T12:.*]],
; MIPS32: lw [[T13:.*]],
; MIPS32: move [[T14:.*]],zero
; MIPS32: move [[T15:.*]],zero
; MIPS32: move [[T5]],zero
; MIPS32: move [[T4]],zero
; MIPS32: move [[T3]],a0
; MIPS32: andi [[T3]],[[T3]],0xffff
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: move [[T2]],[[T6]]
; MIPS32: andi [[T2]],[[T2]],0xffff
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: move [[T1]],[[T10]]
; MIPS32: andi [[T1]],[[T1]],0xffff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: movn [[T1]],[[T2]],[[T3]]
; MIPS32: andi [[T1]],[[T1]],0xffff
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xffff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: andi [[T8]],[[T5]],0xffff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xffff
; MIPS32: srl [[T9]],[[T9]],0x10
; MIPS32: sll [[T9]],[[T9]],0x10
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: or [[T1]],[[T1]],[[T14]]
; MIPS32: srl [[T16:.*]],a0,0x10
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T5]],[[T5]],0x10
; MIPS32: andi [[T5]],[[T5]],0x1
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: sll [[T5]],[[T5]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xffff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T6]],0xffff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: srl [[T10]],[[T10]],0x10
; MIPS32: andi [[T10]],[[T10]],0x1
; MIPS32: movn [[T10]],[[T6]],[[T16]]
; MIPS32: sll [[T10]],[[T10]],0x10
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T17:.*]],a2,0x10
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x10
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: sll [[T1]],[[T1]],0x10
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: or [[T10]],[[T10]],[[T1]]
; MIPS32: move [[T6]],a1
; MIPS32: andi [[T6]],[[T6]],0xffff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: sll [[T6]],[[T6]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: move [[T16]],[[T7]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: move [[T14]],[[T11]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T16]],[[T6]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xffff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T7]],0xffff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: or [[T14]],[[T14]],[[T15]]
; MIPS32: srl [[T17:.*]],a1,0x10
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: srl [[T11]],[[T11]],0x10
; MIPS32: andi [[T11]],[[T11]],0x1
; MIPS32: movn [[T11]],[[T7]],[[T17]]
; MIPS32: sll [[T11]],[[T11]],0x10
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T18:.*]],a3,0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: or [[T11]],[[T11]],[[T14]]
; MIPS32: move [[T6]],a2
; MIPS32: andi [[T6]],[[T6]],0xffff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T8]]
; MIPS32: andi [[T7]],[[T7]],0xffff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: move [[T16]],[[T12]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: srl [[T5]],[[T5]],0x10
; MIPS32: sll [[T5]],[[T5]],0x10
; MIPS32: or [[T16]],[[T16]],[[T5]]
; MIPS32: srl [[T18:.*]],a2,0x10
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x10
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T12]],0x10
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: movn [[T12]],[[T8]],[[T18]]
; MIPS32: sll [[T12]],[[T12]],0x10
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: or [[T12]],[[T12]],[[T16]]
; MIPS32: move [[T6]],a3
; MIPS32: andi [[T6]],[[T6]],0xffff
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: move [[T7]],[[T9]]
; MIPS32: andi [[T7]],[[T7]],0xffff
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: sll [[T7]],[[T7]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
; MIPS32: move [[T16]],[[T13]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T7]],[[T6]]
; MIPS32: andi [[T16]],[[T16]],0xffff
; MIPS32: srl [[T4]],[[T4]],0x10
; MIPS32: sll [[T4]],[[T4]],0x10
; MIPS32: or [[T16]],[[T16]],[[T4]]
; MIPS32: srl [[T19:.*]],a3,0x10
; MIPS32: andi [[T19]],[[T19]],0x1
; MIPS32: srl [[T9]],[[T9]],0x10
; MIPS32: andi [[T9]],[[T9]],0x1
; MIPS32: srl [[T13]],[[T13]],0x10
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: movn [[T13]],[[T9]],[[T19]]
; MIPS32: sll [[T13]],[[T13]],0x10
; MIPS32: sll [[T16]],[[T16]],0x10
; MIPS32: srl [[T16]],[[T16]],0x10
; MIPS32: or [[T13]],[[T13]],[[T16]]
; MIPS32: move v0,[[T10]]
; MIPS32: move v1,[[T11]]
; MIPS32: move a0,[[T12]]
; MIPS32: move a1,[[T13]]
; MIPS32: lw [[T5]],
; MIPS32: lw [[T4]],
; MIPS32: lw [[T3]],
; MIPS32: lw [[T2]],
; MIPS32: lw [[T1]],
; MIPS32: addiu [[T0]],sp,20
}
define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1,
......@@ -702,14 +862,14 @@ entry:
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v4i32
; MIPS32: lw [[T0:.*]],16(sp)
; MIPS32: lw [[T1:.*]],20(sp)
; MIPS32: lw [[T2:.*]],24(sp)
; MIPS32: lw [[T3:.*]],28(sp)
; MIPS32: lw [[T4:.*]],32(sp)
; MIPS32: lw [[T5:.*]],36(sp)
; MIPS32: lw [[T6:.*]],40(sp)
; MIPS32: lw [[T7:.*]],44(sp)
; MIPS32: lw [[T0:.*]],
; MIPS32: lw [[T1:.*]],
; MIPS32: lw [[T2:.*]],
; MIPS32: lw [[T3:.*]],
; MIPS32: lw [[T4:.*]],
; MIPS32: lw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: andi [[T8:.*]],a0,0x1
; MIPS32: movn [[T4]],[[T0]],[[T8]]
; MIPS32: andi [[T9:.*]],a1,0x1
......@@ -739,41 +899,41 @@ entry:
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v4f32
; MIPS32: lw [[T0:.*]],16(sp)
; MIPS32: lw [[T1:.*]],20(sp)
; MIPS32: lw [[T2:.*]],24(sp)
; MIPS32: lw [[T3:.*]],28(sp)
; MIPS32: lw [[T4:.*]],32(sp)
; MIPS32: lw [[T5:.*]],36(sp)
; MIPS32: lw [[T6:.*]],40(sp)
; MIPS32: lw [[T7:.*]],44(sp)
; MIPS32: lw [[T8:.*]],48(sp)
; MIPS32: lw [[T9:.*]],52(sp)
; MIPS32: lw [[T0:.*]],
; MIPS32: lw [[T1:.*]],
; MIPS32: lw [[T2:.*]],
; MIPS32: lw [[T3:.*]],
; MIPS32: lw [[T4:.*]],
; MIPS32: lw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: lw [[T8:.*]],
; MIPS32: lw [[T9:.*]],
; MIPS32: andi [[T10:.*]],a2,0x1
; MIPS32: mtc1 [[T2]],[[F0:.*]]
; MIPS32: mtc1 [[T6]],[[F1:.*]]
; MIPS32: movn.s [[T11:.*]],[[F0]],[[T10]]
; MIPS32: mfc1 v0,[[T11]]
; MIPS32: mtc1 [[T2]],$f0
; MIPS32: mtc1 [[T6]],$f1
; MIPS32: movn.s [[T11:.*]],$f0,[[T10]]
; MIPS32: mfc1 [[T2]],[[T11]]
; MIPS32: andi [[T12:.*]],a3,0x1
; MIPS32: mtc1 [[T3]],[[F0]]
; MIPS32: mtc1 [[T3]],$f0
; MIPS32: mtc1 [[T7]],[[T11]]
; MIPS32: movn.s [[T11]],[[F0]],[[T12]]
; MIPS32: mfc1 v1,[[T11]]
; MIPS32: movn.s [[T11]],$f0,[[T12]]
; MIPS32: mfc1 [[T3]],[[T11]]
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: mtc1 [[T4]],[[F0]]
; MIPS32: mtc1 [[T4]],$f0
; MIPS32: mtc1 [[T8]],[[T11]]
; MIPS32: movn.s [[T11]],[[F0]],[[T0]]
; MIPS32: mfc1 a1,[[T11]]
; MIPS32: movn.s [[T11]],$f0,[[T0]]
; MIPS32: mfc1 [[T4]],[[T11]]
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: mtc1 [[T5]],[[F0]]
; MIPS32: mtc1 [[T5]],$f0
; MIPS32: mtc1 [[T9]],[[T11]]
; MIPS32: movn.s [[T11]],[[F0]],[[T1]]
; MIPS32: mfc1 a2,[[T11]]
; MIPS32: move [[RET:.*]],a0
; MIPS32: sw v0,0([[RET]])
; MIPS32: sw v1,4([[RET]])
; MIPS32: sw a1,8([[RET]])
; MIPS32: sw a2,12([[RET]])
; MIPS32: movn.s [[T11]],$f0,[[T1]]
; MIPS32: mfc1 [[T10]],[[T11]]
; MIPS32: move [[T12]],a0
; MIPS32: sw [[T2]],0(a3)
; MIPS32: sw v1,4(a3)
; MIPS32: sw a1,8(a3)
; MIPS32: sw [[T10]],12(a3)
; MIPS32: move v0,a0
}
......@@ -792,14 +952,14 @@ entry:
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v4i1
; MIPS32: lw [[T0:.*]],16(sp)
; MIPS32: lw [[T1:.*]],20(sp)
; MIPS32: lw [[T2:.*]],24(sp)
; MIPS32: lw [[T3:.*]],28(sp)
; MIPS32: lw [[T4:.*]],32(sp)
; MIPS32: lw [[T5:.*]],36(sp)
; MIPS32: lw [[T6:.*]],40(sp)
; MIPS32: lw [[T7:.*]],44(sp)
; MIPS32: lw [[T0:.*]],
; MIPS32: lw [[T1:.*]],
; MIPS32: lw [[T2:.*]],
; MIPS32: lw [[T3:.*]],
; MIPS32: lw [[T4:.*]],
; MIPS32: lw [[T5:.*]],
; MIPS32: lw [[T6:.*]],
; MIPS32: lw [[T7:.*]],
; MIPS32: andi [[T8:.*]],a0,0x1
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T4]],[[T4]],0x1
......
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