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Commit 175cb138 by Srdjan Obucina Committed by Jim Stichnoth
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Subzero, MIPS32: Intrinsic call Bswap for i16, i32 and i64

Implements intrinsic call llvm.bswap for i16, i32 and i64 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2368343003 . Patch from Srdjan Obucina <Srdjan.Obucina@imgtec.com>.
parent 6fd9c0e3
Showing with 616 additions and 1 deletion
src/IceInstMIPS32.h
......@@ -1271,6 +1271,7 @@ template <> void InstMIPS32Div::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Div_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Div_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Lui::emit(const Cfg *Func) const;
template <> void InstMIPS32Lui::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Lw::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mfc1::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mflo::emit(const Cfg *Func) const;
......
src/IceTargetLoweringMIPS32.cpp
......@@ -3049,7 +3049,96 @@ void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
return;
}
case Intrinsics::Bswap: {
UnimplementedLoweringError(this, Instr);
auto *Src = Instr->getArg(0);
const Type SrcTy = Src->getType();
assert(SrcTy == IceType_i16 || SrcTy == IceType_i32 ||
SrcTy == IceType_i64);
switch (SrcTy) {
case IceType_i16: {
auto *T1 = I32Reg();
auto *T2 = I32Reg();
auto *T3 = I32Reg();
auto *T4 = I32Reg();
auto *SrcR = legalizeToReg(Src);
_sll(T1, SrcR, 8);
_lui(T2, Ctx->getConstantInt32(255));
_and(T1, T1, T2);
_sll(T3, SrcR, 24);
_or(T1, T3, T1);
_srl(T4, T1, 16);
_mov(Dest, T4);
return;
}
case IceType_i32: {
auto *T1 = I32Reg();
auto *T2 = I32Reg();
auto *T3 = I32Reg();
auto *T4 = I32Reg();
auto *T5 = I32Reg();
auto *SrcR = legalizeToReg(Src);
_srl(T1, SrcR, 24);
_srl(T2, SrcR, 8);
_andi(T2, T2, 0xFF00);
_or(T1, T2, T1);
_sll(T4, SrcR, 8);
_lui(T3, Ctx->getConstantInt32(255));
_and(T4, T4, T3);
_sll(T5, SrcR, 24);
_or(T4, T5, T4);
_or(T4, T4, T1);
_mov(Dest, T4);
return;
}
case IceType_i64: {
auto *T1 = I32Reg();
auto *T2 = I32Reg();
auto *T3 = I32Reg();
auto *T4 = I32Reg();
auto *T5 = I32Reg();
auto *T6 = I32Reg();
auto *T7 = I32Reg();
auto *T8 = I32Reg();
auto *T9 = I32Reg();
auto *T10 = I32Reg();
auto *T11 = I32Reg();
auto *T12 = I32Reg();
auto *T13 = I32Reg();
auto *T14 = I32Reg();
auto *T15 = I32Reg();
auto *T16 = I32Reg();
auto *T17 = I32Reg();
auto *T18 = I32Reg();
auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
Src = legalizeUndef(Src);
auto *SrcLoR = legalizeToReg(loOperand(Src));
auto *SrcHiR = legalizeToReg(hiOperand(Src));
_sll(T1, SrcHiR, 8);
_srl(T2, SrcHiR, 24);
_srl(T3, SrcHiR, 8);
_andi(T3, T3, 0xFF00);
_lui(T4, Ctx->getConstantInt32(255));
_or(T5, T3, T2);
_and(T6, T1, T4);
_sll(T7, SrcHiR, 24);
_or(T8, T7, T6);
_srl(T9, SrcLoR, 24);
_srl(T10, SrcLoR, 8);
_andi(T11, T10, 0xFF00);
_or(T12, T8, T5);
_or(T13, T11, T9);
_sll(T14, SrcLoR, 8);
_and(T15, T14, T4);
_sll(T16, SrcLoR, 24);
_or(T17, T16, T15);
_or(T18, T17, T13);
_mov(DestLo, T12);
_mov(DestHi, T18);
return;
}
default:
llvm::report_fatal_error("Control flow should never have reached here.");
}
return;
}
case Intrinsics::Ctpop: {
......
tests_lit/assembler/mips32/encoding_intrinsics.ll
......@@ -22,12 +22,478 @@
; RUN: --args -O2 --allow-externally-defined-symbols --skip-unimplemented \
; RUN: | FileCheck %s --check-prefix=DIS
declare i16 @llvm.bswap.i16(i16)
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)
declare i32 @llvm.ctlz.i32(i32, i1)
declare i64 @llvm.ctlz.i64(i64, i1)
declare i32 @llvm.cttz.i32(i32, i1)
declare i64 @llvm.cttz.i64(i64, i1)
declare void @llvm.trap()
define internal i32 @encBswap16(i32 %x) {
entry:
%x_trunc = trunc i32 %x to i16
%r = call i16 @llvm.bswap.i16(i16 %x_trunc)
%r_zext = zext i16 %r to i32
ret i32 %r_zext
}
; ASM-LABEL: encBswap16
; ASM-NEXT: .LencBswap16$entry:
; ASM-NEXT: sll $v0, $a0, 8
; ASM-NEXT: lui $v1, 255
; ASM-NEXT: and $v0, $v0, $v1
; ASM-NEXT: sll $a0, $a0, 24
; ASM-NEXT: or $v0, $a0, $v0
; ASM-NEXT: srl $v0, $v0, 16
; ASM-NEXT: andi $v0, $v0, 65535
; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap16>:
; DIS-NEXT: {{.*}} 00041200 sll v0,a0,0x8
; DIS-NEXT: {{.*}} 3c0300ff lui v1,0xff
; DIS-NEXT: {{.*}} 00431024 and v0,v0,v1
; DIS-NEXT: {{.*}} 00042600 sll a0,a0,0x18
; DIS-NEXT: {{.*}} 00821025 or v0,a0,v0
; DIS-NEXT: {{.*}} 00021402 srl v0,v0,0x10
; DIS-NEXT: {{.*}} 3042ffff andi v0,v0,0xffff
; DIS-NEXT: {{.*}} 03e00008 jr ra
; IASM-LABEL: encBswap16
; IASM-NEXT: .LencBswap16$entry:
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x12
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x3c
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x43
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x26
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x82
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x42
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x3
define internal i32 @encBswap32(i32 %x) {
entry:
%r = call i32 @llvm.bswap.i32(i32 %x)
ret i32 %r
}
; ASM-LABEL: encBswap32
; ASM-NEXT: .LencBswap32$entry:
; ASM-NEXT: srl $v0, $a0, 24
; ASM-NEXT: srl $v1, $a0, 8
; ASM-NEXT: andi $v1, $v1, 65280
; ASM-NEXT: or $v0, $v1, $v0
; ASM-NEXT: sll $v1, $a0, 8
; ASM-NEXT: lui $a1, 255
; ASM-NEXT: and $v1, $v1, $a1
; ASM-NEXT: sll $a0, $a0, 24
; ASM-NEXT: or $v1, $a0, $v1
; ASM-NEXT: or $v1, $v1, $v0
; ASM-NEXT: move $v0, $v1
; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap32>:
; DIS-NEXT: {{.*}} 00041602 srl v0,a0,0x18
; DIS-NEXT: {{.*}} 00041a02 srl v1,a0,0x8
; DIS-NEXT: {{.*}} 3063ff00 andi v1,v1,0xff00
; DIS-NEXT: {{.*}} 00621025 or v0,v1,v0
; DIS-NEXT: {{.*}} 00041a00 sll v1,a0,0x8
; DIS-NEXT: {{.*}} 3c0500ff lui a1,0xff
; DIS-NEXT: {{.*}} 00651824 and v1,v1,a1
; DIS-NEXT: {{.*}} 00042600 sll a0,a0,0x18
; DIS-NEXT: {{.*}} 00831825 or v1,a0,v1
; DIS-NEXT: {{.*}} 00621825 or v1,v1,v0
; DIS-NEXT: {{.*}} 00601021 move v0,v1
; DIS-NEXT: {{.*}} 03e00008 jr ra
; IASM-LABEL: encBswap32
; IASM-NEXT: .LencBswap32$entry:
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x16
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x1a
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x63
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x62
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x1a
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x5
; IASM-NEXT: .byte 0x3c
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x65
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x26
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x83
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x62
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x60
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x3
define internal i64 @encBswap64(i64 %x) {
entry:
%r = call i64 @llvm.bswap.i64(i64 %x)
ret i64 %r
}
; ASM-LABEL: encBswap64
; ASM-NEXT: .LencBswap64$entry:
; ASM-NEXT: sll $v0, $a1, 8
; ASM-NEXT: srl $v1, $a1, 24
; ASM-NEXT: srl $a2, $a1, 8
; ASM-NEXT: andi $a2, $a2, 65280
; ASM-NEXT: lui $a3, 255
; ASM-NEXT: or $a2, $a2, $v1
; ASM-NEXT: and $v0, $v0, $a3
; ASM-NEXT: sll $a1, $a1, 24
; ASM-NEXT: or $a1, $a1, $v0
; ASM-NEXT: srl $v0, $a0, 24
; ASM-NEXT: srl $v1, $a0, 8
; ASM-NEXT: andi $v1, $v1, 65280
; ASM-NEXT: or $a1, $a1, $a2
; ASM-NEXT: or $v1, $v1, $v0
; ASM-NEXT: sll $v0, $a0, 8
; ASM-NEXT: and $v0, $v0, $a3
; ASM-NEXT: sll $a0, $a0, 24
; ASM-NEXT: or $a0, $a0, $v0
; ASM-NEXT: or $a0, $a0, $v1
; ASM-NEXT: move $v0, $a1
; ASM-NEXT: move $v1, $a0
; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap64>:
; DIS-NEXT: {{.*}} 00051200 sll v0,a1,0x8
; DIS-NEXT: {{.*}} 00051e02 srl v1,a1,0x18
; DIS-NEXT: {{.*}} 00053202 srl a2,a1,0x8
; DIS-NEXT: {{.*}} 30c6ff00 andi a2,a2,0xff00
; DIS-NEXT: {{.*}} 3c0700ff lui a3,0xff
; DIS-NEXT: {{.*}} 00c33025 or a2,a2,v1
; DIS-NEXT: {{.*}} 00471024 and v0,v0,a3
; DIS-NEXT: {{.*}} 00052e00 sll a1,a1,0x18
; DIS-NEXT: {{.*}} 00a22825 or a1,a1,v0
; DIS-NEXT: {{.*}} 00041602 srl v0,a0,0x18
; DIS-NEXT: {{.*}} 00041a02 srl v1,a0,0x8
; DIS-NEXT: {{.*}} 3063ff00 andi v1,v1,0xff00
; DIS-NEXT: {{.*}} 00a62825 or a1,a1,a2
; DIS-NEXT: {{.*}} 00621825 or v1,v1,v0
; DIS-NEXT: {{.*}} 00041200 sll v0,a0,0x8
; DIS-NEXT: {{.*}} 00471024 and v0,v0,a3
; DIS-NEXT: {{.*}} 00042600 sll a0,a0,0x18
; DIS-NEXT: {{.*}} 00822025 or a0,a0,v0
; DIS-NEXT: {{.*}} 00832025 or a0,a0,v1
; DIS-NEXT: {{.*}} 00a01021 move v0,a1
; DIS-NEXT: {{.*}} 00801821 move v1,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra
; IASM-LABEL: encBswap64
; IASM-NEXT: .LencBswap64$entry:
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x12
; IASM-NEXT: .byte 0x5
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x1e
; IASM-NEXT: .byte 0x5
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x32
; IASM-NEXT: .byte 0x5
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0xc6
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x7
; IASM-NEXT: .byte 0x3c
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0xc3
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x47
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x5
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x28
; IASM-NEXT: .byte 0xa2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x16
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x1a
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x63
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x28
; IASM-NEXT: .byte 0xa6
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x62
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x12
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x47
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x26
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x82
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x83
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x3
define internal i64 @encBswap64Undef() {
entry:
%r = call i64 @llvm.bswap.i64(i64 undef)
ret i64 %r
}
; ASM-LABEL: encBswap64Undef
; ASM-NEXT: .LencBswap64Undef$entry:
; ASM-NEXT: # $zero = def.pseudo
; ASM-NEXT: addiu $v0, $zero, 0
; ASM-NEXT: # $zero = def.pseudo
; ASM-NEXT: addiu $v1, $zero, 0
; ASM-NEXT: sll $a0, $v1, 8
; ASM-NEXT: srl $a1, $v1, 24
; ASM-NEXT: srl $a2, $v1, 8
; ASM-NEXT: andi $a2, $a2, 65280
; ASM-NEXT: lui $a3, 255
; ASM-NEXT: or $a2, $a2, $a1
; ASM-NEXT: and $a0, $a0, $a3
; ASM-NEXT: sll $v1, $v1, 24
; ASM-NEXT: or $v1, $v1, $a0
; ASM-NEXT: srl $a0, $v0, 24
; ASM-NEXT: srl $a1, $v0, 8
; ASM-NEXT: andi $a1, $a1, 65280
; ASM-NEXT: or $v1, $v1, $a2
; ASM-NEXT: or $a1, $a1, $a0
; ASM-NEXT: sll $a0, $v0, 8
; ASM-NEXT: and $a0, $a0, $a3
; ASM-NEXT: sll $v0, $v0, 24
; ASM-NEXT: or $v0, $v0, $a0
; ASM-NEXT: or $v0, $v0, $a1
; ASM-NEXT: move $a0, $v0
; ASM-NEXT: move $v0, $v1
; ASM-NEXT: move $v1, $a0
; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap64Undef>:
; DIS-NEXT: {{.*}} 24020000 li v0,0
; DIS-NEXT: {{.*}} 24030000 li v1,0
; DIS-NEXT: {{.*}} 00032200 sll a0,v1,0x8
; DIS-NEXT: {{.*}} 00032e02 srl a1,v1,0x18
; DIS-NEXT: {{.*}} 00033202 srl a2,v1,0x8
; DIS-NEXT: {{.*}} 30c6ff00 andi a2,a2,0xff00
; DIS-NEXT: {{.*}} 3c0700ff lui a3,0xff
; DIS-NEXT: {{.*}} 00c53025 or a2,a2,a1
; DIS-NEXT: {{.*}} 00872024 and a0,a0,a3
; DIS-NEXT: {{.*}} 00031e00 sll v1,v1,0x18
; DIS-NEXT: {{.*}} 00641825 or v1,v1,a0
; DIS-NEXT: {{.*}} 00022602 srl a0,v0,0x18
; DIS-NEXT: {{.*}} 00022a02 srl a1,v0,0x8
; DIS-NEXT: {{.*}} 30a5ff00 andi a1,a1,0xff00
; DIS-NEXT: {{.*}} 00661825 or v1,v1,a2
; DIS-NEXT: {{.*}} 00a42825 or a1,a1,a0
; DIS-NEXT: {{.*}} 00022200 sll a0,v0,0x8
; DIS-NEXT: {{.*}} 00872024 and a0,a0,a3
; DIS-NEXT: {{.*}} 00021600 sll v0,v0,0x18
; DIS-NEXT: {{.*}} 00441025 or v0,v0,a0
; DIS-NEXT: {{.*}} 00451025 or v0,v0,a1
; DIS-NEXT: {{.*}} 00402021 move a0,v0
; DIS-NEXT: {{.*}} 00601021 move v0,v1
; DIS-NEXT: {{.*}} 00801821 move v1,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra
; IASM-LABEL: encBswap64Undef
; IASM-NEXT: .LencBswap64Undef$entry:
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x22
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x32
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0xc6
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x7
; IASM-NEXT: .byte 0x3c
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0xc5
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x87
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x1e
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x64
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x26
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x2a
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0xa5
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x66
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x28
; IASM-NEXT: .byte 0xa4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x22
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x87
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x16
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x44
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x25
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x45
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x60
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x3
define internal i32 @encCtlz32(i32 %x) {
entry:
%r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
......
tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
......@@ -353,6 +353,14 @@ entry:
; ARM32-LABEL: test_bswap_16
; ARM32: rev
; ARM32: lsr {{.*}} #16
; MIPS32-LABEL: test_bswap_16
; MIPS32: sll {{.*}},0x8
; MIPS32: lui {{.*}},0xff
; MIPS32: and
; MIPS32: sll {{.*}},0x18
; MIPS32: or
; MIPS32: srl {{.*}},0x10
; MIPS32: andi {{.*}},0xffff
define internal i32 @test_bswap_32(i32 %x) {
entry:
......@@ -363,6 +371,17 @@ entry:
; CHECK: bswap e{{.*}}
; ARM32-LABEL: test_bswap_32
; ARM32: rev
; MIPS32-LABEL: test_bswap_32
; MIPS32: srl {{.*}},0x18
; MIPS32: srl {{.*}},0x8
; MIPS32: andi {{.*}},0xff00
; MIPS32: or
; MIPS32: sll {{.*}},0x8
; MIPS32: lui {{.*}},0xff
; MIPS32: and
; MIPS32: sll {{.*}},0x18
; MIPS32: or
; MIPS32: or
define internal i64 @test_bswap_64(i64 %x) {
entry:
......@@ -375,6 +394,26 @@ entry:
; ARM32-LABEL: test_bswap_64
; ARM32: rev
; ARM32: rev
; MIPS32-LABEL: test_bswap_64
; MIPS32: sll {{.*}},0x8
; MIPS32: srl {{.*}},0x18
; MIPS32: srl {{.*}},0x8
; MIPS32: andi {{.*}},0xff00
; MIPS32: lui {{.*}},0xff
; MIPS32: or
; MIPS32: and
; MIPS32: sll {{.*}},0x18
; MIPS32: or
; MIPS32: srl {{.*}},0x18
; MIPS32: srl {{.*}},0x8
; MIPS32: andi {{.*}},0xff00
; MIPS32: or
; MIPS32: or
; MIPS32: sll {{.*}},0x8
; MIPS32: and
; MIPS32: sll {{.*}},0x18
; MIPS32: or
; MIPS32: or
define internal i64 @test_bswap_64_undef() {
entry:
......@@ -387,6 +426,26 @@ entry:
; ARM32-LABEL: test_bswap_64
; ARM32: rev
; ARM32: rev
; MIPS32-LABEL: test_bswap_64_undef
; MIPS32: sll {{.*}},0x8
; MIPS32: srl {{.*}},0x18
; MIPS32: srl {{.*}},0x8
; MIPS32: andi {{.*}},0xff00
; MIPS32: lui {{.*}},0xff
; MIPS32: or
; MIPS32: and
; MIPS32: sll {{.*}},0x18
; MIPS32: or
; MIPS32: srl {{.*}},0x18
; MIPS32: srl {{.*}},0x8
; MIPS32: andi {{.*}},0xff00
; MIPS32: or
; MIPS32: or
; MIPS32: sll {{.*}},0x8
; MIPS32: and
; MIPS32: sll {{.*}},0x18
; MIPS32: or
; MIPS32: or
define internal i32 @test_ctlz_32(i32 %x) {
entry:
......
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