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Commit 36847bdd by Srdjan Obucina Committed by Jim Stichnoth
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Subzero, MIPS32: Extend InstMIPS32Mov to support different data types

This patch extends InstMIPS32Mov instruction to support different datatypes, and emit proper low level instruction depending on operands properties and data types. R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2122043002 . Patch from Srdjan Obucina <Srdjan.Obucina@imgtec.com>.
parent a7e5a951
Showing with 124 additions and 46 deletions
src/IceInstMIPS32.cpp
......@@ -553,29 +553,107 @@ void InstMIPS32Mov::emitSingleDestSingleSource(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
Variable *Dest = getDest();
Operand *Src = getSrc(0);
auto *S = llvm::dyn_cast<Variable>(Src);
Str << "\t";
if (Dest->hasReg()) {
if (S && S->hasReg())
Str << "move";
else
Str << "lw";
} else {
if (S && S->hasReg()) {
Str << "sw"
auto *SrcV = llvm::dyn_cast<Variable>(Src);
assert(!llvm::isa<Constant>(Src));
const char *ActualOpcode = nullptr;
const bool DestIsReg = Dest->hasReg();
const bool DestIsMem = !Dest->hasReg();
const bool SrcIsReg = (SrcV && SrcV->hasReg());
const bool SrcIsMem = !(SrcV && SrcV->hasReg());
// reg to reg
if (DestIsReg && SrcIsReg) {
switch (Dest->getType()) {
case IceType_f32:
ActualOpcode = "mov.s";
break;
case IceType_f64:
ActualOpcode = "mov.d";
break;
case IceType_i1:
case IceType_i8:
case IceType_i16:
case IceType_i32:
Str << "\t"
"add"
"\t";
getDest()->emit(Func);
Str << ", $zero, ";
getSrc(0)->emit(Func);
return;
default:
UnimplementedError(getFlags());
return;
}
assert(ActualOpcode);
Str << "\t" << ActualOpcode << "\t";
getDest()->emit(Func);
Str << ", ";
getSrc(0)->emit(Func);
return;
}
// reg to stack
if (DestIsMem && SrcIsReg) {
switch (Dest->getType()) {
case IceType_f32:
ActualOpcode = "swc1";
break;
case IceType_f64:
ActualOpcode = "sdc1";
break;
case IceType_i1:
case IceType_i8:
case IceType_i16:
case IceType_i32:
ActualOpcode = "sw";
break;
default:
UnimplementedError(getFlags());
return;
}
assert(ActualOpcode);
Str << "\t" << ActualOpcode << "\t";
getSrc(0)->emit(Func);
Str << ", ";
getDest()->emit(Func);
return;
} else
Str << "move";
}
Str << "\t";
// stack to reg
if (DestIsReg && SrcIsMem) {
switch (Dest->getType()) {
case IceType_f32:
ActualOpcode = "lwc1";
break;
case IceType_f64:
ActualOpcode = "ldc1";
break;
case IceType_i1:
case IceType_i8:
case IceType_i16:
case IceType_i32:
ActualOpcode = "lw";
break;
default:
UnimplementedError(getFlags());
return;
}
assert(ActualOpcode);
Str << "\t" << ActualOpcode << "\t";
getDest()->emit(Func);
Str << ", ";
getSrc(0)->emit(Func);
return;
}
// stack to stack
llvm::report_fatal_error("mov cant copy stack to stack.");
}
} // end of namespace MIPS32
......
tests_lit/llvm2ice_tests/64bit.pnacl.ll
......@@ -47,7 +47,7 @@ entry:
}
; MIPS32-LABEL: ignore64BitArg
; MIPS32: move v0,a2
; MIPS32: add v0,zero,a2
define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) {
entry:
......@@ -203,8 +203,8 @@ entry:
; ARM32: bx lr
; MIPS32-LABEL; return64BitArg
; MIPS32: move v0,a2
; MIPS32: move v1,a3
; MIPS32: add v0,zero,a2
; MIPS32: add v1,zero,a3
; MIPS32: jr ra
define internal i64 @return64BitConst() {
......@@ -800,7 +800,7 @@ entry:
; ARM32: mov r0, r2
; MIPS32-LABEL: trunc64To32Signed
; MIPS32: move v0,a2
; MIPS32: add v0,zero,a2
define internal i32 @trunc64To16Signed(i64 %a) {
entry:
......@@ -822,7 +822,7 @@ entry:
; MIPS32-LABEL: trunc64To16Signed
; MIPS32: sll a0,a0,0x10
; MIPS32: sra a0,a0,0x10
; MIPS32: move v0,a0
; MIPS32: add v0,zero,a0
define internal i32 @trunc64To8Signed(i64 %a) {
entry:
......@@ -844,7 +844,7 @@ entry:
; MIPS32-LABEL: trunc64To8Signed
; MIPS32: sll a0,a0,0x18
; MIPS32: sra a0,a0,0x18
; MIPS32: move v0,a0
; MIPS32: add v0,zero,a0
define internal i32 @trunc64To32SignedConst() {
entry:
......@@ -905,7 +905,7 @@ entry:
; ARM32: mov r0, r2
; MIPS32-LABEL: trunc64To32Unsigned
; MIPS32: move v0,a2
; MIPS32: add v0,zero,a2
define internal i32 @trunc64To16Unsigned(i64 %a) {
entry:
......@@ -926,7 +926,7 @@ entry:
; MIPS32-LABEL: trunc64To16Unsigned
; MIPS32: andi a0,a0,0xffff
; MIPS32: move v0,a0
; MIPS32: add v0,zero,a0
define internal i32 @trunc64To8Unsigned(i64 %a) {
entry:
......@@ -947,7 +947,7 @@ entry:
; MIPS32-LABEL: trunc64To8Unsigned
; MIPS32: andi a0,a0,0xff
; MIPS32: move v0,a0
; MIPS32: add v0,zero,a0
define internal i32 @trunc64To1(i64 %a) {
entry:
......@@ -972,7 +972,7 @@ entry:
; MIPS32-LABEL: trunc64To1
; MIPS32: andi {{.*}},a0,0x1
; MIPS32: move v0,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @sext32To64(i32 %a) {
entry:
......@@ -992,8 +992,8 @@ entry:
; MIPS32-LABEL: sext32To64
; MIPS32-LABEL: sra {{.*}},a0,0x1f
; MIPS32-LABEL: move v1,{{.*}}
; MIPS32-LABEL: move v0,{{.*}}
; MIPS32-LABEL: add v1,{{.*}}
; MIPS32-LABEL: add v0,{{.*}}
define internal i64 @sext16To64(i32 %a) {
entry:
......@@ -1017,8 +1017,8 @@ entry:
; MIPS32: sll {{.*}},{{.*}},0x10
; MIPS32: sra {{.*}},{{.*}},0x10
; MIPS32: sra {{.*}},{{.*}},0x1f
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @sext8To64(i32 %a) {
entry:
......@@ -1042,8 +1042,8 @@ entry:
; MIPS32: sll {{.*}},a0,0x18
; MIPS32: sra {{.*}},{{.*}},0x18
; MIPS32: sra {{.*}},{{.*}},0x1f
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @sext1To64(i32 %a) {
entry:
......@@ -1070,8 +1070,8 @@ entry:
; MIPS32-LABEL: sext1To64
; MIPS32: sll {{.*}},a0,0x1f
; MIPS32: sra {{.*}},{{.*}},0x1f
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @zext32To64(i32 %a) {
entry:
......@@ -1091,8 +1091,8 @@ entry:
; MIPS32-LABEL: zext32To64
; MIPS32: li {{.*}},0
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @zext16To64(i32 %a) {
entry:
......@@ -1115,8 +1115,8 @@ entry:
; MIPS32-LABEL: zext16To64
; MIPS32: andi {{.*}},a0,0xffff
; MIPS32: li {{.*}},0
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @zext8To64(i32 %a) {
entry:
......@@ -1139,8 +1139,8 @@ entry:
; MIPS32-LABEL: zext8To64
; MIPS32: andi {{.*}},a0,0xff
; MIPS32: li {{.*}},0
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal i64 @zext1To64(i32 %a) {
entry:
......@@ -1164,8 +1164,8 @@ entry:
; MIPS32-LABEL: zext1To64
; MIPS32: andi {{.*}},a0,0x1
; MIPS32: li {{.*}},0
; MIPS32: move v1,{{.*}}
; MIPS32: move v0,{{.*}}
; MIPS32: add v1,{{.*}}
; MIPS32: add v0,{{.*}}
define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
......
tests_lit/llvm2ice_tests/int-arg.ll
......@@ -42,7 +42,7 @@ entry:
; ARM32-LABEL: test_returning32_arg0
; ARM32-NEXT: bx lr
; MIPS32-LABEL: test_returning32_arg0
; MIPS32: move v0,a0
; MIPS32: add v0,zero,a0
; MIPS32-NEXT: jr ra
define internal i32 @test_returning32_arg1(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
......@@ -56,7 +56,7 @@ entry:
; ARM32-NEXT: mov r0, r1
; ARM32-NEXT: bx lr
; MIPS32-LABEL: test_returning32_arg1
; MIPS32: move v0,a1
; MIPS32: add v0,zero,a1
; MIPS32-NEXT: jr ra
define internal i32 @test_returning32_arg2(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
......@@ -70,7 +70,7 @@ entry:
; ARM32-NEXT: mov r0, r2
; ARM32-NEXT: bx lr
; MIPS32-LABEL: test_returning32_arg2
; MIPS32: move v0,a2
; MIPS32: add v0,zero,a2
; MIPS32-NEXT: jr ra
......@@ -122,8 +122,8 @@ entry:
; ARM32-LABEL: test_returning64_arg0
; ARM32-NEXT: bx lr
; MIPS32-LABEL: test_returning64_arg0
; MIPS32-NEXT: move v0,a0
; MIPS32-NEXT: move v1,a1
; MIPS32-NEXT: add v0,zero,a0
; MIPS32-NEXT: add v1,zero,a1
define internal i64 @test_returning64_arg1(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
......@@ -139,8 +139,8 @@ entry:
; ARM32-NEXT: mov r1, r3
; ARM32-NEXT: bx lr
; MIPS32-LABEL: test_returning64_arg1
; MIPS32-NEXT: move v0,a2
; MIPS32-NEXT: move v1,a3
; MIPS32-NEXT: add v0,zero,a2
; MIPS32-NEXT: add v1,zero,a3
define internal i64 @test_returning64_arg2(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
entry:
......
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