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Commit 3a01f337 by Jaydeep Patil Committed by Jim Stichnoth
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[SubZero] Implement Fcmp, ICmp, Cast and Select for vector type

The patch scalarizes Fcmp, ICmp, Cast and Select for operands of vector type. R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2412053002 . Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.
parent 45e4d5ed
Showing with 1297 additions and 77 deletions
src/IceOperand.h
......@@ -979,7 +979,7 @@ public:
void setName(const Cfg *Func, const std::string &NewName) override {
Variable::setName(Func, NewName);
if (!Containers.empty()) {
for (SizeT i = 0; i < ElementsPerContainer; ++i) {
for (SizeT i = 0; i < ContainersPerVector; ++i) {
Containers[i]->setName(Func, getName() + "__cont" + std::to_string(i));
}
}
......@@ -995,7 +995,7 @@ public:
const VarList &getContainers() const { return Containers; }
void initVecElement(Cfg *Func) {
for (SizeT i = 0; i < ElementsPerContainer; ++i) {
for (SizeT i = 0; i < ContainersPerVector; ++i) {
Variable *Var = Func->makeVariable(IceType_i32);
Var->setIsArg(getIsArg());
if (BuildDefs::dump()) {
......@@ -1011,13 +1011,13 @@ public:
}
// A 128-bit vector value is mapped onto 4 32-bit register values.
static constexpr SizeT ElementsPerContainer = 4;
static constexpr SizeT ContainersPerVector = 4;
protected:
VariableVecOn32(const Cfg *Func, OperandKind K, Type Ty, SizeT Index)
: Variable(Func, K, Ty, Index) {
assert(typeWidthInBytes(Ty) ==
ElementsPerContainer * typeWidthInBytes(IceType_i32));
ContainersPerVector * typeWidthInBytes(IceType_i32));
}
VarList Containers;
......
src/IceTargetLowering.h
......@@ -511,8 +511,11 @@ protected:
Variable *T = Func->makeVariable(DestTy);
if (auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T)) {
VarVecOn32->initVecElement(Func);
auto *Undef = ConstantUndef::create(Ctx, DestTy);
Context.insert<InstAssign>(T, Undef);
} else {
Context.insert<InstFakeDef>(T);
}
Context.insert<InstFakeDef>(T);
for (SizeT I = 0; I < NumElements; ++I) {
auto *Index = Ctx->getConstantInt32(I);
......
src/IceTargetLoweringMIPS32.cpp
......@@ -238,13 +238,97 @@ uint32_t TargetMIPS32::getCallStackArgumentsSizeBytes(const InstCall *Call) {
void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
constexpr bool NoTailCall = false;
constexpr bool IsTargetHelperCall = true;
Variable *Dest = Instr->getDest();
const Type DestTy = Dest ? Dest->getType() : IceType_void;
switch (Instr->getKind()) {
default:
return;
case Inst::Select: {
if (isVectorType(DestTy)) {
Operand *SrcT = llvm::cast<InstSelect>(Instr)->getTrueOperand();
Operand *SrcF = llvm::cast<InstSelect>(Instr)->getFalseOperand();
Operand *Cond = llvm::cast<InstSelect>(Instr)->getCondition();
Variable *T = Func->makeVariable(DestTy);
auto *Undef = ConstantUndef::create(Ctx, DestTy);
Context.insert<InstAssign>(T, Undef);
auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
VarVecOn32->initVecElement(Func);
for (SizeT I = 0; I < typeNumElements(DestTy); ++I) {
auto *Index = Ctx->getConstantInt32(I);
auto *OpC = Func->makeVariable(typeElementType(Cond->getType()));
Context.insert<InstExtractElement>(OpC, Cond, Index);
auto *OpT = Func->makeVariable(typeElementType(DestTy));
Context.insert<InstExtractElement>(OpT, SrcT, Index);
auto *OpF = Func->makeVariable(typeElementType(DestTy));
Context.insert<InstExtractElement>(OpF, SrcF, Index);
auto *Dst = Func->makeVariable(typeElementType(DestTy));
Variable *DestT = Func->makeVariable(DestTy);
Context.insert<InstSelect>(Dst, OpC, OpT, OpF);
Context.insert<InstInsertElement>(DestT, T, Dst, Index);
T = DestT;
}
Context.insert<InstAssign>(Dest, T);
Instr->setDeleted();
}
return;
}
case Inst::Fcmp: {
if (isVectorType(DestTy)) {
InstFcmp::FCond Cond = llvm::cast<InstFcmp>(Instr)->getCondition();
Operand *Src0 = Instr->getSrc(0);
Operand *Src1 = Instr->getSrc(1);
Variable *T = Func->makeVariable(IceType_v4f32);
auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
Context.insert<InstAssign>(T, Undef);
auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
VarVecOn32->initVecElement(Func);
for (SizeT I = 0; I < typeNumElements(IceType_v4f32); ++I) {
auto *Index = Ctx->getConstantInt32(I);
auto *Op0 = Func->makeVariable(IceType_f32);
Context.insert<InstExtractElement>(Op0, Src0, Index);
auto *Op1 = Func->makeVariable(IceType_f32);
Context.insert<InstExtractElement>(Op1, Src1, Index);
auto *Dst = Func->makeVariable(IceType_f32);
Variable *DestT = Func->makeVariable(IceType_v4f32);
Context.insert<InstFcmp>(Cond, Dst, Op0, Op1);
Context.insert<InstInsertElement>(DestT, T, Dst, Index);
T = DestT;
}
Context.insert<InstAssign>(Dest, T);
Instr->setDeleted();
}
return;
}
case Inst::Icmp: {
if (isVectorType(DestTy)) {
InstIcmp::ICond Cond = llvm::cast<InstIcmp>(Instr)->getCondition();
Operand *Src0 = Instr->getSrc(0);
Operand *Src1 = Instr->getSrc(1);
const Type SrcType = Src0->getType();
Variable *T = Func->makeVariable(DestTy);
auto *Undef = ConstantUndef::create(Ctx, DestTy);
Context.insert<InstAssign>(T, Undef);
auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
VarVecOn32->initVecElement(Func);
for (SizeT I = 0; I < typeNumElements(SrcType); ++I) {
auto *Index = Ctx->getConstantInt32(I);
auto *Op0 = Func->makeVariable(typeElementType(SrcType));
Context.insert<InstExtractElement>(Op0, Src0, Index);
auto *Op1 = Func->makeVariable(typeElementType(SrcType));
Context.insert<InstExtractElement>(Op1, Src1, Index);
auto *Dst = Func->makeVariable(typeElementType(DestTy));
Variable *DestT = Func->makeVariable(DestTy);
Context.insert<InstIcmp>(Cond, Dst, Op0, Op1);
Context.insert<InstInsertElement>(DestT, T, Dst, Index);
T = DestT;
}
Context.insert<InstAssign>(Dest, T);
Instr->setDeleted();
}
return;
}
case Inst::Arithmetic: {
Variable *Dest = Instr->getDest();
const Type DestTy = Dest->getType();
const InstArithmetic::OpKind Op =
llvm::cast<InstArithmetic>(Instr)->getOp();
if (isVectorType(DestTy)) {
......@@ -307,12 +391,32 @@ void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
llvm::report_fatal_error("Control flow should never have reached here.");
}
case Inst::Cast: {
Variable *Dest = Instr->getDest();
Operand *Src0 = Instr->getSrc(0);
const Type DestTy = Dest->getType();
const Type SrcTy = Src0->getType();
auto *CastInstr = llvm::cast<InstCast>(Instr);
const InstCast::OpKind CastKind = CastInstr->getCastKind();
if (isVectorType(DestTy)) {
Variable *T = Func->makeVariable(DestTy);
auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
VarVecOn32->initVecElement(Func);
auto *Undef = ConstantUndef::create(Ctx, DestTy);
Context.insert<InstAssign>(T, Undef);
for (SizeT I = 0; I < typeNumElements(DestTy); ++I) {
auto *Index = Ctx->getConstantInt32(I);
auto *Op = Func->makeVariable(typeElementType(SrcTy));
Context.insert<InstExtractElement>(Op, Src0, Index);
auto *Dst = Func->makeVariable(typeElementType(DestTy));
Variable *DestT = Func->makeVariable(DestTy);
Context.insert<InstCast>(CastKind, Dst, Op);
Context.insert<InstInsertElement>(DestT, T, Dst, Index);
T = DestT;
}
Context.insert<InstAssign>(Dest, T);
Instr->setDeleted();
return;
}
switch (CastKind) {
default:
return;
......@@ -352,7 +456,7 @@ void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
}
const bool SourceIs32 = SrcTy == IceType_i32;
const bool SourceIsSigned = CastKind == InstCast::Sitofp;
const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
const bool DestIsF32 = isFloat32Asserting32Or64(DestTy);
RuntimeHelper RTHFunc = RuntimeHelper::H_Num;
if (SourceIsSigned) {
if (SourceIs32) {
......@@ -416,7 +520,7 @@ void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
Context.insert(Call);
// The PNaCl ABI disallows i8/i16 return types, so truncate the helper
// call result to the appropriate type as necessary.
if (CallDest->getType() != Dest->getType())
if (CallDest->getType() != DestTy)
Context.insert<InstCast>(InstCast::Trunc, Dest, CallDest);
Instr->setDeleted();
return;
......@@ -450,10 +554,9 @@ void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
llvm::report_fatal_error("Control flow should never have reached here.");
}
case Inst::IntrinsicCall: {
Variable *Dest = Instr->getDest();
auto *IntrinsicCall = llvm::cast<InstIntrinsicCall>(Instr);
Intrinsics::IntrinsicID ID = IntrinsicCall->getIntrinsicInfo().ID;
if (Dest && isVectorType(Dest->getType()) && ID == Intrinsics::Fabs) {
if (isVectorType(DestTy) && ID == Intrinsics::Fabs) {
Operand *Src0 = IntrinsicCall->getArg(0);
GlobalString FabsFloat = Ctx->getGlobalString("llvm.fabs.f32");
Operand *CallTarget = Ctx->getConstantExternSym(FabsFloat);
......@@ -464,11 +567,12 @@ void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
Intrinsics::IntrinsicInfo Info = FullInfo->Info;
Variable *T = Func->makeVariable(IceType_v4f32);
auto *VarVecOn32 = llvm::dyn_cast<VariableVecOn32>(T);
auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
Context.insert<InstAssign>(T, Undef);
auto *VarVecOn32 = llvm::cast<VariableVecOn32>(T);
VarVecOn32->initVecElement(Func);
Context.insert<InstFakeDef>(T);
for (SizeT i = 0; i < VarVecOn32->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < typeNumElements(IceType_v4f32); ++i) {
auto *Index = Ctx->getConstantInt32(i);
auto *Op = Func->makeVariable(IceType_f32);
Context.insert<InstExtractElement>(Op, Src0, Index);
......@@ -1099,23 +1203,13 @@ void TargetMIPS32::lowerArguments() {
// v4f32 is returned through stack. $4 is setup by the caller and passed as
// first argument implicitly. Callee then copies the return vector at $4.
Variable *ImplicitRetVec = nullptr;
if (isVectorFloatingType(Func->getReturnType())) {
Variable *ImplicitRetVec = Func->makeVariable(IceType_i32);
ImplicitRetVec = Func->makeVariable(IceType_i32);
ImplicitRetVec->setName(Func, "ImplicitRet_v4f32");
ImplicitRetVec->setIsArg();
Args.insert(Args.begin(), ImplicitRetVec);
setImplicitRet(ImplicitRetVec);
Context.insert<InstFakeDef>(ImplicitRetVec);
for (CfgNode *Node : Func->getNodes()) {
for (Inst &Instr : Node->getInsts()) {
if (llvm::isa<InstRet>(&Instr)) {
Context.setInsertPoint(Instr);
Context.insert<InstFakeUse>(ImplicitRetVec);
break;
}
}
}
Context.setInsertPoint(Context.getCur());
}
for (SizeT i = 0, E = Args.size(); i < E; ++i) {
......@@ -1169,6 +1263,19 @@ void TargetMIPS32::lowerArguments() {
}
Context.insert<InstAssign>(Arg, RegisterArg);
}
// Insert fake use of ImplicitRet_v4f32 to keep it live
if (ImplicitRetVec) {
for (CfgNode *Node : Func->getNodes()) {
for (Inst &Instr : Node->getInsts()) {
if (llvm::isa<InstRet>(&Instr)) {
Context.setInsertPoint(Instr);
Context.insert<InstFakeUse>(ImplicitRetVec);
break;
}
}
}
}
}
Type TargetMIPS32::stackSlotType() { return IceType_i32; }
......@@ -2361,7 +2468,7 @@ void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) {
return;
}
if (isVectorType(Dest->getType())) {
UnimplementedLoweringError(this, Instr);
llvm::report_fatal_error("Arithmetic: Destination type is vector");
return;
}
......@@ -2509,6 +2616,20 @@ void TargetMIPS32::lowerAssign(const InstAssign *Instr) {
return;
}
// Source type may not be same as destination
if (isVectorType(Dest->getType())) {
Operand *Src0 = legalizeUndef(Instr->getSrc(0));
auto *DstVec = llvm::dyn_cast<VariableVecOn32>(Dest);
for (SizeT i = 0; i < DstVec->ContainersPerVector; ++i) {
auto *DCont = DstVec->getContainers()[i];
auto *SCont =
legalize(getOperandAtIndex(Src0, IceType_i32, i), Legal_Reg);
auto *TReg = makeReg(IceType_i32);
_mov(TReg, SCont);
_mov(DCont, TReg);
}
return;
}
Operand *Src0 = Instr->getSrc(0);
assert(Dest->getType() == Src0->getType());
if (Dest->getType() == IceType_i64) {
......@@ -2524,18 +2645,6 @@ void TargetMIPS32::lowerAssign(const InstAssign *Instr) {
_mov(DestHi, T_Hi);
return;
}
if (isVectorType(Dest->getType())) {
auto *DstVec = llvm::dyn_cast<VariableVecOn32>(Dest);
for (SizeT i = 0; i < DstVec->ElementsPerContainer; ++i) {
auto *DCont = DstVec->getContainers()[i];
auto *SCont =
legalize(getOperandAtIndex(Src0, IceType_i32, i), Legal_Reg);
auto *TReg = makeReg(IceType_i32);
_mov(TReg, SCont);
_mov(DCont, TReg);
}
return;
}
Operand *SrcR;
if (Dest->hasReg()) {
// If Dest already has a physical register, then legalize the Src operand
......@@ -2944,7 +3053,7 @@ void TargetMIPS32::lowerCall(const InstCall *Instr) {
ReturnReg = makeReg(Dest->getType(), RegMIPS32::Reg_V0);
auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg);
RetVec->initVecElement(Func);
for (SizeT i = 0; i < RetVec->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < RetVec->ContainersPerVector; ++i) {
auto *Var = RetVec->getContainers()[i];
Var->setRegNum(RegNumT::fixme(RegMIPS32::Reg_V0 + i));
}
......@@ -3035,7 +3144,7 @@ void TargetMIPS32::lowerCall(const InstCall *Instr) {
if (ReturnReg) {
if (RetVecFloat) {
auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
for (SizeT i = 0; i < DestVecOn32->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
auto *Var = DestVecOn32->getContainers()[i];
OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
Func, IceType_i32, RetVecFloat,
......@@ -3044,7 +3153,7 @@ void TargetMIPS32::lowerCall(const InstCall *Instr) {
}
} else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) {
auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest);
for (SizeT i = 0; i < DestVecOn32->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) {
_mov(DestVecOn32->getContainers()[i], RetVec->getContainers()[i]);
}
} else if (ReturnRegHi) {
......@@ -3080,7 +3189,7 @@ void TargetMIPS32::lowerCast(const InstCast *Instr) {
: (1 << (CHAR_BITS * typeWidthInBytes(Src0Ty))) - 1);
if (isVectorType(DestTy)) {
UnimplementedLoweringError(this, Instr);
llvm::report_fatal_error("Cast: Destination type is vector");
return;
}
switch (CastKind) {
......@@ -3243,6 +3352,11 @@ void TargetMIPS32::lowerCast(const InstCast *Instr) {
lowerAssign(Assign);
return;
}
if (isVectorType(DestTy) || isVectorType(Src0->getType())) {
llvm::report_fatal_error(
"Bitcast: vector type should have been prelowered.");
return;
}
switch (DestTy) {
case IceType_NUM:
case IceType_void:
......@@ -3292,16 +3406,6 @@ void TargetMIPS32::lowerCast(const InstCast *Instr) {
}
break;
}
case IceType_v8i1:
assert(Src0->getType() == IceType_i8);
llvm::report_fatal_error(
"v8i1 to i8 conversion should have been prelowered.");
break;
case IceType_v16i1:
assert(Src0->getType() == IceType_i16);
llvm::report_fatal_error(
"v16i1 to i16 conversion should have been prelowered.");
break;
default:
UnimplementedLoweringError(this, Instr);
}
......@@ -3322,7 +3426,7 @@ void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
// Number of elements in each container
uint32_t ElemPerCont =
typeNumElements(Src0->getType()) / Src0R->ElementsPerContainer;
typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
// Position of the element in the container
uint32_t PosInCont = Index % ElemPerCont;
......@@ -3362,8 +3466,9 @@ void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
}
}
if (typeElementType(Src0R->getType()) == IceType_i1) {
_andi(TReg, TDest, 0x1);
_mov(Dest, TReg);
Variable *TReg1 = makeReg(DestTy);
_andi(TReg1, TDest, 0x1);
_mov(Dest, TReg1);
} else {
_mov(Dest, TDest);
}
......@@ -3375,7 +3480,7 @@ void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
Variable *Dest = Instr->getDest();
if (isVectorType(Dest->getType())) {
UnimplementedLoweringError(this, Instr);
llvm::report_fatal_error("Fcmp: Destination type is vector");
return;
}
......@@ -3384,7 +3489,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
auto *Zero = getZero();
InstFcmp::FCond Cond = Instr->getCondition();
auto *DestR = makeReg(Dest->getType());
auto *DestR = makeReg(IceType_i32);
auto *Src0R = legalizeToReg(Src0);
auto *Src1R = legalizeToReg(Src1);
const Type Src0Ty = Src0->getType();
......@@ -3722,7 +3827,7 @@ void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) {
}
Variable *Dest = Instr->getDest();
if (isVectorType(Dest->getType())) {
UnimplementedLoweringError(this, Instr);
llvm::report_fatal_error("Icmp: Destination type is vector");
return;
}
InstIcmp::ICond Cond = Instr->getCondition();
......@@ -3828,14 +3933,13 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) {
const uint32_t Index = Imm->getValue();
// Vector to insert in
auto *Src0 = Instr->getSrc(0);
auto *Src0 = legalizeUndef(Instr->getSrc(0));
auto *Src0R = llvm::dyn_cast<VariableVecOn32>(Src0);
// Number of elements in each container
uint32_t ElemPerCont =
typeNumElements(Src0->getType()) / Src0R->ElementsPerContainer;
typeNumElements(Src0->getType()) / Src0R->ContainersPerVector;
// Source Element
auto *SrcE = Src0R->getContainers()[Index / ElemPerCont];
Context.insert<InstFakeDef>(SrcE);
// Dest is a vector
auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest);
VDest->initVecElement(Func);
......@@ -3855,7 +3959,7 @@ void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
// Position of the element in the container
uint32_t PosInCont = Index % ElemPerCont;
// Load source vector in a temporary vector
for (SizeT i = 0; i < TVDest->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < TVDest->ContainersPerVector; ++i) {
auto *DCont = TVDest->getContainers()[i];
// Do not define DstE as we are going to redefine it
if (DCont == DstE)
......@@ -4406,7 +4510,6 @@ OperandMIPS32Mem *TargetMIPS32::formAddressingMode(Type Ty, Cfg *Func,
}
if (isVectorType(Ty)) {
UnimplementedError(getFlags());
return nullptr;
}
......@@ -4549,7 +4652,7 @@ void TargetMIPS32::lowerRet(const InstRet *Instr) {
Reg = getImplicitRet();
auto *RegT = legalizeToReg(Reg);
// Return the vector through buffer in implicit argument a0
for (SizeT i = 0; i < SrcVec->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) {
OperandMIPS32Mem *Mem = OperandMIPS32Mem::create(
Func, IceType_f32, RegT,
llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4)));
......@@ -4575,7 +4678,7 @@ void TargetMIPS32::lowerSelect(const InstSelect *Instr) {
const Type DestTy = Dest->getType();
if (isVectorType(DestTy)) {
UnimplementedLoweringError(this, Instr);
llvm::report_fatal_error("Select: Destination type is vector");
return;
}
......@@ -4647,7 +4750,7 @@ void TargetMIPS32::lowerStore(const InstStore *Instr) {
_sw(ValueLo, llvm::cast<OperandMIPS32Mem>(loOperand(NewAddr)));
} else if (isVectorType(Value->getType())) {
auto *DataVec = llvm::dyn_cast<VariableVecOn32>(Value);
for (SizeT i = 0; i < DataVec->ElementsPerContainer; ++i) {
for (SizeT i = 0; i < DataVec->ContainersPerVector; ++i) {
auto *DCont = legalizeToReg(DataVec->getContainers()[i]);
auto *MCont = llvm::cast<OperandMIPS32Mem>(
getOperandAtIndex(NewAddr, IceType_i32, i));
......
tests_lit/llvm2ice_tests/fp.cmp.ll
......@@ -379,8 +379,8 @@ entry:
; ARM32-LABEL: fcmpFalseFloat
; ARM32: mov [[R:r[0-9]+]], #0
; MIPS32-LABEL: fcmpFalseFloat
; MIPS32: addiu
; MIPS32: sb
; MIPS32: addiu [[R:.*]], $zero, 0
; MIPS32: andi [[R]], [[R]], 1
define internal i32 @fcmpFalseDouble(double %a, double %b) {
entry:
......@@ -393,8 +393,8 @@ entry:
; ARM32-LABEL: fcmpFalseDouble
; ARM32: mov [[R:r[0-9]+]], #0
; MIPS32-LABEL: fcmpFalseDouble
; MIPS32: addiu
; MIPS32: sb
; MIPS32: addiu [[R:.*]], $zero, 0
; MIPS32: andi [[R]], [[R]], 1
define internal i32 @fcmpOeqFloat(float %a, float %b) {
entry:
......@@ -975,8 +975,8 @@ entry:
; ARM32-LABEL: fcmpTrueFloat
; ARM32: mov {{r[0-9]+}}, #1
; MIPS32-LABEL: fcmpTrueFloat
; MIPS32: addiu
; MIPS32: sb
; MIPS32: addiu [[R:.*]], $zero, 1
; MIPS32: andi [[R]], [[R]], 1
define internal i32 @fcmpTrueDouble(double %a, double %b) {
entry:
......@@ -989,8 +989,8 @@ entry:
; ARM32-LABEL: fcmpTrueDouble
; ARM32: mov {{r[0-9]+}}, #1
; MIPS32-LABEL: fcmpTrueDouble
; MIPS32: addiu
; MIPS32: sb
; MIPS32: addiu [[R:.*]], $zero, 1
; MIPS32: andi [[R]], [[R]], 1
define internal float @selectFloatVarVar(float %a, float %b) {
entry:
......
tests_lit/llvm2ice_tests/vector-align.ll
......@@ -7,6 +7,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
; RUN: %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
; RUN: -i %s --args -O2 --skip-unimplemented \
; RUN: | %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix MIPS32 %s
define internal <4 x i32> @test_add(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
......@@ -18,6 +24,12 @@ entry:
; CHECK-NOT: paddd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: paddd xmm{{.}},
; MIPS32-LABEL: test_add
; MIPS32: addu
; MIPS32: addu
; MIPS32: addu
; MIPS32: addu
define internal <4 x i32> @test_and(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
......@@ -29,6 +41,12 @@ entry:
; CHECK-NOT: pand xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: pand xmm{{.}},
; MIPS32-LABEL: test_and
; MIPS32: and
; MIPS32: and
; MIPS32: and
; MIPS32: and
define internal <4 x i32> @test_or(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
......@@ -40,6 +58,12 @@ entry:
; CHECK-NOT: por xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: por xmm{{.}},
; MIPS32-LABEL: test_or
; MIPS32: or
; MIPS32: or
; MIPS32: or
; MIPS32: or
define internal <4 x i32> @test_xor(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
......@@ -51,6 +75,12 @@ entry:
; CHECK-NOT: pxor xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: pxor xmm{{.}},
; MIPS32-LABEL: test_xor
; MIPS32: xor
; MIPS32: xor
; MIPS32: xor
; MIPS32: xor
define internal <4 x i32> @test_sub(i32 %addr_i, <4 x i32> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x i32>*
......@@ -62,6 +92,12 @@ entry:
; CHECK-NOT: psubd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: psubd xmm{{.}},
; MIPS32-LABEL: test_sub
; MIPS32: subu
; MIPS32: subu
; MIPS32: subu
; MIPS32: subu
define internal <4 x float> @test_fadd(i32 %addr_i, <4 x float> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x float>*
......@@ -73,6 +109,12 @@ entry:
; CHECK-NOT: addps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: addps xmm{{.}},
; MIPS32-LABEL: test_fadd
; MIPS32: add.s
; MIPS32: add.s
; MIPS32: add.s
; MIPS32: add.s
define internal <4 x float> @test_fsub(i32 %addr_i, <4 x float> %addend) {
entry:
%addr = inttoptr i32 %addr_i to <4 x float>*
......@@ -83,3 +125,9 @@ entry:
; CHECK-LABEL: test_fsub
; CHECK-NOT: subps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
; CHECK: subps xmm{{.}},
; MIPS32-LABEL: test_fsub
; MIPS32: sub.s
; MIPS32: sub.s
; MIPS32: sub.s
; MIPS32: sub.s
tests_lit/llvm2ice_tests/vector-fcmp.ll
......@@ -4,6 +4,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble -a -O2 | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble -a -Om1 | FileCheck %s
; RUN: %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
; RUN: -i %s --args -O2 --skip-unimplemented \
; RUN: | %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix MIPS32 %s
; Check that sext elimination occurs when the result of the comparison
; instruction is alrady sign extended. Sign extension to 4 x i32 uses
; the pslld instruction.
......@@ -16,6 +22,19 @@ entry:
; CHECK: cmpeqps
; CHECK-NOT: pslld
}
; MIPS32-LABEL: sextElimination
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpFalseVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -25,6 +44,11 @@ entry:
; CHECK-LABEL: fcmpFalseVector
; CHECK: pxor
}
; MIPS32-LABEL: fcmpFalseVector
; MIPS32: li v0,0
; MIPS32: li v1,0
; MIPS32: li a0,0
; MIPS32: li a1,0
define internal <4 x i32> @fcmpOeqVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -34,6 +58,19 @@ entry:
; CHECK-LABEL: fcmpOeqVector
; CHECK: cmpeqps
}
; MIPS32-LABEL: fcmpOeqVector
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOgeVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -43,6 +80,19 @@ entry:
; CHECK-LABEL: fcmpOgeVector
; CHECK: cmpleps
}
; MIPS32-LABEL: fcmpOgeVector
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOgtVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -52,6 +102,19 @@ entry:
; CHECK-LABEL: fcmpOgtVector
; CHECK: cmpltps
}
; MIPS32-LABEL: fcmpOgtVector
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOleVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -61,6 +124,19 @@ entry:
; CHECK-LABEL: fcmpOleVector
; CHECK: cmpleps
}
; MIPS32-LABEL: fcmpOleVector
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOltVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -70,6 +146,19 @@ entry:
; CHECK-LABEL: fcmpOltVector
; CHECK: cmpltps
}
; MIPS32-LABEL: fcmpOltVector
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOneVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -81,6 +170,19 @@ entry:
; CHECK: cmpordps
; CHECK: pand
}
; MIPS32-LABEL: fcmpOneVector
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpOrdVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -90,6 +192,19 @@ entry:
; CHECK-LABEL: fcmpOrdVector
; CHECK: cmpordps
}
; MIPS32-LABEL: fcmpOrdVector
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpTrueVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -99,6 +214,11 @@ entry:
; CHECK-LABEL: fcmpTrueVector
; CHECK: pcmpeqd
}
; MIPS32-LABEL: fcmpTrueVector
; MIPS32: li v0,1
; MIPS32: li v1,1
; MIPS32: li a0,1
; MIPS32: li a1,1
define internal <4 x i32> @fcmpUeqVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -110,6 +230,19 @@ entry:
; CHECK: cmpunordps
; CHECK: por
}
; MIPS32-LABEL: fcmpUeqVector
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ueq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUgeVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -119,6 +252,19 @@ entry:
; CHECK-LABEL: fcmpUgeVector
; CHECK: cmpnltps
}
; MIPS32-LABEL: fcmpUgeVector
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.olt.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUgtVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -128,6 +274,19 @@ entry:
; CHECK-LABEL: fcmpUgtVector
; CHECK: cmpnleps
}
; MIPS32-LABEL: fcmpUgtVector
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.ole.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUleVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -137,6 +296,19 @@ entry:
; CHECK-LABEL: fcmpUleVector
; CHECK: cmpnltps
}
; MIPS32-LABEL: fcmpUleVector
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ule.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUltVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -146,6 +318,19 @@ entry:
; CHECK-LABEL: fcmpUltVector
; CHECK: cmpnleps
}
; MIPS32-LABEL: fcmpUltVector
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.ult.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUneVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -155,6 +340,19 @@ entry:
; CHECK-LABEL: fcmpUneVector
; CHECK: cmpneqps
}
; MIPS32-LABEL: fcmpUneVector
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
; MIPS32: c.eq.s
; MIPS32: li [[R:.*]],1
; MIPS32: movt [[R]],zero,$fcc0
define internal <4 x i32> @fcmpUnoVector(<4 x float> %a, <4 x float> %b) {
entry:
......@@ -164,3 +362,16 @@ entry:
; CHECK-LABEL: fcmpUnoVector
; CHECK: cmpunordps
}
; MIPS32-LABEL: fcmpUnoVector
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
; MIPS32: c.un.s
; MIPS32: li [[R:.*]],1
; MIPS32: movf [[R]],zero,$fcc0
tests_lit/llvm2ice_tests/vector-icmp.ll
This source diff could not be displayed because it is too large. You can view the blob instead.
tests_lit/llvm2ice_tests/vector-ops.ll
......@@ -9,6 +9,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
; RUN: -i %s --args -O2 --skip-unimplemented \
; RUN: | %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix MIPS32 %s
; insertelement operations
define internal <4 x float> @insertelement_v4f32_0(<4 x float> %vec,
......@@ -21,6 +27,24 @@ entry:
; SSE41-LABEL: insertelement_v4f32_0
; SSE41: insertps {{.*}},{{.*}},0x0
; *** a0 - implicit return <4 x float>
; *** a1 - unused due to alignment of %vec
; *** a2:a3:sp[16]:s[20] - %vec
; *** sp[24] - %elt
; MIPS32-LABEL: insertelement_v4f32_0
; *** Load element 2 and 3 of %vec
; MIPS32: lw [[BV_E2:.*]],
; MIPS32: lw [[BV_E3:.*]],
; *** Load %elt
; MIPS32: lwc1 [[ELT:.*]],
; *** Insert %elt at %vec[0]
; MIPS32: mfc1 [[RV_E0:.*]],[[ELT]]
; MIPS32: move [[RET_PTR:.*]],a0
; MIPS32: sw [[RV_E0]],0([[RET_PTR]])
; MIPS32: sw a3,4([[RET_PTR]])
; MIPS32: sw [[BV_E2]],8([[RET_PTR]])
; MIPS32: sw [[BV_E3]],12([[RET_PTR]])
}
define internal <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
......@@ -33,6 +57,15 @@ entry:
; SSE41-LABEL: insertelement_v4i32_0
; SSE41: pinsrd {{.*}},{{.*}},0x0
; *** a0:a1:a2:a3 - %vec
; *** sp[16] - %elt
; MIPS32-LABEL: insertelement_v4i32_0
; *** Load %elt
; MIPS32: lw v0,16(sp)
; MIPS32: move v1,a1
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
......@@ -47,6 +80,17 @@ entry:
; SSE41-LABEL: insertelement_v4f32_1
; SSE41: insertps {{.*}},{{.*}},0x10
; MIPS32-LABEL: insertelement_v4f32_1
; MIPS32: lw [[VEC_E2:.*]],16(sp)
; MIPS32: lw [[VEC_E3:.*]],20(sp)
; MIPS32: lwc1 [[ELT:.*]],24(sp)
; MIPS32: mfc1 [[R_E1:.*]],[[ELT]]
; MIPS32: move [[PTR:.*]],a0
; MIPS32: sw a2,0([[PTR]])
; MIPS32: sw [[R_E1]],4([[PTR]])
; MIPS32: sw [[VEC_E2]],8([[PTR]])
; MIPS32: sw [[VEC_E3]],12([[PTR]])
}
define internal <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
......@@ -59,6 +103,13 @@ entry:
; SSE41-LABEL: insertelement_v4i32_1
; SSE41: pinsrd {{.*}},{{.*}},0x1
; MIPS32-LABEL: insertelement_v4i32_1
; MIPS32: lw [[ELT:.*]],16(sp)
; MIPS32: move v1,[[ELT]]
; MIPS32: move v0,a0
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
define internal <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
......@@ -71,6 +122,16 @@ entry:
; SSE41-LABEL: insertelement_v8i16
; SSE41: pinsrw
; MIPS32-LABEL: insertelement_v8i16
; MIPS32: lw [[ELT:.*]],16(sp)
; MIPS32: sll [[ELT]],[[ELT]],0x10
; MIPS32: sll a0,a0,0x10
; MIPS32: srl a0,a0,0x10
; MIPS32: or v0,[[ELT]],a0
; MIPS32: move v1,a1
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
define internal <16 x i8> @insertelement_v16i8(<16 x i8> %vec, i32 %elt.arg) {
......@@ -85,6 +146,18 @@ entry:
; SSE41-LABEL: insertelement_v16i8
; SSE41: pinsrb
; MIPS32-LABEL: insertelement_v16i8
; MIPS32: lw [[ELT:.*]],16(sp)
; MIPS32: andi [[ELT]],[[ELT]],0xff
; MIPS32: sll [[ELT]],[[ELT]],0x8
; MIPS32: lui [[T:.*]],0xffff
; MIPS32: ori [[T]],[[T]],0xff
; MIPS32: and a0,a0,[[T]]
; MIPS32: or v0,v0,a0
; MIPS32: move v1,a1
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
define internal <4 x i1> @insertelement_v4i1_0(<4 x i1> %vec, i32 %elt.arg) {
......@@ -97,6 +170,12 @@ entry:
; SSE41-LABEL: insertelement_v4i1_0
; SSE41: pinsrd {{.*}},{{.*}},0x0
; MIPS32-LABEL: insertelement_v4i1_0
; MIPS32: lw v0,16(sp)
; MIPS32: move v1,a1
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
define internal <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
......@@ -110,6 +189,13 @@ entry:
; SSE41-LABEL: insertelement_v4i1_1
; SSE41: pinsrd {{.*}},{{.*}},0x1
; MIPS32-LABEL: insertelement_v4i1_1
; MIPS32: lw [[ELT:.*]],16(sp)
; MIPS32: move v1,[[ELT]]
; MIPS32: move v0,a0
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
define internal <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
......@@ -122,6 +208,16 @@ entry:
; SSE41-LABEL: insertelement_v8i1
; SSE41: pinsrw
; MIPS32-LABEL: insertelement_v8i1
; MIPS32: lw [[ELT:.*]],16(sp)
; MIPS32: sll [[ELT]],[[ELT]],0x10
; MIPS32: sll a0,a0,0x10
; MIPS32: srl a0,a0,0x10
; MIPS32: or v0,[[ELT]],a0
; MIPS32: move v1,a1
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
define internal <16 x i1> @insertelement_v16i1(<16 x i1> %vec, i32 %elt.arg) {
......@@ -136,6 +232,18 @@ entry:
; SSE41-LABEL: insertelement_v16i1
; SSE41: pinsrb
; MIPS32-LABEL: insertelement_v16i1
; MIPS32: lw [[ELT:.*]],16(sp)
; MIPS32: andi [[ELT]],[[ELT]],0xff
; MIPS32: sll [[ELT]],[[ELT]],0x8
; MIPS32: lui [[T:.*]],0xffff
; MIPS32: ori [[T]],[[T]],0xff
; MIPS32: and a0,a0,[[T]]
; MIPS32: or v0,[[ELT]],a0
; MIPS32: move v1,a1
; MIPS32: move a0,a2
; MIPS32: move a1,a3
}
; extractelement operations
......@@ -149,6 +257,9 @@ entry:
; SSE41-LABEL: extractelement_v4f32
; SSE41: pshufd
; MIPS32-LABEL: extractelement_v4f32
; MIPS32: mtc1 a1,$f0
}
define internal i32 @extractelement_v4i32(<4 x i32> %vec) {
......@@ -161,6 +272,9 @@ entry:
; SSE41-LABEL: extractelement_v4i32
; SSE41: pextrd
; MIPS32-LABEL: extractelement_v4i32
; MIPS32L move v0,a1
}
define internal i32 @extractelement_v8i16(<8 x i16> %vec) {
......@@ -173,6 +287,11 @@ entry:
; SSE41-LABEL: extractelement_v8i16
; SSE41: pextrw
; MIPS32-LABEL: extractelement_v8i16
; MIPS32: srl a0,a0,0x10
; MIPS32: andi a0,a0,0xffff
; MIPS32: move v0,a0
}
define internal i32 @extractelement_v16i8(<16 x i8> %vec) {
......@@ -187,6 +306,12 @@ entry:
; SSE41-LABEL: extractelement_v16i8
; SSE41: pextrb
; MIPS32-LABEL: extractelement_v16i8
; MIPS32: srl a0,a0,0x8
; MIPS32: andi a0,a0,0xff
; MIPS32: andi a0,a0,0xff
; MIPS32: move v0,a0
}
define internal i32 @extractelement_v4i1(<4 x i1> %vec) {
......@@ -199,6 +324,11 @@ entry:
; SSE41-LABEL: extractelement_v4i1
; SSE41: pextrd
; MIPS32-LABEL: extractelement_v4i1
; MIPS32: andi a1,a1,0x1
; MIPS32: andi a1,a1,0x1
; MIPS32: move v0,a1
}
define internal i32 @extractelement_v8i1(<8 x i1> %vec) {
......@@ -211,6 +341,12 @@ entry:
; SSE41-LABEL: extractelement_v8i1
; SSE41: pextrw
; MIPS32-LABEL: extractelement_v8i1
; MIPS32: srl a0,a0,0x10
; MIPS32: andi a0,a0,0x1
; MIPS32: andi a0,a0,0x1
; MIPS32: move v0,a0
}
define internal i32 @extractelement_v16i1(<16 x i1> %vec) {
......@@ -225,4 +361,11 @@ entry:
; SSE41-LABEL: extractelement_v16i1
; SSE41: pextrb
; MIPS32-LABEL: extractelement_v16i1
; MIPS32: srl a0,a0,0x8
; MIPS32: andi a0,a0,0xff
; MIPS32: andi a0,a0,0x1
; MIPS32: andi a0,a0,0x1
; MIPS32: move v0,a0
}
tests_lit/llvm2ice_tests/vector-select.ll
......@@ -9,6 +9,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
; RUN: -i %s --args -O2 --skip-unimplemented \
; RUN: | %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix MIPS32 %s
define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1,
<16 x i8> %arg2) {
entry:
......@@ -21,6 +27,204 @@ entry:
; SSE41-LABEL: test_select_v16i8
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v16i8
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xff
; MIPS32: andi [[T14:.*]],[[T4]],0xff
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T8]],a0,0x8
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x8
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: srl [[T13]],[[T4]],0x8
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: movn [[T13]],[[T12]],[[T8]]
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: sll [[T13]],[[T13]],0x8
; MIPS32: lui [[T8]],0xffff
; MIPS32: ori [[T8]],[[T8]],0xff
; MIPS32: and [[T14]],[[T14]],[[T8]]
; MIPS32: or [[T13]],[[T13]],[[T14]]
; MIPS32: srl [[T8]],a0,0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x10
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: srl [[T14]],[[T4]],0x10
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: movn [[T14]],[[T12]],[[T8]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: lui [[T8]],0xff00
; MIPS32: ori [[T8]],[[T8]],0xffff
; MIPS32: and [[T13]],[[T13]],[[T8]]
; MIPS32: or [[T14]],[[T14]],[[T13]]
; MIPS32: srl [[T15:.*]],a0,0x18
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x18
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xff
; MIPS32: andi [[T8]],[[T5]],0xff
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: srl [[T9]],[[T9]],0x8
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T0]],a1,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x8
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T9]],[[T5]],0x8
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: movn [[T9]],[[T15]],[[T0]]
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T8]],[[T8]],[[T0]]
; MIPS32: or [[T9]],[[T9]],[[T8]]
; MIPS32: srl [[T0]],a1,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T8]],[[T5]],0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T9]],[[T9]],[[T0]]
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x18
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x18
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xff
; MIPS32: andi [[T15]],[[T6]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T10]],[[T10]],0x8
; MIPS32: sll [[T10]],[[T10]],0x8
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T0]],a2,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T16]],[[T6]],0x8
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a2,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T15]],[[T6]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T17:.*]],a2,0x18
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x18
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xff
; MIPS32: andi [[T15]],[[T7]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T11]],[[T11]],0x8
; MIPS32: sll [[T11]],[[T11]],0x8
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T0]],a3,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T16]],[[T7]],0x8
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a3,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: srl [[T15]],[[T7]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T18:.*]],a3,0x18
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x18
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1,
......@@ -35,6 +239,236 @@ entry:
; SSE41-LABEL: test_select_v16i1
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v16i1
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xff
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: andi [[T14:.*]],[[T4]],0xff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T8]],a0,0x8
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x8
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: srl [[T13]],[[T4]],0x8
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: movn [[T13]],[[T12]],[[T8]]
; MIPS32: andi [[T13]],[[T13]],0xff
; MIPS32: sll [[T13]],[[T13]],0x8
; MIPS32: lui [[T8]],0xffff
; MIPS32: ori [[T8]],[[T8]],0xff
; MIPS32: and [[T14]],[[T14]],[[T8]]
; MIPS32: or [[T13]],[[T13]],[[T14]]
; MIPS32: srl [[T8]],a0,0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: srl [[T12]],[[T0]],0x10
; MIPS32: andi [[T12]],[[T12]],0xff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: srl [[T14]],[[T4]],0x10
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T12]],[[T8]]
; MIPS32: andi [[T14]],[[T14]],0xff
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: lui [[T8]],0xff00
; MIPS32: ori [[T8]],[[T8]],0xffff
; MIPS32: and [[T13]],[[T13]],[[T8]]
; MIPS32: or [[T14]],[[T14]],[[T13]]
; MIPS32: srl [[T15:.*]],a0,0x18
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x18
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: andi [[T4]],[[T4]],0x1
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: srl [[T4]],[[T4]],0x18
; MIPS32: sll [[T14]],[[T14]],0x8
; MIPS32: srl [[T14]],[[T14]],0x8
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: andi [[T8]],[[T5]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: srl [[T9]],[[T9]],0x8
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T0]],a1,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x8
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T9]],[[T5]],0x8
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: andi [[T9]],[[T9]],0x1
; MIPS32: movn [[T9]],[[T15]],[[T0]]
; MIPS32: andi [[T9]],[[T9]],0xff
; MIPS32: sll [[T9]],[[T9]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T8]],[[T8]],[[T0]]
; MIPS32: or [[T9]],[[T9]],[[T8]]
; MIPS32: srl [[T0]],a1,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T15]],[[T1]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T8]],[[T5]],0x10
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xff
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T9]],[[T9]],[[T0]]
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x18
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x18
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: andi [[T5]],[[T5]],0x1
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: srl [[T5]],[[T5]],0x18
; MIPS32: sll [[T8]],[[T8]],0x8
; MIPS32: srl [[T8]],[[T8]],0x8
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T6]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T10]],[[T10]],0x8
; MIPS32: sll [[T10]],[[T10]],0x8
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T0]],a2,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T16]],[[T6]],0x8
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a2,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T2]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T15]],[[T6]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T17:.*]],a2,0x18
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x18
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: srl [[T6]],[[T6]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T7]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: srl [[T11]],[[T11]],0x8
; MIPS32: sll [[T11]],[[T11]],0x8
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T0]],a3,0x8
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x8
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T16]],[[T7]],0x8
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: movn [[T16]],[[T1]],[[T0]]
; MIPS32: andi [[T16]],[[T16]],0xff
; MIPS32: sll [[T16]],[[T16]],0x8
; MIPS32: lui [[T0]],0xffff
; MIPS32: ori [[T0]],[[T0]],0xff
; MIPS32: and [[T15]],[[T15]],[[T0]]
; MIPS32: or [[T16]],[[T16]],[[T15]]
; MIPS32: srl [[T0]],a3,0x10
; MIPS32: andi [[T0]],[[T0]],0xff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T1]],[[T3]],0x10
; MIPS32: andi [[T1]],[[T1]],0xff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T15]],[[T7]],0x10
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xff
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: lui [[T0]],0xff00
; MIPS32: ori [[T0]],[[T0]],0xffff
; MIPS32: and [[T16]],[[T16]],[[T0]]
; MIPS32: or [[T15]],[[T15]],[[T16]]
; MIPS32: srl [[T18:.*]],a3,0x18
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x18
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: srl [[T7]],[[T7]],0x18
; MIPS32: sll [[T15]],[[T15]],0x8
; MIPS32: srl [[T15]],[[T15]],0x8
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1,
......@@ -49,6 +483,92 @@ entry:
; SSE41-LABEL: test_select_v8i16
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v8i16
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xffff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xffff
; MIPS32: andi [[T14:.*]],[[T4]],0xffff
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T15:.*]],a0,0x10
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x10
; MIPS32: srl [[T4]],[[T4]],0x10
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: sll [[T4]],[[T4]],0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xffff
; MIPS32: andi [[T8]],[[T5]],0xffff
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xffff
; MIPS32: srl [[T9]],[[T9]],0x10
; MIPS32: sll [[T9]],[[T9]],0x10
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x10
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: srl [[T5]],[[T5]],0x10
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: sll [[T5]],[[T5]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xffff
; MIPS32: andi [[T15]],[[T6]],0xffff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: srl [[T10]],[[T10]],0x10
; MIPS32: sll [[T10]],[[T10]],0x10
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T17:.*]],a2,0x10
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x10
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: sll [[T6]],[[T6]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xffff
; MIPS32: andi [[T15]],[[T7]],0xffff
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: srl [[T11]],[[T11]],0x10
; MIPS32: sll [[T11]],[[T11]],0x10
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T18:.*]],a3,0x10
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x10
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: sll [[T7]],[[T7]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1,
......@@ -63,6 +583,108 @@ entry:
; SSE41-LABEL: test_select_v8i1
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v8i1
; MIPS32: lw [[T0:.*]],36(sp)
; MIPS32: lw [[T1:.*]],40(sp)
; MIPS32: lw [[T2:.*]],44(sp)
; MIPS32: lw [[T3:.*]],48(sp)
; MIPS32: lw [[T4:.*]],52(sp)
; MIPS32: lw [[T5:.*]],56(sp)
; MIPS32: lw [[T6:.*]],60(sp)
; MIPS32: lw [[T7:.*]],64(sp)
; MIPS32: move [[T8:.*]],zero
; MIPS32: move [[T9:.*]],zero
; MIPS32: move [[T10:.*]],zero
; MIPS32: move [[T11:.*]],zero
; MIPS32: andi [[T12:.*]],a0,0xffff
; MIPS32: andi [[T12]],[[T12]],0x1
; MIPS32: andi [[T13:.*]],[[T0]],0xffff
; MIPS32: andi [[T13]],[[T13]],0x1
; MIPS32: andi [[T14:.*]],[[T4]],0xffff
; MIPS32: andi [[T14]],[[T14]],0x1
; MIPS32: movn [[T14]],[[T13]],[[T12]]
; MIPS32: andi [[T14]],[[T14]],0xffff
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: or [[T14]],[[T14]],[[T8]]
; MIPS32: srl [[T15:.*]],a0,0x10
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: srl [[T0]],[[T0]],0x10
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: srl [[T4]],[[T4]],0x10
; MIPS32: andi [[T4]],[[T4]],0x1
; MIPS32: movn [[T4]],[[T0]],[[T15]]
; MIPS32: sll [[T4]],[[T4]],0x10
; MIPS32: sll [[T14]],[[T14]],0x10
; MIPS32: srl [[T14]],[[T14]],0x10
; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]]
; MIPS32: andi [[T0]],a1,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T15]],[[T1]],0xffff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: andi [[T8]],[[T5]],0xffff
; MIPS32: andi [[T8]],[[T8]],0x1
; MIPS32: movn [[T8]],[[T15]],[[T0]]
; MIPS32: andi [[T8]],[[T8]],0xffff
; MIPS32: srl [[T9]],[[T9]],0x10
; MIPS32: sll [[T9]],[[T9]],0x10
; MIPS32: or [[T8]],[[T8]],[[T9]]
; MIPS32: srl [[T16:.*]],a1,0x10
; MIPS32: andi [[T16]],[[T16]],0x1
; MIPS32: srl [[T1]],[[T1]],0x10
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: srl [[T5]],[[T5]],0x10
; MIPS32: andi [[T5]],[[T5]],0x1
; MIPS32: movn [[T5]],[[T1]],[[T16]]
; MIPS32: sll [[T5]],[[T5]],0x10
; MIPS32: sll [[T8]],[[T8]],0x10
; MIPS32: srl [[T8]],[[T8]],0x10
; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]]
; MIPS32: andi [[T0]],a2,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T2]],0xffff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T6]],0xffff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: srl [[T10]],[[T10]],0x10
; MIPS32: sll [[T10]],[[T10]],0x10
; MIPS32: or [[T15]],[[T15]],[[T10]]
; MIPS32: srl [[T17:.*]],a2,0x10
; MIPS32: andi [[T17]],[[T17]],0x1
; MIPS32: srl [[T2]],[[T2]],0x10
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: srl [[T6]],[[T6]],0x10
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: movn [[T6]],[[T2]],[[T17]]
; MIPS32: sll [[T6]],[[T6]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]]
; MIPS32: andi [[T0]],a3,0xffff
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T1]],[[T3]],0xffff
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T15]],[[T7]],0xffff
; MIPS32: andi [[T15]],[[T15]],0x1
; MIPS32: movn [[T15]],[[T1]],[[T0]]
; MIPS32: andi [[T15]],[[T15]],0xffff
; MIPS32: srl [[T11]],[[T11]],0x10
; MIPS32: sll [[T11]],[[T11]],0x10
; MIPS32: or [[T15]],[[T15]],[[T11]]
; MIPS32: srl [[T18:.*]],a3,0x10
; MIPS32: andi [[T18]],[[T18]],0x1
; MIPS32: srl [[T3]],[[T3]],0x10
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: srl [[T7]],[[T7]],0x10
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: movn [[T7]],[[T3]],[[T18]]
; MIPS32: sll [[T7]],[[T7]],0x10
; MIPS32: sll [[T15]],[[T15]],0x10
; MIPS32: srl [[T15]],[[T15]],0x10
; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]]
}
define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1,
......@@ -78,6 +700,28 @@ entry:
; SSE41-LABEL: test_select_v4i32
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v4i32
; MIPS32: lw [[T0:.*]],16(sp)
; MIPS32: lw [[T1:.*]],20(sp)
; MIPS32: lw [[T2:.*]],24(sp)
; MIPS32: lw [[T3:.*]],28(sp)
; MIPS32: lw [[T4:.*]],32(sp)
; MIPS32: lw [[T5:.*]],36(sp)
; MIPS32: lw [[T6:.*]],40(sp)
; MIPS32: lw [[T7:.*]],44(sp)
; MIPS32: andi [[T8:.*]],a0,0x1
; MIPS32: movn [[T4]],[[T0]],[[T8]]
; MIPS32: andi [[T9:.*]],a1,0x1
; MIPS32: movn [[T5]],[[T1]],[[T9]]
; MIPS32: andi [[T10:.*]],a2,0x1
; MIPS32: movn [[T6]],[[T2]],[[T10]]
; MIPS32: andi [[T11:.*]],a3,0x1
; MIPS32: movn [[T7]],[[T3]],[[T11]]
; MIPS32: move v0,[[T4]]
; MIPS32: move v1,[[T5]]
; MIPS32: move a0,[[T6]]
; MIPS32: move a1,[[T7]]
}
define internal <4 x float> @test_select_v4f32(
......@@ -93,6 +737,44 @@ entry:
; SSE41-LABEL: test_select_v4f32
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v4f32
; MIPS32: lw [[T0:.*]],16(sp)
; MIPS32: lw [[T1:.*]],20(sp)
; MIPS32: lw [[T2:.*]],24(sp)
; MIPS32: lw [[T3:.*]],28(sp)
; MIPS32: lw [[T4:.*]],32(sp)
; MIPS32: lw [[T5:.*]],36(sp)
; MIPS32: lw [[T6:.*]],40(sp)
; MIPS32: lw [[T7:.*]],44(sp)
; MIPS32: lw [[T8:.*]],48(sp)
; MIPS32: lw [[T9:.*]],52(sp)
; MIPS32: andi [[T10:.*]],a2,0x1
; MIPS32: mtc1 [[T2]],[[F0:.*]]
; MIPS32: mtc1 [[T6]],[[F1:.*]]
; MIPS32: movn.s [[T11:.*]],[[F0]],[[T10]]
; MIPS32: mfc1 v0,[[T11]]
; MIPS32: andi [[T12:.*]],a3,0x1
; MIPS32: mtc1 [[T3]],[[F0]]
; MIPS32: mtc1 [[T7]],[[T11]]
; MIPS32: movn.s [[T11]],[[F0]],[[T12]]
; MIPS32: mfc1 v1,[[T11]]
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: mtc1 [[T4]],[[F0]]
; MIPS32: mtc1 [[T8]],[[T11]]
; MIPS32: movn.s [[T11]],[[F0]],[[T0]]
; MIPS32: mfc1 a1,[[T11]]
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: mtc1 [[T5]],[[F0]]
; MIPS32: mtc1 [[T9]],[[T11]]
; MIPS32: movn.s [[T11]],[[F0]],[[T1]]
; MIPS32: mfc1 a2,[[T11]]
; MIPS32: move [[RET:.*]],a0
; MIPS32: sw v0,0([[RET]])
; MIPS32: sw v1,4([[RET]])
; MIPS32: sw a1,8([[RET]])
; MIPS32: sw a2,12([[RET]])
; MIPS32: move v0,a0
}
define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1,
......@@ -108,4 +790,34 @@ entry:
; SSE41-LABEL: test_select_v4i1
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
; MIPS32-LABEL: test_select_v4i1
; MIPS32: lw [[T0:.*]],16(sp)
; MIPS32: lw [[T1:.*]],20(sp)
; MIPS32: lw [[T2:.*]],24(sp)
; MIPS32: lw [[T3:.*]],28(sp)
; MIPS32: lw [[T4:.*]],32(sp)
; MIPS32: lw [[T5:.*]],36(sp)
; MIPS32: lw [[T6:.*]],40(sp)
; MIPS32: lw [[T7:.*]],44(sp)
; MIPS32: andi [[T8:.*]],a0,0x1
; MIPS32: andi [[T0]],[[T0]],0x1
; MIPS32: andi [[T4]],[[T4]],0x1
; MIPS32: movn [[T4]],[[T0]],[[T8]]
; MIPS32: andi [[T9:.*]],a1,0x1
; MIPS32: andi [[T1]],[[T1]],0x1
; MIPS32: andi [[T5]],[[T5]],0x1
; MIPS32: movn [[T5]],[[T1]],[[T9]]
; MIPS32: andi [[T10:.*]],a2,0x1
; MIPS32: andi [[T2]],[[T2]],0x1
; MIPS32: andi [[T6]],[[T6]],0x1
; MIPS32: movn [[T6]],[[T2]],[[T10]]
; MIPS32: andi [[T11:.*]],a3,0x1
; MIPS32: andi [[T3]],[[T3]],0x1
; MIPS32: andi [[T7]],[[T7]],0x1
; MIPS32: movn [[T7]],[[T3]],[[T11]]
; MIPS32: move v0,[[T4]]
; MIPS32: move v1,[[T5]]
; MIPS32: move a0,[[T6]]
; MIPS32: move a1,[[T7]]
}
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