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Commit 3dbe7806 by Karl Schimpf
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Add VDIVS and VDIVD instructions to the integrated ARM assembler.

Also fixes some badly named locals for VSUBS and VSUBD. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1568933002 .
parent b3e2574c
Showing with 138 additions and 16 deletions
src/DartARM32/assembler_arm.cc
......@@ -1026,18 +1026,19 @@ void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
EmitVFPddd(cond, B6, dd, dn, dm);
}
#if 0
// Moved to Arm32::AssemblerARM32::vdivs()
void Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
Condition cond) {
EmitVFPsss(cond, B23, sd, sn, sm);
}
// Moved to Arm32::AssemblerARM32::vdivd()
void Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
Condition cond) {
EmitVFPddd(cond, B23, dd, dn, dm);
}
#endif
void Assembler::vabss(SRegister sd, SRegister sm, Condition cond) {
EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
......
src/DartARM32/assembler_arm.h
......@@ -673,8 +673,12 @@ class Assembler : public ValueObject {
void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
#if 0
// Moved to Arm32::AssemblerARM32::vdivs()
void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
// Moved to Arm32::AssemblerARM32::vdivd()
void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
#endif
void vminqs(QRegister qd, QRegister qn, QRegister qm);
void vmaxqs(QRegister qd, QRegister qn, QRegister qm);
void vrecpeqs(QRegister qd, QRegister qm);
......
src/IceAssemblerARM32.cpp
......@@ -2071,6 +2071,36 @@ void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
}
void AssemblerARM32::vdivs(const Operand *OpSd, const Operand *OpSn,
const Operand *OpSm, CondARM32::Cond Cond) {
// VDIV (floating-point) - ARM section A8.8.283, encoding A2:
// vdiv<c>.f32 <Sd>, <Sn>, <Sm>
//
// cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
// and mmmmM=Rm.
constexpr const char *Vdivs = "vdivs";
IValueT Sd = encodeSRegister(OpSd, "Sd", Vdivs);
IValueT Sn = encodeSRegister(OpSn, "Sn", Vdivs);
IValueT Sm = encodeSRegister(OpSm, "Sm", Vdivs);
constexpr IValueT VdivsOpcode = B23;
emitVFPsss(Cond, VdivsOpcode, Sd, Sn, Sm);
}
void AssemblerARM32::vdivd(const Operand *OpDd, const Operand *OpDn,
const Operand *OpDm, CondARM32::Cond Cond) {
// VDIV (floating-point) - ARM section A8.8.283, encoding A2:
// vdiv<c>.f64 <Dd>, <Dn>, <Dm>
//
// cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
// and Mmmmm=Rm.
constexpr const char *Vdivd = "vdivd";
IValueT Dd = encodeDRegister(OpDd, "Dd", Vdivd);
IValueT Dn = encodeDRegister(OpDn, "Dn", Vdivd);
IValueT Dm = encodeDRegister(OpDm, "Dm", Vdivd);
constexpr IValueT VdivdOpcode = B23;
emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
}
void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
const Operand *OpSm, CondARM32::Cond Cond) {
// VSUB (floating-point) - ARM section A8.8.415, encoding A2:
......@@ -2078,27 +2108,27 @@ void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
//
// cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
// and mmmmM=Rm.
constexpr const char *Vadds = "vsubs";
IValueT Sd = encodeSRegister(OpSd, "Sd", Vadds);
IValueT Sn = encodeSRegister(OpSn, "Sn", Vadds);
IValueT Sm = encodeSRegister(OpSm, "Sm", Vadds);
constexpr IValueT VaddsOpcode = B21 | B20 | B6;
emitVFPsss(Cond, VaddsOpcode, Sd, Sn, Sm);
constexpr const char *Vsubs = "vsubs";
IValueT Sd = encodeSRegister(OpSd, "Sd", Vsubs);
IValueT Sn = encodeSRegister(OpSn, "Sn", Vsubs);
IValueT Sm = encodeSRegister(OpSm, "Sm", Vsubs);
constexpr IValueT VsubsOpcode = B21 | B20 | B6;
emitVFPsss(Cond, VsubsOpcode, Sd, Sn, Sm);
}
void AssemblerARM32::vsubd(const Operand *OpDd, const Operand *OpDn,
const Operand *OpDm, CondARM32::Cond Cond) {
// VSUB (floating-point) - ARM section A8.8.415, encoding A2:
// vadd<c>.f64 <Dd>, <Dn>, <Dm>
// vsub<c>.f64 <Dd>, <Dn>, <Dm>
//
// cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
// and Mmmmm=Rm.
constexpr const char *Vaddd = "vsubd";
IValueT Dd = encodeDRegister(OpDd, "Dd", Vaddd);
IValueT Dn = encodeDRegister(OpDn, "Dn", Vaddd);
IValueT Dm = encodeDRegister(OpDm, "Dm", Vaddd);
constexpr IValueT VadddOpcode = B21 | B20 | B6;
emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
constexpr const char *Vsubd = "vsubd";
IValueT Dd = encodeDRegister(OpDd, "Dd", Vsubd);
IValueT Dn = encodeDRegister(OpDn, "Dn", Vsubd);
IValueT Dm = encodeDRegister(OpDm, "Dm", Vsubd);
constexpr IValueT VsubdOpcode = B21 | B20 | B6;
emitVFPddd(Cond, VsubdOpcode, Dd, Dn, Dm);
}
void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
......
src/IceAssemblerARM32.h
......@@ -324,6 +324,12 @@ public:
void vadds(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
CondARM32::Cond Cond);
void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
CondARM32::Cond Cond);
void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
CondARM32::Cond Cond);
void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
CondARM32::Cond Cond);
......
src/IceInstARM32.cpp
......@@ -615,6 +615,24 @@ template <> void InstARM32Vadd::emitIAS(const Cfg *Func) const {
assert(!Asm->needsTextFixup());
}
template <> void InstARM32Vdiv::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
const Variable *Dest = getDest();
switch (Dest->getType()) {
default:
// TODO(kschimpf) Figure if more cases are needed.
Asm->setNeedsTextFixup();
break;
case IceType_f32:
Asm->vdivs(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
break;
case IceType_f64:
Asm->vdivd(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
break;
}
assert(!Asm->needsTextFixup());
}
template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
const Variable *Dest = getDest();
......
tests_lit/assembler/arm32/vdiv.ll 0 → 100644
; Show that we know how to translate vdiv.
; NOTE: We use -O2 to get rid of memory stores.
; REQUIRES: allow_dump
; Compile using standalone assembler.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
; RUN: | FileCheck %s --check-prefix=ASM
; Show bytes in assembled standalone code.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
; Compile using integrated assembler.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
; RUN: | FileCheck %s --check-prefix=IASM
; Show bytes in assembled integrated code.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
define internal float @testVdivFloat(float %v1, float %v2) {
; ASM-LABEL: testVdivFloat:
; DIS-LABEL: 00000000 <testVdivFloat>:
; IASM-LABEL: testVdivFloat:
entry:
; ASM-NEXT: .LtestVdivFloat$entry:
; IASM-NEXT: .LtestVdivFloat$entry:
%res = fdiv float %v1, %v2
; ASM-NEXT: vdiv.f32 s0, s0, s1
; DIS-NEXT: 0: ee800a20
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0xa
; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0xee
ret float %res
}
define internal double @testVdivDouble(double %v1, double %v2) {
; ASM-LABEL: testVdivDouble:
; DIS-LABEL: 00000010 <testVdivDouble>:
; IASM-LABEL: testVdivDouble:
entry:
; ASM-NEXT: .LtestVdivDouble$entry:
; IASM-NEXT: .LtestVdivDouble$entry:
%res = fdiv double %v1, %v2
; ASM-NEXT: vdiv.f64 d0, d0, d1
; DIS-NEXT: 10: ee800b01
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0xee
ret double %res
}
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