Compute the size of the stack space required to send the parameters to a call.

src/IceTargetLoweringMIPS32.cpp

@@ -94,7 +94,7 @@ void TargetMIPS32::translateO2() {
   genTargetHelperCalls();
 
   // Merge Alloca instructions, and lay out the stack.
-  static constexpr bool SortAndCombineAllocas = true;
+  static constexpr bool SortAndCombineAllocas = false;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 

src/IceTargetLoweringX8632Traits.h

@@ -579,6 +579,8 @@ template <> struct MachineTraits<TargetX8632> {
 
   /// The maximum number of arguments to pass in XMM registers
   static const uint32_t X86_MAX_XMM_ARGS = 4;
+  /// The maximum number of arguments to pass in GPR registers
+  static const uint32_t X86_MAX_GPR_ARGS = 0;
   /// The number of bits in a byte
   static const uint32_t X86_CHAR_BIT = 8;
   /// Stack alignment. This is defined in IceTargetLoweringX8632.cpp because it

src/IceTargetLoweringX86Base.h

@@ -182,10 +182,7 @@ protected:
   void lowerOther(const Inst *Instr) override;
   void lowerRMW(const typename Traits::Insts::FakeRMW *RMW);
   void prelowerPhis() override;
-  uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override {
-    (void)Instr;
-    return 0;
-  }
+  uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
   void genTargetHelperCallFor(Inst *Instr) override { (void)Instr; }
   void doAddressOptLoad() override;
   void doAddressOptStore() override;

src/IceTargetLoweringX86BaseImpl.h

@@ -5323,6 +5323,49 @@ template <class Machine> void TargetX86Base<Machine>::prelowerPhis() {
 }
 
 template <class Machine>
+uint32_t
+TargetX86Base<Machine>::getCallStackArgumentsSizeBytes(const InstCall *Instr) {
+  uint32_t OutArgumentsSizeBytes = 0;
+  uint32_t XmmArgCount = 0;
+  uint32_t GprArgCount = 0;
+  // Classify each argument operand according to the location where the
+  // argument is passed.
+  for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
+    Operand *Arg = Instr->getArg(i);
+    Type Ty = Arg->getType();
+    // The PNaCl ABI requires the width of arguments to be at least 32 bits.
+    assert(typeWidthInBytes(Ty) >= 4);
+    if (isVectorType(Ty) && XmmArgCount < Traits::X86_MAX_XMM_ARGS) {
+      ++XmmArgCount;
+    } else if (isScalarIntegerType(Ty) &&
+               GprArgCount < Traits::X86_MAX_GPR_ARGS) {
+      // The 64 bit ABI allows some integers to be passed in GPRs.
+      ++GprArgCount;
+    } else {
+      if (isVectorType(Arg->getType())) {
+        OutArgumentsSizeBytes =
+            Traits::applyStackAlignment(OutArgumentsSizeBytes);
+      }
+      OutArgumentsSizeBytes += typeWidthInBytesOnStack(Arg->getType());
+    }
+  }
+  if (Traits::Is64Bit)
+    return OutArgumentsSizeBytes;
+  // The 32 bit ABI requires floating point values to be returned on the x87 FP
+  // stack. Ensure there is enough space for the fstp/movs for floating returns.
+  Variable *Dest = Instr->getDest();
+  if (Dest == nullptr)
+    return OutArgumentsSizeBytes;
+  const Type DestType = Dest->getType();
+  if (isScalarFloatingType(Dest->getType())) {
+    OutArgumentsSizeBytes =
+        std::max(OutArgumentsSizeBytes,
+                 static_cast<uint32_t>(typeWidthInBytesOnStack(DestType)));
+  }
+  return OutArgumentsSizeBytes;
+}
+
+template <class Machine>
 Variable *TargetX86Base<Machine>::makeZeroedRegister(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   switch (Ty) {