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Commit 4a56686b by John Porto
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Subzero. Code organization.

This CL does more than any CL should. First, it moves all target-specific classes (TargetLowering, Assembler, and Instructions) to a target-specific namespace. For example, the ::Ice::TargetX8632 class now lives in ::Ice::X8632::TargetX8632. Same goes for ARM32, X8664, and MIPS32. Now, we have a ton of redundant prefixes (it should be pretty obvious that ::Ice::X8632::TargetLowering is an X8632 target lowering), but this is definitively not something for this CL. Second, this CL gets rid of the excessive use of 'typename Foo::Bar' in the X86 templates. These changes appear more intimidating than they really are, and they were fairly mechanical. Third, the x86?? Traitses (gollum!) classes are no longer template instatiation. The previous X86 templates were parameterized with a X86 TargetLowering, and they assumed that a MachineTraits<Target> was defined for that TargetLowering. The X86 templates are now parameterized with a TraitsType, and different backends may have completely unrelated traits. Fourth, the X86 templates are no longer members of ::Ice::X86Internal. Instead, each file #include'ing a Ice*X86Base.h file need to #define X86NAMESPACE to the namespace where the backend is being defined. With this change, the template instantiation for X8632 live in ::Ice::X8632, and, for X8664, in ::Ice::X8664. BUG= R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1548363002 .
parent 4a308ced
Showing with 1187 additions and 1405 deletions
src/IceAssemblerX8632.h
......@@ -16,47 +16,24 @@
//===----------------------------------------------------------------------===//
///
/// \file
/// \brief Implements the Assembler class for x86-32.
/// \brief Instantiates the Assembler for X86-32.
///
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICEASSEMBLERX8632_H
#define SUBZERO_SRC_ICEASSEMBLERX8632_H
#include "IceAssembler.h"
#define X86NAMESPACE X8632
#include "IceAssemblerX86Base.h"
#include "IceDefs.h"
#include "IceOperand.h"
#undef X86NAMESPACE
#include "IceTargetLoweringX8632Traits.h"
#include "IceTypes.h"
#include "IceUtils.h"
namespace Ice {
class TargetX8632;
namespace X8632 {
using Immediate = ::Ice::X86Internal::Immediate;
using Label = ::Ice::X86Internal::Label;
class AssemblerX8632 : public X86Internal::AssemblerX86Base<TargetX8632> {
AssemblerX8632(const AssemblerX8632 &) = delete;
AssemblerX8632 &operator=(const AssemblerX8632 &) = delete;
public:
explicit AssemblerX8632(bool use_far_branches = false)
: X86Internal::AssemblerX86Base<TargetX8632>(Asm_X8632,
use_far_branches) {}
~AssemblerX8632() override = default;
static bool classof(const Assembler *Asm) {
return Asm->getKind() == Asm_X8632;
}
private:
ENABLE_MAKE_UNIQUE;
};
using AssemblerX8632 = AssemblerX86Base<X8632::Traits>;
using Label = AssemblerX8632::Label;
using Immediate = AssemblerX8632::Immediate;
} // end of namespace X8632
} // end of namespace Ice
......
src/IceAssemblerX8664.h
......@@ -16,47 +16,24 @@
//===----------------------------------------------------------------------===//
///
/// \file
/// \brief Implements the Assembler class for x86-64.
/// \brief Instantiates the Assembler for X86-64.
///
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICEASSEMBLERX8664_H
#define SUBZERO_SRC_ICEASSEMBLERX8664_H
#include "IceAssembler.h"
#define X86NAMESPACE X8664
#include "IceAssemblerX86Base.h"
#include "IceDefs.h"
#include "IceOperand.h"
#undef X86NAMESPACE
#include "IceTargetLoweringX8664Traits.h"
#include "IceTypes.h"
#include "IceUtils.h"
namespace Ice {
class TargetX8664;
namespace X8664 {
using Immediate = ::Ice::X86Internal::Immediate;
using Label = ::Ice::X86Internal::Label;
class AssemblerX8664 : public X86Internal::AssemblerX86Base<TargetX8664> {
AssemblerX8664(const AssemblerX8664 &) = delete;
AssemblerX8664 &operator=(const AssemblerX8664 &) = delete;
public:
explicit AssemblerX8664(bool use_far_branches = false)
: X86Internal::AssemblerX86Base<TargetX8664>(Asm_X8664,
use_far_branches) {}
~AssemblerX8664() override = default;
static bool classof(const Assembler *Asm) {
return Asm->getKind() == Asm_X8664;
}
private:
ENABLE_MAKE_UNIQUE;
};
using AssemblerX8664 = AssemblerX86Base<X8664::Traits>;
using Label = AssemblerX8664::Label;
using Immediate = AssemblerX8664::Immediate;
} // end of namespace X8664
} // end of namespace Ice
......
src/IceAssemblerX86Base.h
......@@ -32,102 +32,116 @@
namespace Ice {
namespace X86Internal {
#ifndef X86NAMESPACE
#error "You must define the X86 Target namespace."
#endif
template <class Machine> class AssemblerX86Base;
template <class Machine> struct MachineTraits;
namespace X86NAMESPACE {
constexpr int MAX_NOP_SIZE = 8;
template <typename TraitsType>
class AssemblerX86Base : public ::Ice::Assembler {
AssemblerX86Base(const AssemblerX86Base &) = delete;
AssemblerX86Base &operator=(const AssemblerX86Base &) = delete;
class Immediate {
Immediate(const Immediate &) = delete;
Immediate &operator=(const Immediate &) = delete;
protected:
explicit AssemblerX86Base(bool use_far_branches = false)
: Assembler(Traits::AsmKind) {
// This mode is only needed and implemented for MIPS and ARM.
assert(!use_far_branches);
(void)use_far_branches;
}
public:
explicit Immediate(int32_t value) : value_(value) {}
Immediate(RelocOffsetT offset, AssemblerFixup *fixup)
: value_(offset), fixup_(fixup) {
// Use the Offset in the "value" for now. If we decide to process fixups,
// we'll need to patch that offset with the true value.
using Traits = TraitsType;
using Address = typename Traits::Address;
using ByteRegister = typename Traits::ByteRegister;
using BrCond = typename Traits::Cond::BrCond;
using CmppsCond = typename Traits::Cond::CmppsCond;
using GPRRegister = typename Traits::GPRRegister;
using Operand = typename Traits::Operand;
using XmmRegister = typename Traits::XmmRegister;
static constexpr int MAX_NOP_SIZE = 8;
static bool classof(const Assembler *Asm) {
return Asm->getKind() == Traits::AsmKind;
}
int32_t value() const { return value_; }
AssemblerFixup *fixup() const { return fixup_; }
class Immediate {
Immediate(const Immediate &) = delete;
Immediate &operator=(const Immediate &) = delete;
bool is_int8() const {
// We currently only allow 32-bit fixups, and they usually have value = 0,
// so if fixup_ != nullptr, it shouldn't be classified as int8/16.
return fixup_ == nullptr && Utils::IsInt(8, value_);
}
bool is_uint8() const {
return fixup_ == nullptr && Utils::IsUint(8, value_);
}
bool is_uint16() const {
return fixup_ == nullptr && Utils::IsUint(16, value_);
}
public:
explicit Immediate(int32_t value) : value_(value) {}
private:
const int32_t value_;
AssemblerFixup *fixup_ = nullptr;
};
Immediate(RelocOffsetT offset, AssemblerFixup *fixup)
: value_(offset), fixup_(fixup) {
// Use the Offset in the "value" for now. If we decide to process fixups,
// we'll need to patch that offset with the true value.
}
/// X86 allows near and far jumps.
class Label final : public Ice::Label {
Label(const Label &) = delete;
Label &operator=(const Label &) = delete;
int32_t value() const { return value_; }
AssemblerFixup *fixup() const { return fixup_; }
public:
Label() = default;
~Label() = default;
bool is_int8() const {
// We currently only allow 32-bit fixups, and they usually have value = 0,
// so if fixup_ != nullptr, it shouldn't be classified as int8/16.
return fixup_ == nullptr && Utils::IsInt(8, value_);
}
bool is_uint8() const {
return fixup_ == nullptr && Utils::IsUint(8, value_);
}
bool is_uint16() const {
return fixup_ == nullptr && Utils::IsUint(16, value_);
}
void finalCheck() const override {
Ice::Label::finalCheck();
assert(!hasNear());
}
private:
const int32_t value_;
AssemblerFixup *fixup_ = nullptr;
};
/// Returns the position of an earlier branch instruction which assumes that
/// this label is "near", and bumps iterator to the next near position.
intptr_t getNearPosition() {
assert(hasNear());
intptr_t Pos = UnresolvedNearPositions.back();
UnresolvedNearPositions.pop_back();
return Pos;
}
/// X86 allows near and far jumps.
class Label final : public Ice::Label {
Label(const Label &) = delete;
Label &operator=(const Label &) = delete;
bool hasNear() const { return !UnresolvedNearPositions.empty(); }
bool isUnused() const override {
return Ice::Label::isUnused() && !hasNear();
}
public:
Label() = default;
~Label() = default;
private:
void nearLinkTo(const Assembler &Asm, intptr_t position) {
if (Asm.getPreliminary())
return;
assert(!isBound());
UnresolvedNearPositions.push_back(position);
}
void finalCheck() const override {
Ice::Label::finalCheck();
assert(!hasNear());
}
llvm::SmallVector<intptr_t, 20> UnresolvedNearPositions;
/// Returns the position of an earlier branch instruction which assumes that
/// this label is "near", and bumps iterator to the next near position.
intptr_t getNearPosition() {
assert(hasNear());
intptr_t Pos = UnresolvedNearPositions.back();
UnresolvedNearPositions.pop_back();
return Pos;
}
template <class> friend class AssemblerX86Base;
};
bool hasNear() const { return !UnresolvedNearPositions.empty(); }
bool isUnused() const override {
return Ice::Label::isUnused() && !hasNear();
}
template <class Machine> class AssemblerX86Base : public Assembler {
AssemblerX86Base(const AssemblerX86Base &) = delete;
AssemblerX86Base &operator=(const AssemblerX86Base &) = delete;
private:
friend class AssemblerX86Base<TraitsType>;
protected:
AssemblerX86Base(AssemblerKind Kind, bool use_far_branches)
: Assembler(Kind) {
// This mode is only needed and implemented for MIPS and ARM.
assert(!use_far_branches);
(void)use_far_branches;
}
void nearLinkTo(const Assembler &Asm, intptr_t position) {
if (Asm.getPreliminary())
return;
assert(!isBound());
UnresolvedNearPositions.push_back(position);
}
public:
using Traits = MachineTraits<Machine>;
llvm::SmallVector<intptr_t, 20> UnresolvedNearPositions;
};
public:
~AssemblerX86Base() override;
static const bool kNearJump = true;
......@@ -166,21 +180,19 @@ public:
}
// Operations to emit GPR instructions (and dispatch on operand type).
using TypedEmitGPR = void (AssemblerX86Base::*)(Type,
typename Traits::GPRRegister);
using TypedEmitAddr =
void (AssemblerX86Base::*)(Type, const typename Traits::Address &);
using TypedEmitGPR = void (AssemblerX86Base::*)(Type, GPRRegister);
using TypedEmitAddr = void (AssemblerX86Base::*)(Type, const Address &);
struct GPREmitterOneOp {
TypedEmitGPR Reg;
TypedEmitAddr Addr;
};
using TypedEmitGPRGPR = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, typename Traits::GPRRegister);
using TypedEmitGPRAddr = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, const typename Traits::Address &);
using TypedEmitGPRImm = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, const Immediate &);
using TypedEmitGPRGPR = void (AssemblerX86Base::*)(Type, GPRRegister,
GPRRegister);
using TypedEmitGPRAddr = void (AssemblerX86Base::*)(Type, GPRRegister,
const Address &);
using TypedEmitGPRImm = void (AssemblerX86Base::*)(Type, GPRRegister,
const Immediate &);
struct GPREmitterRegOp {
TypedEmitGPRGPR GPRGPR;
TypedEmitGPRAddr GPRAddr;
......@@ -188,15 +200,15 @@ public:
};
struct GPREmitterShiftOp {
// Technically, Addr/GPR and Addr/Imm are also allowed, but */Addr are not.
// In practice, we always normalize the Dest to a Register first.
// Technically, Addr/GPR and Addr/Imm are also allowed, but */Addr are
// not. In practice, we always normalize the Dest to a Register first.
TypedEmitGPRGPR GPRGPR;
TypedEmitGPRImm GPRImm;
};
using TypedEmitGPRGPRImm = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, typename Traits::GPRRegister,
const Immediate &);
using TypedEmitGPRGPRImm = void (AssemblerX86Base::*)(Type, GPRRegister,
GPRRegister,
const Immediate &);
struct GPREmitterShiftD {
// Technically AddrGPR and AddrGPRImm are also allowed, but in practice we
// always normalize Dest to a Register first.
......@@ -204,39 +216,36 @@ public:
TypedEmitGPRGPRImm GPRGPRImm;
};
using TypedEmitAddrGPR = void (AssemblerX86Base::*)(
Type, const typename Traits::Address &, typename Traits::GPRRegister);
using TypedEmitAddrImm = void (AssemblerX86Base::*)(
Type, const typename Traits::Address &, const Immediate &);
using TypedEmitAddrGPR = void (AssemblerX86Base::*)(Type, const Address &,
GPRRegister);
using TypedEmitAddrImm = void (AssemblerX86Base::*)(Type, const Address &,
const Immediate &);
struct GPREmitterAddrOp {
TypedEmitAddrGPR AddrGPR;
TypedEmitAddrImm AddrImm;
};
// Operations to emit XMM instructions (and dispatch on operand type).
using TypedEmitXmmXmm = void (AssemblerX86Base::*)(
Type, typename Traits::XmmRegister, typename Traits::XmmRegister);
using TypedEmitXmmAddr = void (AssemblerX86Base::*)(
Type, typename Traits::XmmRegister, const typename Traits::Address &);
using TypedEmitXmmXmm = void (AssemblerX86Base::*)(Type, XmmRegister,
XmmRegister);
using TypedEmitXmmAddr = void (AssemblerX86Base::*)(Type, XmmRegister,
const Address &);
struct XmmEmitterRegOp {
TypedEmitXmmXmm XmmXmm;
TypedEmitXmmAddr XmmAddr;
};
using EmitXmmXmm = void (AssemblerX86Base::*)(typename Traits::XmmRegister,
typename Traits::XmmRegister);
using EmitXmmAddr = void (AssemblerX86Base::*)(
typename Traits::XmmRegister, const typename Traits::Address &);
using EmitAddrXmm = void (AssemblerX86Base::*)(
const typename Traits::Address &, typename Traits::XmmRegister);
using EmitXmmXmm = void (AssemblerX86Base::*)(XmmRegister, XmmRegister);
using EmitXmmAddr = void (AssemblerX86Base::*)(XmmRegister, const Address &);
using EmitAddrXmm = void (AssemblerX86Base::*)(const Address &, XmmRegister);
struct XmmEmitterMovOps {
EmitXmmXmm XmmXmm;
EmitXmmAddr XmmAddr;
EmitAddrXmm AddrXmm;
};
using TypedEmitXmmImm = void (AssemblerX86Base::*)(
Type, typename Traits::XmmRegister, const Immediate &);
using TypedEmitXmmImm = void (AssemblerX86Base::*)(Type, XmmRegister,
const Immediate &);
struct XmmEmitterShiftOp {
TypedEmitXmmXmm XmmXmm;
......@@ -248,8 +257,8 @@ public:
template <typename DReg_t, typename SReg_t> struct CastEmitterRegOp {
using TypedEmitRegs = void (AssemblerX86Base::*)(Type, DReg_t, Type,
SReg_t);
using TypedEmitAddr = void (AssemblerX86Base::*)(
Type, DReg_t, Type, const typename Traits::Address &);
using TypedEmitAddr = void (AssemblerX86Base::*)(Type, DReg_t, Type,
const Address &);
TypedEmitRegs RegReg;
TypedEmitAddr RegAddr;
......@@ -260,8 +269,9 @@ public:
template <typename DReg_t, typename SReg_t> struct ThreeOpImmEmitter {
using TypedEmitRegRegImm = void (AssemblerX86Base::*)(Type, DReg_t, SReg_t,
const Immediate &);
using TypedEmitRegAddrImm = void (AssemblerX86Base::*)(
Type, DReg_t, const typename Traits::Address &, const Immediate &);
using TypedEmitRegAddrImm = void (AssemblerX86Base::*)(Type, DReg_t,
const Address &,
const Immediate &);
TypedEmitRegRegImm RegRegImm;
TypedEmitRegAddrImm RegAddrImm;
......@@ -270,17 +280,17 @@ public:
/*
* Emit Machine Instructions.
*/
void call(typename Traits::GPRRegister reg);
void call(const typename Traits::Address &address);
void call(GPRRegister reg);
void call(const Address &address);
void call(const ConstantRelocatable *label); // not testable.
void call(const Immediate &abs_address);
static const intptr_t kCallExternalLabelSize = 5;
void pushl(typename Traits::GPRRegister reg);
void pushl(GPRRegister reg);
void popl(typename Traits::GPRRegister reg);
void popl(const typename Traits::Address &address);
void popl(GPRRegister reg);
void popl(const Address &address);
template <typename T = Traits,
typename = typename std::enable_if<T::HasPusha>::type>
......@@ -289,309 +299,190 @@ public:
typename = typename std::enable_if<T::HasPopa>::type>
void popal();
void setcc(typename Traits::Cond::BrCond condition,
typename Traits::ByteRegister dst);
void setcc(typename Traits::Cond::BrCond condition,
const typename Traits::Address &address);
void setcc(BrCond condition, ByteRegister dst);
void setcc(BrCond condition, const Address &address);
void mov(Type Ty, typename Traits::GPRRegister dst, const Immediate &src);
void mov(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void mov(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void mov(Type Ty, const typename Traits::Address &dst,
typename Traits::GPRRegister src);
void mov(Type Ty, const typename Traits::Address &dst, const Immediate &imm);
void mov(Type Ty, GPRRegister dst, const Immediate &src);
void mov(Type Ty, GPRRegister dst, GPRRegister src);
void mov(Type Ty, GPRRegister dst, const Address &src);
void mov(Type Ty, const Address &dst, GPRRegister src);
void mov(Type Ty, const Address &dst, const Immediate &imm);
template <typename T = Traits>
typename std::enable_if<T::Is64Bit, void>::type
movabs(const typename Traits::GPRRegister Dst, uint64_t Imm64);
typename std::enable_if<T::Is64Bit, void>::type movabs(const GPRRegister Dst,
uint64_t Imm64);
template <typename T = Traits>
typename std::enable_if<!T::Is64Bit, void>::type
movabs(const typename Traits::GPRRegister, uint64_t) {
typename std::enable_if<!T::Is64Bit, void>::type movabs(const GPRRegister,
uint64_t) {
llvm::report_fatal_error("movabs is only supported in 64-bit x86 targets.");
}
void movzx(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void movzx(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void movsx(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void movsx(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void movzx(Type Ty, GPRRegister dst, GPRRegister src);
void movzx(Type Ty, GPRRegister dst, const Address &src);
void movsx(Type Ty, GPRRegister dst, GPRRegister src);
void movsx(Type Ty, GPRRegister dst, const Address &src);
void lea(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void lea(Type Ty, GPRRegister dst, const Address &src);
void cmov(Type Ty, typename Traits::Cond::BrCond cond,
typename Traits::GPRRegister dst, typename Traits::GPRRegister src);
void cmov(Type Ty, typename Traits::Cond::BrCond cond,
typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void cmov(Type Ty, BrCond cond, GPRRegister dst, GPRRegister src);
void cmov(Type Ty, BrCond cond, GPRRegister dst, const Address &src);
void rep_movsb();
void movss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void movss(Type Ty, const typename Traits::Address &dst,
typename Traits::XmmRegister src);
void movss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void movd(Type SrcTy, typename Traits::XmmRegister dst,
typename Traits::GPRRegister src);
void movd(Type SrcTy, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void movd(Type DestTy, typename Traits::GPRRegister dst,
typename Traits::XmmRegister src);
void movd(Type DestTy, const typename Traits::Address &dst,
typename Traits::XmmRegister src);
void movq(typename Traits::XmmRegister dst, typename Traits::XmmRegister src);
void movq(const typename Traits::Address &dst,
typename Traits::XmmRegister src);
void movq(typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void addss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void addss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void subss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void subss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void mulss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void mulss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void divss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void divss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void movaps(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void movups(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void movups(typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void movups(const typename Traits::Address &dst,
typename Traits::XmmRegister src);
void padd(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void padd(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pand(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pand(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pandn(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pandn(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pmull(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pmull(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pmuludq(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pmuludq(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void por(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void por(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void psub(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void psub(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pxor(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pxor(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void psll(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void psll(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void psll(Type Ty, typename Traits::XmmRegister dst, const Immediate &src);
void psra(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void psra(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void psra(Type Ty, typename Traits::XmmRegister dst, const Immediate &src);
void psrl(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void psrl(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void psrl(Type Ty, typename Traits::XmmRegister dst, const Immediate &src);
void addps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void addps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void subps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void subps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void divps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void divps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void mulps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void mulps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void minps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void minps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void minss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void minss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void maxps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void maxps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void maxss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void maxss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void andnps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void andnps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void andps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void andps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void orps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void orps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void blendvps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void blendvps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pblendvb(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pblendvb(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void cmpps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src,
typename Traits::Cond::CmppsCond CmpCondition);
void cmpps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src,
typename Traits::Cond::CmppsCond CmpCondition);
void sqrtps(typename Traits::XmmRegister dst);
void rsqrtps(typename Traits::XmmRegister dst);
void reciprocalps(typename Traits::XmmRegister dst);
void movhlps(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void movlhps(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void unpcklps(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void unpckhps(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void unpcklpd(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void unpckhpd(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void set1ps(typename Traits::XmmRegister dst,
typename Traits::GPRRegister tmp, const Immediate &imm);
void sqrtpd(typename Traits::XmmRegister dst);
void pshufd(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src, const Immediate &mask);
void pshufd(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src, const Immediate &mask);
void shufps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src, const Immediate &mask);
void shufps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src, const Immediate &mask);
void cvtdq2ps(Type, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void cvtdq2ps(Type, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void cvttps2dq(Type, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void cvttps2dq(Type, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void cvtsi2ss(Type DestTy, typename Traits::XmmRegister dst, Type SrcTy,
typename Traits::GPRRegister src);
void cvtsi2ss(Type DestTy, typename Traits::XmmRegister dst, Type SrcTy,
const typename Traits::Address &src);
void cvtfloat2float(Type SrcTy, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void cvtfloat2float(Type SrcTy, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void cvttss2si(Type DestTy, typename Traits::GPRRegister dst, Type SrcTy,
typename Traits::XmmRegister src);
void cvttss2si(Type DestTy, typename Traits::GPRRegister dst, Type SrcTy,
const typename Traits::Address &src);
void ucomiss(Type Ty, typename Traits::XmmRegister a,
typename Traits::XmmRegister b);
void ucomiss(Type Ty, typename Traits::XmmRegister a,
const typename Traits::Address &b);
void movmskpd(typename Traits::GPRRegister dst,
typename Traits::XmmRegister src);
void movmskps(typename Traits::GPRRegister dst,
typename Traits::XmmRegister src);
void sqrtss(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void sqrtss(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void xorps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void xorps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void insertps(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src, const Immediate &imm);
void insertps(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src, const Immediate &imm);
void pinsr(Type Ty, typename Traits::XmmRegister dst,
typename Traits::GPRRegister src, const Immediate &imm);
void pinsr(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src, const Immediate &imm);
void pextr(Type Ty, typename Traits::GPRRegister dst,
typename Traits::XmmRegister src, const Immediate &imm);
void pmovsxdq(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pcmpeq(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pcmpeq(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void pcmpgt(Type Ty, typename Traits::XmmRegister dst,
typename Traits::XmmRegister src);
void pcmpgt(Type Ty, typename Traits::XmmRegister dst,
const typename Traits::Address &src);
void movss(Type Ty, XmmRegister dst, const Address &src);
void movss(Type Ty, const Address &dst, XmmRegister src);
void movss(Type Ty, XmmRegister dst, XmmRegister src);
void movd(Type SrcTy, XmmRegister dst, GPRRegister src);
void movd(Type SrcTy, XmmRegister dst, const Address &src);
void movd(Type DestTy, GPRRegister dst, XmmRegister src);
void movd(Type DestTy, const Address &dst, XmmRegister src);
void movq(XmmRegister dst, XmmRegister src);
void movq(const Address &dst, XmmRegister src);
void movq(XmmRegister dst, const Address &src);
void addss(Type Ty, XmmRegister dst, XmmRegister src);
void addss(Type Ty, XmmRegister dst, const Address &src);
void subss(Type Ty, XmmRegister dst, XmmRegister src);
void subss(Type Ty, XmmRegister dst, const Address &src);
void mulss(Type Ty, XmmRegister dst, XmmRegister src);
void mulss(Type Ty, XmmRegister dst, const Address &src);
void divss(Type Ty, XmmRegister dst, XmmRegister src);
void divss(Type Ty, XmmRegister dst, const Address &src);
void movaps(XmmRegister dst, XmmRegister src);
void movups(XmmRegister dst, XmmRegister src);
void movups(XmmRegister dst, const Address &src);
void movups(const Address &dst, XmmRegister src);
void padd(Type Ty, XmmRegister dst, XmmRegister src);
void padd(Type Ty, XmmRegister dst, const Address &src);
void pand(Type Ty, XmmRegister dst, XmmRegister src);
void pand(Type Ty, XmmRegister dst, const Address &src);
void pandn(Type Ty, XmmRegister dst, XmmRegister src);
void pandn(Type Ty, XmmRegister dst, const Address &src);
void pmull(Type Ty, XmmRegister dst, XmmRegister src);
void pmull(Type Ty, XmmRegister dst, const Address &src);
void pmuludq(Type Ty, XmmRegister dst, XmmRegister src);
void pmuludq(Type Ty, XmmRegister dst, const Address &src);
void por(Type Ty, XmmRegister dst, XmmRegister src);
void por(Type Ty, XmmRegister dst, const Address &src);
void psub(Type Ty, XmmRegister dst, XmmRegister src);
void psub(Type Ty, XmmRegister dst, const Address &src);
void pxor(Type Ty, XmmRegister dst, XmmRegister src);
void pxor(Type Ty, XmmRegister dst, const Address &src);
void psll(Type Ty, XmmRegister dst, XmmRegister src);
void psll(Type Ty, XmmRegister dst, const Address &src);
void psll(Type Ty, XmmRegister dst, const Immediate &src);
void psra(Type Ty, XmmRegister dst, XmmRegister src);
void psra(Type Ty, XmmRegister dst, const Address &src);
void psra(Type Ty, XmmRegister dst, const Immediate &src);
void psrl(Type Ty, XmmRegister dst, XmmRegister src);
void psrl(Type Ty, XmmRegister dst, const Address &src);
void psrl(Type Ty, XmmRegister dst, const Immediate &src);
void addps(Type Ty, XmmRegister dst, XmmRegister src);
void addps(Type Ty, XmmRegister dst, const Address &src);
void subps(Type Ty, XmmRegister dst, XmmRegister src);
void subps(Type Ty, XmmRegister dst, const Address &src);
void divps(Type Ty, XmmRegister dst, XmmRegister src);
void divps(Type Ty, XmmRegister dst, const Address &src);
void mulps(Type Ty, XmmRegister dst, XmmRegister src);
void mulps(Type Ty, XmmRegister dst, const Address &src);
void minps(Type Ty, XmmRegister dst, const Address &src);
void minps(Type Ty, XmmRegister dst, XmmRegister src);
void minss(Type Ty, XmmRegister dst, const Address &src);
void minss(Type Ty, XmmRegister dst, XmmRegister src);
void maxps(Type Ty, XmmRegister dst, const Address &src);
void maxps(Type Ty, XmmRegister dst, XmmRegister src);
void maxss(Type Ty, XmmRegister dst, const Address &src);
void maxss(Type Ty, XmmRegister dst, XmmRegister src);
void andnps(Type Ty, XmmRegister dst, const Address &src);
void andnps(Type Ty, XmmRegister dst, XmmRegister src);
void andps(Type Ty, XmmRegister dst, const Address &src);
void andps(Type Ty, XmmRegister dst, XmmRegister src);
void orps(Type Ty, XmmRegister dst, const Address &src);
void orps(Type Ty, XmmRegister dst, XmmRegister src);
void blendvps(Type Ty, XmmRegister dst, XmmRegister src);
void blendvps(Type Ty, XmmRegister dst, const Address &src);
void pblendvb(Type Ty, XmmRegister dst, XmmRegister src);
void pblendvb(Type Ty, XmmRegister dst, const Address &src);
void cmpps(Type Ty, XmmRegister dst, XmmRegister src, CmppsCond CmpCondition);
void cmpps(Type Ty, XmmRegister dst, const Address &src,
CmppsCond CmpCondition);
void sqrtps(XmmRegister dst);
void rsqrtps(XmmRegister dst);
void reciprocalps(XmmRegister dst);
void movhlps(XmmRegister dst, XmmRegister src);
void movlhps(XmmRegister dst, XmmRegister src);
void unpcklps(XmmRegister dst, XmmRegister src);
void unpckhps(XmmRegister dst, XmmRegister src);
void unpcklpd(XmmRegister dst, XmmRegister src);
void unpckhpd(XmmRegister dst, XmmRegister src);
void set1ps(XmmRegister dst, GPRRegister tmp, const Immediate &imm);
void sqrtpd(XmmRegister dst);
void pshufd(Type Ty, XmmRegister dst, XmmRegister src, const Immediate &mask);
void pshufd(Type Ty, XmmRegister dst, const Address &src,
const Immediate &mask);
void shufps(Type Ty, XmmRegister dst, XmmRegister src, const Immediate &mask);
void shufps(Type Ty, XmmRegister dst, const Address &src,
const Immediate &mask);
void cvtdq2ps(Type, XmmRegister dst, XmmRegister src);
void cvtdq2ps(Type, XmmRegister dst, const Address &src);
void cvttps2dq(Type, XmmRegister dst, XmmRegister src);
void cvttps2dq(Type, XmmRegister dst, const Address &src);
void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy, GPRRegister src);
void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy, const Address &src);
void cvtfloat2float(Type SrcTy, XmmRegister dst, XmmRegister src);
void cvtfloat2float(Type SrcTy, XmmRegister dst, const Address &src);
void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy, XmmRegister src);
void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy, const Address &src);
void ucomiss(Type Ty, XmmRegister a, XmmRegister b);
void ucomiss(Type Ty, XmmRegister a, const Address &b);
void movmskpd(GPRRegister dst, XmmRegister src);
void movmskps(GPRRegister dst, XmmRegister src);
void sqrtss(Type Ty, XmmRegister dst, const Address &src);
void sqrtss(Type Ty, XmmRegister dst, XmmRegister src);
void xorps(Type Ty, XmmRegister dst, const Address &src);
void xorps(Type Ty, XmmRegister dst, XmmRegister src);
void insertps(Type Ty, XmmRegister dst, XmmRegister src,
const Immediate &imm);
void insertps(Type Ty, XmmRegister dst, const Address &src,
const Immediate &imm);
void pinsr(Type Ty, XmmRegister dst, GPRRegister src, const Immediate &imm);
void pinsr(Type Ty, XmmRegister dst, const Address &src,
const Immediate &imm);
void pextr(Type Ty, GPRRegister dst, XmmRegister src, const Immediate &imm);
void pmovsxdq(XmmRegister dst, XmmRegister src);
void pcmpeq(Type Ty, XmmRegister dst, XmmRegister src);
void pcmpeq(Type Ty, XmmRegister dst, const Address &src);
void pcmpgt(Type Ty, XmmRegister dst, XmmRegister src);
void pcmpgt(Type Ty, XmmRegister dst, const Address &src);
enum RoundingMode {
kRoundToNearest = 0x0,
......@@ -599,8 +490,7 @@ public:
kRoundUp = 0x2,
kRoundToZero = 0x3
};
void roundsd(typename Traits::XmmRegister dst,
typename Traits::XmmRegister src, RoundingMode mode);
void roundsd(XmmRegister dst, XmmRegister src, RoundingMode mode);
//----------------------------------------------------------------------------
//
......@@ -646,93 +536,58 @@ public:
//
//----------------------------------------------------------------------------
void cmp(Type Ty, typename Traits::GPRRegister reg0,
typename Traits::GPRRegister reg1);
void cmp(Type Ty, typename Traits::GPRRegister reg,
const typename Traits::Address &address);
void cmp(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void cmp(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void cmp(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void test(Type Ty, typename Traits::GPRRegister reg0,
typename Traits::GPRRegister reg1);
void test(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void test(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void test(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void And(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void And(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &address);
void And(Type Ty, typename Traits::GPRRegister dst, const Immediate &imm);
void And(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void And(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void Or(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void Or(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &address);
void Or(Type Ty, typename Traits::GPRRegister dst, const Immediate &imm);
void Or(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void Or(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void Xor(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void Xor(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &address);
void Xor(Type Ty, typename Traits::GPRRegister dst, const Immediate &imm);
void Xor(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void Xor(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void add(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void add(Type Ty, typename Traits::GPRRegister reg,
const typename Traits::Address &address);
void add(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void add(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void add(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void adc(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void adc(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &address);
void adc(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void adc(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void adc(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void sub(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void sub(Type Ty, typename Traits::GPRRegister reg,
const typename Traits::Address &address);
void sub(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void sub(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void sub(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void sbb(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void sbb(Type Ty, typename Traits::GPRRegister reg,
const typename Traits::Address &address);
void sbb(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void sbb(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void sbb(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void cmp(Type Ty, GPRRegister reg0, GPRRegister reg1);
void cmp(Type Ty, GPRRegister reg, const Address &address);
void cmp(Type Ty, GPRRegister reg, const Immediate &imm);
void cmp(Type Ty, const Address &address, GPRRegister reg);
void cmp(Type Ty, const Address &address, const Immediate &imm);
void test(Type Ty, GPRRegister reg0, GPRRegister reg1);
void test(Type Ty, GPRRegister reg, const Immediate &imm);
void test(Type Ty, const Address &address, GPRRegister reg);
void test(Type Ty, const Address &address, const Immediate &imm);
void And(Type Ty, GPRRegister dst, GPRRegister src);
void And(Type Ty, GPRRegister dst, const Address &address);
void And(Type Ty, GPRRegister dst, const Immediate &imm);
void And(Type Ty, const Address &address, GPRRegister reg);
void And(Type Ty, const Address &address, const Immediate &imm);
void Or(Type Ty, GPRRegister dst, GPRRegister src);
void Or(Type Ty, GPRRegister dst, const Address &address);
void Or(Type Ty, GPRRegister dst, const Immediate &imm);
void Or(Type Ty, const Address &address, GPRRegister reg);
void Or(Type Ty, const Address &address, const Immediate &imm);
void Xor(Type Ty, GPRRegister dst, GPRRegister src);
void Xor(Type Ty, GPRRegister dst, const Address &address);
void Xor(Type Ty, GPRRegister dst, const Immediate &imm);
void Xor(Type Ty, const Address &address, GPRRegister reg);
void Xor(Type Ty, const Address &address, const Immediate &imm);
void add(Type Ty, GPRRegister dst, GPRRegister src);
void add(Type Ty, GPRRegister reg, const Address &address);
void add(Type Ty, GPRRegister reg, const Immediate &imm);
void add(Type Ty, const Address &address, GPRRegister reg);
void add(Type Ty, const Address &address, const Immediate &imm);
void adc(Type Ty, GPRRegister dst, GPRRegister src);
void adc(Type Ty, GPRRegister dst, const Address &address);
void adc(Type Ty, GPRRegister reg, const Immediate &imm);
void adc(Type Ty, const Address &address, GPRRegister reg);
void adc(Type Ty, const Address &address, const Immediate &imm);
void sub(Type Ty, GPRRegister dst, GPRRegister src);
void sub(Type Ty, GPRRegister reg, const Address &address);
void sub(Type Ty, GPRRegister reg, const Immediate &imm);
void sub(Type Ty, const Address &address, GPRRegister reg);
void sub(Type Ty, const Address &address, const Immediate &imm);
void sbb(Type Ty, GPRRegister dst, GPRRegister src);
void sbb(Type Ty, GPRRegister reg, const Address &address);
void sbb(Type Ty, GPRRegister reg, const Immediate &imm);
void sbb(Type Ty, const Address &address, GPRRegister reg);
void sbb(Type Ty, const Address &address, const Immediate &imm);
void cbw();
void cwd();
......@@ -744,93 +599,71 @@ public:
llvm::report_fatal_error("CQO is only available in 64-bit x86 backends.");
}
void div(Type Ty, typename Traits::GPRRegister reg);
void div(Type Ty, const typename Traits::Address &address);
void div(Type Ty, GPRRegister reg);
void div(Type Ty, const Address &address);
void idiv(Type Ty, typename Traits::GPRRegister reg);
void idiv(Type Ty, const typename Traits::Address &address);
void idiv(Type Ty, GPRRegister reg);
void idiv(Type Ty, const Address &address);
void imul(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void imul(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void imul(Type Ty, typename Traits::GPRRegister reg,
const typename Traits::Address &address);
void imul(Type Ty, GPRRegister dst, GPRRegister src);
void imul(Type Ty, GPRRegister reg, const Immediate &imm);
void imul(Type Ty, GPRRegister reg, const Address &address);
void imul(Type Ty, typename Traits::GPRRegister reg);
void imul(Type Ty, const typename Traits::Address &address);
void imul(Type Ty, GPRRegister reg);
void imul(Type Ty, const Address &address);
void imul(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src, const Immediate &imm);
void imul(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &address, const Immediate &imm);
void imul(Type Ty, GPRRegister dst, GPRRegister src, const Immediate &imm);
void imul(Type Ty, GPRRegister dst, const Address &address,
const Immediate &imm);
void mul(Type Ty, typename Traits::GPRRegister reg);
void mul(Type Ty, const typename Traits::Address &address);
void mul(Type Ty, GPRRegister reg);
void mul(Type Ty, const Address &address);
template <class T = Traits,
typename = typename std::enable_if<!T::Is64Bit>::type>
void incl(typename Traits::GPRRegister reg);
void incl(const typename Traits::Address &address);
void incl(GPRRegister reg);
void incl(const Address &address);
template <class T = Traits,
typename = typename std::enable_if<!T::Is64Bit>::type>
void decl(typename Traits::GPRRegister reg);
void decl(const typename Traits::Address &address);
void rol(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void rol(Type Ty, typename Traits::GPRRegister operand,
typename Traits::GPRRegister shifter);
void rol(Type Ty, const typename Traits::Address &operand,
typename Traits::GPRRegister shifter);
void shl(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void shl(Type Ty, typename Traits::GPRRegister operand,
typename Traits::GPRRegister shifter);
void shl(Type Ty, const typename Traits::Address &operand,
typename Traits::GPRRegister shifter);
void shr(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void shr(Type Ty, typename Traits::GPRRegister operand,
typename Traits::GPRRegister shifter);
void shr(Type Ty, const typename Traits::Address &operand,
typename Traits::GPRRegister shifter);
void sar(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
void sar(Type Ty, typename Traits::GPRRegister operand,
typename Traits::GPRRegister shifter);
void sar(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister shifter);
void shld(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void shld(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src, const Immediate &imm);
void shld(Type Ty, const typename Traits::Address &operand,
typename Traits::GPRRegister src);
void shrd(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void shrd(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src, const Immediate &imm);
void shrd(Type Ty, const typename Traits::Address &dst,
typename Traits::GPRRegister src);
void neg(Type Ty, typename Traits::GPRRegister reg);
void neg(Type Ty, const typename Traits::Address &addr);
void notl(typename Traits::GPRRegister reg);
void bsf(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void bsf(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void bsr(Type Ty, typename Traits::GPRRegister dst,
typename Traits::GPRRegister src);
void bsr(Type Ty, typename Traits::GPRRegister dst,
const typename Traits::Address &src);
void bswap(Type Ty, typename Traits::GPRRegister reg);
void bt(typename Traits::GPRRegister base,
typename Traits::GPRRegister offset);
void decl(GPRRegister reg);
void decl(const Address &address);
void rol(Type Ty, GPRRegister reg, const Immediate &imm);
void rol(Type Ty, GPRRegister operand, GPRRegister shifter);
void rol(Type Ty, const Address &operand, GPRRegister shifter);
void shl(Type Ty, GPRRegister reg, const Immediate &imm);
void shl(Type Ty, GPRRegister operand, GPRRegister shifter);
void shl(Type Ty, const Address &operand, GPRRegister shifter);
void shr(Type Ty, GPRRegister reg, const Immediate &imm);
void shr(Type Ty, GPRRegister operand, GPRRegister shifter);
void shr(Type Ty, const Address &operand, GPRRegister shifter);
void sar(Type Ty, GPRRegister reg, const Immediate &imm);
void sar(Type Ty, GPRRegister operand, GPRRegister shifter);
void sar(Type Ty, const Address &address, GPRRegister shifter);
void shld(Type Ty, GPRRegister dst, GPRRegister src);
void shld(Type Ty, GPRRegister dst, GPRRegister src, const Immediate &imm);
void shld(Type Ty, const Address &operand, GPRRegister src);
void shrd(Type Ty, GPRRegister dst, GPRRegister src);
void shrd(Type Ty, GPRRegister dst, GPRRegister src, const Immediate &imm);
void shrd(Type Ty, const Address &dst, GPRRegister src);
void neg(Type Ty, GPRRegister reg);
void neg(Type Ty, const Address &addr);
void notl(GPRRegister reg);
void bsf(Type Ty, GPRRegister dst, GPRRegister src);
void bsf(Type Ty, GPRRegister dst, const Address &src);
void bsr(Type Ty, GPRRegister dst, GPRRegister src);
void bsr(Type Ty, GPRRegister dst, const Address &src);
void bswap(Type Ty, GPRRegister reg);
void bt(GPRRegister base, GPRRegister offset);
void ret();
void ret(const Immediate &imm);
......@@ -842,27 +675,21 @@ public:
void ud2();
// j(Label) is fully tested.
void j(typename Traits::Cond::BrCond condition, Label *label,
bool near = kFarJump);
void j(typename Traits::Cond::BrCond condition,
const ConstantRelocatable *label); // not testable.
void j(BrCond condition, Label *label, bool near = kFarJump);
void j(BrCond condition, const ConstantRelocatable *label); // not testable.
void jmp(typename Traits::GPRRegister reg);
void jmp(GPRRegister reg);
void jmp(Label *label, bool near = kFarJump);
void jmp(const ConstantRelocatable *label); // not testable.
void mfence();
void lock();
void cmpxchg(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg, bool Locked);
void cmpxchg8b(const typename Traits::Address &address, bool Locked);
void xadd(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg, bool Locked);
void xchg(Type Ty, typename Traits::GPRRegister reg0,
typename Traits::GPRRegister reg1);
void xchg(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void cmpxchg(Type Ty, const Address &address, GPRRegister reg, bool Locked);
void cmpxchg8b(const Address &address, bool Locked);
void xadd(Type Ty, const Address &address, GPRRegister reg, bool Locked);
void xchg(Type Ty, GPRRegister reg0, GPRRegister reg1);
void xchg(Type Ty, const Address &address, GPRRegister reg);
/// \name Intel Architecture Code Analyzer markers.
/// @{
......@@ -882,9 +709,11 @@ protected:
inline void emitUint8(uint8_t value);
private:
ENABLE_MAKE_UNIQUE;
static constexpr Type RexTypeIrrelevant = IceType_i32;
static constexpr Type RexTypeForceRexW = IceType_i64;
static constexpr typename Traits::GPRRegister RexRegIrrelevant =
static constexpr GPRRegister RexRegIrrelevant =
Traits::GPRRegister::Encoded_Reg_eax;
inline void emitInt16(int16_t value);
......@@ -894,21 +723,19 @@ private:
inline void emitXmmRegisterOperand(RegType reg, RmType rm);
inline void emitOperandSizeOverride();
void emitOperand(int rm, const typename Traits::Operand &operand);
void emitOperand(int rm, const Operand &operand);
void emitImmediate(Type ty, const Immediate &imm);
void emitComplexI8(int rm, const typename Traits::Operand &operand,
void emitComplexI8(int rm, const Operand &operand,
const Immediate &immediate);
void emitComplex(Type Ty, int rm, const typename Traits::Operand &operand,
void emitComplex(Type Ty, int rm, const Operand &operand,
const Immediate &immediate);
void emitLabel(Label *label, intptr_t instruction_size);
void emitLabelLink(Label *label);
void emitNearLabelLink(Label *label);
void emitGenericShift(int rm, Type Ty, typename Traits::GPRRegister reg,
const Immediate &imm);
void emitGenericShift(int rm, Type Ty,
const typename Traits::Operand &operand,
typename Traits::GPRRegister shifter);
void emitGenericShift(int rm, Type Ty, GPRRegister reg, const Immediate &imm);
void emitGenericShift(int rm, Type Ty, const Operand &operand,
GPRRegister shifter);
using LabelVector = std::vector<Label *>;
// A vector of pool-allocated x86 labels for CFG nodes.
......@@ -930,24 +757,19 @@ private:
// of add(), Or(), adc(), sbb(), And(), sub(), Xor(), and cmp(). The Tag
// parameter is statically asserted to be less than 8.
template <uint32_t Tag>
void arith_int(Type Ty, typename Traits::GPRRegister reg,
const Immediate &imm);
void arith_int(Type Ty, GPRRegister reg, const Immediate &imm);
template <uint32_t Tag>
void arith_int(Type Ty, typename Traits::GPRRegister reg0,
typename Traits::GPRRegister reg1);
void arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1);
template <uint32_t Tag>
void arith_int(Type Ty, typename Traits::GPRRegister reg,
const typename Traits::Address &address);
void arith_int(Type Ty, GPRRegister reg, const Address &address);
template <uint32_t Tag>
void arith_int(Type Ty, const typename Traits::Address &address,
typename Traits::GPRRegister reg);
void arith_int(Type Ty, const Address &address, GPRRegister reg);
template <uint32_t Tag>
void arith_int(Type Ty, const typename Traits::Address &address,
const Immediate &imm);
void arith_int(Type Ty, const Address &address, const Immediate &imm);
// gprEncoding returns Reg encoding for operand emission. For x86-64 we mask
// out the 4th bit as it is encoded in the REX.[RXB] bits. No other bits are
......@@ -955,8 +777,7 @@ private:
template <typename RegType, typename T = Traits>
typename std::enable_if<T::Is64Bit, typename T::GPRRegister>::type
gprEncoding(const RegType Reg) {
return static_cast<typename Traits::GPRRegister>(static_cast<uint8_t>(Reg) &
~0x08);
return static_cast<GPRRegister>(static_cast<uint8_t>(Reg) & ~0x08);
}
template <typename RegType, typename T = Traits>
......@@ -968,18 +789,16 @@ private:
template <typename RegType>
bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) {
static constexpr bool IsGPR =
std::is_same<typename std::decay<RegType>::type,
typename Traits::ByteRegister>::value ||
std::is_same<typename std::decay<RegType>::type,
typename Traits::GPRRegister>::value;
std::is_same<typename std::decay<RegType>::type, ByteRegister>::value ||
std::is_same<typename std::decay<RegType>::type, GPRRegister>::value;
// At this point in the assembler, we have encoded regs, so it is not
// possible to distinguish between the "new" low byte registers introduced
// in x86-64 and the legacy [abcd]h registers. Because x86, we may still see
// ah (div) in the assembler, so we whitelist it here.
// in x86-64 and the legacy [abcd]h registers. Because x86, we may still
// see ah (div) in the assembler, so we whitelist it here.
//
// The "local" uint32_t Encoded_Reg_ah is needed because RegType is an enum
// that is not necessarily the same type of
// The "local" uint32_t Encoded_Reg_ah is needed because RegType is an
// enum that is not necessarily the same type of
// Traits::RegisterSet::Encoded_Reg_ah.
constexpr uint32_t Encoded_Reg_ah = Traits::RegisterSet::Encoded_Reg_ah;
return IsGPR && (Reg & 0x04) != 0 && (Reg & 0x08) == 0 &&
......@@ -988,9 +807,10 @@ private:
// assembleAndEmitRex is used for determining which (if any) rex prefix
// should be emitted for the current instruction. It allows different types
// for Reg and Rm because they could be of different types (e.g., in mov[sz]x
// instructions.) If Addr is not nullptr, then Rm is ignored, and Rex.B is
// determined by Addr instead. TyRm is still used to determine Addr's size.
// for Reg and Rm because they could be of different types (e.g., in
// mov[sz]x instructions.) If Addr is not nullptr, then Rm is ignored, and
// Rex.B is determined by Addr instead. TyRm is still used to determine
// Addr's size.
template <typename RegType, typename RmType, typename T = Traits>
typename std::enable_if<T::Is64Bit, void>::type
assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
......@@ -1021,8 +841,8 @@ private:
assembleAndEmitRex(const Type, const RegType, const Type, const RmType,
const typename T::Address * = nullptr) {}
// emitRexRB is used for emitting a Rex prefix instructions with two explicit
// register operands in its mod-rm byte.
// emitRexRB is used for emitting a Rex prefix instructions with two
// explicit register operands in its mod-rm byte.
template <typename RegType, typename RmType>
void emitRexRB(const Type Ty, const RegType Reg, const RmType Rm) {
assembleAndEmitRex(Ty, Reg, Ty, Rm);
......@@ -1044,53 +864,52 @@ private:
// emitRex is used for emitting a Rex prefix for an address and a GPR. The
// address may contain zero, one, or two registers.
template <typename RegType>
void emitRex(const Type Ty, const typename Traits::Address &Addr,
const RegType Reg) {
void emitRex(const Type Ty, const Address &Addr, const RegType Reg) {
assembleAndEmitRex(Ty, Reg, Ty, RexRegIrrelevant, &Addr);
}
template <typename RegType>
void emitRex(const Type AddrTy, const typename Traits::Address &Addr,
const Type TyReg, const RegType Reg) {
void emitRex(const Type AddrTy, const Address &Addr, const Type TyReg,
const RegType Reg) {
assembleAndEmitRex(TyReg, Reg, AddrTy, RexRegIrrelevant, &Addr);
}
};
template <class Machine>
inline void AssemblerX86Base<Machine>::emitUint8(uint8_t value) {
template <typename TraitsType>
inline void AssemblerX86Base<TraitsType>::emitUint8(uint8_t value) {
Buffer.emit<uint8_t>(value);
}
template <class Machine>
inline void AssemblerX86Base<Machine>::emitInt16(int16_t value) {
template <typename TraitsType>
inline void AssemblerX86Base<TraitsType>::emitInt16(int16_t value) {
Buffer.emit<int16_t>(value);
}
template <class Machine>
inline void AssemblerX86Base<Machine>::emitInt32(int32_t value) {
template <typename TraitsType>
inline void AssemblerX86Base<TraitsType>::emitInt32(int32_t value) {
Buffer.emit<int32_t>(value);
}
template <class Machine>
inline void AssemblerX86Base<Machine>::emitRegisterOperand(int reg, int rm) {
template <typename TraitsType>
inline void AssemblerX86Base<TraitsType>::emitRegisterOperand(int reg, int rm) {
assert(reg >= 0 && reg < 8);
assert(rm >= 0 && rm < 8);
Buffer.emit<uint8_t>(0xC0 + (reg << 3) + rm);
}
template <class Machine>
template <typename TraitsType>
template <typename RegType, typename RmType>
inline void AssemblerX86Base<Machine>::emitXmmRegisterOperand(RegType reg,
RmType rm) {
inline void AssemblerX86Base<TraitsType>::emitXmmRegisterOperand(RegType reg,
RmType rm) {
emitRegisterOperand(gprEncoding(reg), gprEncoding(rm));
}
template <class Machine>
inline void AssemblerX86Base<Machine>::emitOperandSizeOverride() {
template <typename TraitsType>
inline void AssemblerX86Base<TraitsType>::emitOperandSizeOverride() {
emitUint8(0x66);
}
} // end of namespace X86Internal
} // end of namespace X86NAMESPACE
} // end of namespace Ice
......
src/IceAssemblerX86BaseImpl.h
This source diff could not be displayed because it is too large. You can view the blob instead.
src/IceInstARM32.cpp
......@@ -24,6 +24,7 @@
#include "IceTargetLoweringARM32.h"
namespace Ice {
namespace ARM32 {
namespace {
......@@ -2151,4 +2152,5 @@ template class InstARM32CmpLike<InstARM32::Cmn>;
template class InstARM32CmpLike<InstARM32::Cmp>;
template class InstARM32CmpLike<InstARM32::Tst>;
} // end of namespace ARM32
} // end of namespace Ice
src/IceInstARM32.h
......@@ -25,6 +25,7 @@
#include "IceOperand.h"
namespace Ice {
namespace ARM32 {
class TargetARM32;
......@@ -1376,6 +1377,7 @@ template <> void InstARM32Ldr::emit(const Cfg *Func) const;
template <> void InstARM32Movw::emit(const Cfg *Func) const;
template <> void InstARM32Movt::emit(const Cfg *Func) const;
} // end of namespace ARM32
} // end of namespace Ice
#endif // SUBZERO_SRC_ICEINSTARM32_H
src/IceInstMIPS32.cpp
......@@ -23,6 +23,7 @@
#include <limits>
namespace Ice {
namespace MIPS32 {
bool OperandMIPS32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) {
(void)SignExt;
......@@ -274,4 +275,5 @@ void InstMIPS32Mov::emitSingleDestSingleSource(const Cfg *Func) const {
getSrc(0)->emit(Func);
}
} // end of namespace MIPS32
} // end of namespace Ice
src/IceInstMIPS32.h
......@@ -25,6 +25,7 @@
#include "IceOperand.h"
namespace Ice {
namespace MIPS32 {
class TargetMIPS32;
......@@ -395,6 +396,7 @@ private:
Variable *DestHi = nullptr;
};
} // end of namespace MIPS32
} // end of namespace Ice
#endif // SUBZERO_SRC_ICEINSTMIPS32_H
src/IceInstX8632.cpp
......@@ -28,10 +28,10 @@
namespace Ice {
namespace X86Internal {
namespace X8632 {
const MachineTraits<TargetX8632>::InstBrAttributesType
MachineTraits<TargetX8632>::InstBrAttributes[] = {
const TargetX8632Traits::InstBrAttributesType
TargetX8632Traits::InstBrAttributes[] = {
#define X(val, encode, opp, dump, emit) \
{ X8632::Traits::Cond::opp, dump, emit } \
,
......@@ -39,8 +39,8 @@ const MachineTraits<TargetX8632>::InstBrAttributesType
#undef X
};
const MachineTraits<TargetX8632>::InstCmppsAttributesType
MachineTraits<TargetX8632>::InstCmppsAttributes[] = {
const TargetX8632Traits::InstCmppsAttributesType
TargetX8632Traits::InstCmppsAttributes[] = {
#define X(val, emit) \
{ emit } \
,
......@@ -48,8 +48,8 @@ const MachineTraits<TargetX8632>::InstCmppsAttributesType
#undef X
};
const MachineTraits<TargetX8632>::TypeAttributesType
MachineTraits<TargetX8632>::TypeAttributes[] = {
const TargetX8632Traits::TypeAttributesType
TargetX8632Traits::TypeAttributes[] = {
#define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld) \
{ cvt, sdss, pdps, spsd, pack, width, fld } \
,
......@@ -57,27 +57,28 @@ const MachineTraits<TargetX8632>::TypeAttributesType
#undef X
};
const char *MachineTraits<TargetX8632>::InstSegmentRegNames[] = {
const char *TargetX8632Traits::InstSegmentRegNames[] = {
#define X(val, name, prefix) name,
SEG_REGX8632_TABLE
#undef X
};
uint8_t MachineTraits<TargetX8632>::InstSegmentPrefixes[] = {
uint8_t TargetX8632Traits::InstSegmentPrefixes[] = {
#define X(val, name, prefix) prefix,
SEG_REGX8632_TABLE
#undef X
};
void MachineTraits<TargetX8632>::X86Operand::dump(const Cfg *,
Ostream &Str) const {
void TargetX8632Traits::X86Operand::dump(const Cfg *, Ostream &Str) const {
if (BuildDefs::dump())
Str << "<OperandX8632>";
}
MachineTraits<TargetX8632>::X86OperandMem::X86OperandMem(
Cfg *Func, Type Ty, Variable *Base, Constant *Offset, Variable *Index,
uint16_t Shift, SegmentRegisters SegmentReg)
TargetX8632Traits::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
Variable *Base,
Constant *Offset,
Variable *Index, uint16_t Shift,
SegmentRegisters SegmentReg)
: X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
Shift(Shift), SegmentReg(SegmentReg), Randomized(false) {
assert(Shift <= 3);
......@@ -99,8 +100,9 @@ MachineTraits<TargetX8632>::X86OperandMem::X86OperandMem(
}
namespace {
static int32_t GetRematerializableOffset(Variable *Var,
const Ice::TargetX8632 *Target) {
static int32_t
GetRematerializableOffset(Variable *Var,
const Ice::X8632::TargetX8632 *Target) {
int32_t Disp = Var->getStackOffset();
SizeT RegNum = static_cast<SizeT>(Var->getRegNum());
if (RegNum == Target->getFrameReg()) {
......@@ -112,10 +114,11 @@ static int32_t GetRematerializableOffset(Variable *Var,
}
} // end of anonymous namespace
void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const {
void TargetX8632Traits::X86OperandMem::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
const auto *Target = static_cast<const Ice::TargetX8632 *>(Func->getTarget());
const auto *Target =
static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
// If the base is rematerializable, we need to replace it with the correct
// physical register (esp or ebp), and update the Offset.
int32_t Disp = 0;
......@@ -166,8 +169,8 @@ void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const {
}
}
void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
Ostream &Str) const {
void TargetX8632Traits::X86OperandMem::dump(const Cfg *Func,
Ostream &Str) const {
if (!BuildDefs::dump())
return;
if (SegmentReg != DefaultSegment) {
......@@ -177,7 +180,8 @@ void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
bool Dumped = false;
Str << "[";
int32_t Disp = 0;
const auto *Target = static_cast<const Ice::TargetX8632 *>(Func->getTarget());
const auto *Target =
static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
if (getBase() && getBase()->isRematerializable()) {
Disp += GetRematerializableOffset(getBase(), Target);
}
......@@ -230,20 +234,20 @@ void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
Str << "]";
}
void MachineTraits<TargetX8632>::X86OperandMem::emitSegmentOverride(
MachineTraits<TargetX8632>::Assembler *Asm) const {
void TargetX8632Traits::X86OperandMem::emitSegmentOverride(
TargetX8632Traits::Assembler *Asm) const {
if (SegmentReg != DefaultSegment) {
assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
Asm->emitSegmentOverride(X8632::Traits::InstSegmentPrefixes[SegmentReg]);
}
}
MachineTraits<TargetX8632>::Address
MachineTraits<TargetX8632>::X86OperandMem::toAsmAddress(
MachineTraits<TargetX8632>::Assembler *Asm,
TargetX8632Traits::Address TargetX8632Traits::X86OperandMem::toAsmAddress(
TargetX8632Traits::Assembler *Asm,
const Ice::TargetLowering *TargetLowering) const {
int32_t Disp = 0;
const auto *Target = static_cast<const Ice::TargetX8632 *>(TargetLowering);
const auto *Target =
static_cast<const ::Ice::X8632::TargetX8632 *>(TargetLowering);
if (getBase() && getBase()->isRematerializable()) {
Disp += GetRematerializableOffset(getBase(), Target);
}
......@@ -284,8 +288,8 @@ MachineTraits<TargetX8632>::X86OperandMem::toAsmAddress(
}
}
MachineTraits<TargetX8632>::Address
MachineTraits<TargetX8632>::VariableSplit::toAsmAddress(const Cfg *Func) const {
TargetX8632Traits::Address
TargetX8632Traits::VariableSplit::toAsmAddress(const Cfg *Func) const {
assert(!Var->hasReg());
const ::Ice::TargetLowering *Target = Func->getTarget();
int32_t Offset = Var->getStackOffset() + getOffset();
......@@ -293,7 +297,7 @@ MachineTraits<TargetX8632>::VariableSplit::toAsmAddress(const Cfg *Func) const {
Offset, AssemblerFixup::NoFixup);
}
void MachineTraits<TargetX8632>::VariableSplit::emit(const Cfg *Func) const {
void TargetX8632Traits::VariableSplit::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
Ostream &Str = Func->getContext()->getStrEmit();
......@@ -307,8 +311,8 @@ void MachineTraits<TargetX8632>::VariableSplit::emit(const Cfg *Func) const {
Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
}
void MachineTraits<TargetX8632>::VariableSplit::dump(const Cfg *Func,
Ostream &Str) const {
void TargetX8632Traits::VariableSplit::dump(const Cfg *Func,
Ostream &Str) const {
if (!BuildDefs::dump())
return;
switch (Part) {
......@@ -327,7 +331,7 @@ void MachineTraits<TargetX8632>::VariableSplit::dump(const Cfg *Func,
Str << ")";
}
} // namespace X86Internal
} // namespace X8632
} // end of namespace Ice
X86INSTS_DEFINE_STATIC_DATA(TargetX8632)
X86INSTS_DEFINE_STATIC_DATA(X8632, X8632::Traits)
src/IceInstX8632.h
......@@ -28,7 +28,9 @@
#include "IceDefs.h"
#include "IceInst.h"
#define X86NAMESPACE X8632
#include "IceInstX86Base.h"
#undef X86NAMESPACE
#include "IceOperand.h"
#include "IceTargetLoweringX8632Traits.h"
......
src/IceInstX8664.cpp
......@@ -29,10 +29,10 @@
namespace Ice {
namespace X86Internal {
namespace X8664 {
const MachineTraits<TargetX8664>::InstBrAttributesType
MachineTraits<TargetX8664>::InstBrAttributes[] = {
const TargetX8664Traits::InstBrAttributesType
TargetX8664Traits::InstBrAttributes[] = {
#define X(val, encode, opp, dump, emit) \
{ X8664::Traits::Cond::opp, dump, emit } \
,
......@@ -40,8 +40,8 @@ const MachineTraits<TargetX8664>::InstBrAttributesType
#undef X
};
const MachineTraits<TargetX8664>::InstCmppsAttributesType
MachineTraits<TargetX8664>::InstCmppsAttributes[] = {
const TargetX8664Traits::InstCmppsAttributesType
TargetX8664Traits::InstCmppsAttributes[] = {
#define X(val, emit) \
{ emit } \
,
......@@ -49,8 +49,8 @@ const MachineTraits<TargetX8664>::InstCmppsAttributesType
#undef X
};
const MachineTraits<TargetX8664>::TypeAttributesType
MachineTraits<TargetX8664>::TypeAttributes[] = {
const TargetX8664Traits::TypeAttributesType
TargetX8664Traits::TypeAttributes[] = {
#define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld) \
{ cvt, sdss, pdps, spsd, pack, width, fld } \
,
......@@ -58,17 +58,15 @@ const MachineTraits<TargetX8664>::TypeAttributesType
#undef X
};
void MachineTraits<TargetX8664>::X86Operand::dump(const Cfg *,
Ostream &Str) const {
void TargetX8664Traits::X86Operand::dump(const Cfg *, Ostream &Str) const {
if (BuildDefs::dump())
Str << "<OperandX8664>";
}
MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
Variable *Base,
Constant *Offset,
Variable *Index,
uint16_t Shift)
TargetX8664Traits::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
Variable *Base,
Constant *Offset,
Variable *Index, uint16_t Shift)
: X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
Shift(Shift) {
assert(Shift <= 3);
......@@ -90,8 +88,9 @@ MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
}
namespace {
static int32_t getRematerializableOffset(Variable *Var,
const Ice::TargetX8664 *Target) {
static int32_t
getRematerializableOffset(Variable *Var,
const ::Ice::X8664::TargetX8664 *Target) {
int32_t Disp = Var->getStackOffset();
SizeT RegNum = static_cast<SizeT>(Var->getRegNum());
if (RegNum == Target->getFrameReg()) {
......@@ -103,10 +102,11 @@ static int32_t getRematerializableOffset(Variable *Var,
}
} // end of anonymous namespace
void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
void TargetX8664Traits::X86OperandMem::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
const auto *Target = static_cast<const Ice::TargetX8664 *>(Func->getTarget());
const auto *Target =
static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
// If the base is rematerializable, we need to replace it with the correct
// physical register (stack or base pointer), and update the Offset.
int32_t Disp = 0;
......@@ -164,14 +164,15 @@ void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
}
}
void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
Ostream &Str) const {
void TargetX8664Traits::X86OperandMem::dump(const Cfg *Func,
Ostream &Str) const {
if (!BuildDefs::dump())
return;
bool Dumped = false;
Str << "[";
int32_t Disp = 0;
const auto *Target = static_cast<const Ice::TargetX8664 *>(Func->getTarget());
const auto *Target =
static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
if (getBase() && getBase()->isRematerializable()) {
Disp += getRematerializableOffset(getBase(), Target);
}
......@@ -223,11 +224,11 @@ void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
Str << "]";
}
MachineTraits<TargetX8664>::Address
MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
MachineTraits<TargetX8664>::Assembler *Asm,
TargetX8664Traits::Address TargetX8664Traits::X86OperandMem::toAsmAddress(
TargetX8664Traits::Assembler *Asm,
const Ice::TargetLowering *TargetLowering) const {
const auto *Target = static_cast<const Ice::TargetX8664 *>(TargetLowering);
const auto *Target =
static_cast<const ::Ice::X8664::TargetX8664 *>(TargetLowering);
int32_t Disp = 0;
if (getBase() && getBase()->isRematerializable()) {
Disp += getRematerializableOffset(getBase(), Target);
......@@ -266,8 +267,8 @@ MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
}
}
MachineTraits<TargetX8664>::Address
MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
TargetX8664Traits::Address
TargetX8664Traits::VariableSplit::toAsmAddress(const Cfg *Func) const {
assert(!Var->hasReg());
const ::Ice::TargetLowering *Target = Func->getTarget();
int32_t Offset = Var->getStackOffset() + getOffset();
......@@ -275,7 +276,7 @@ MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
Offset, AssemblerFixup::NoFixup);
}
void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
void TargetX8664Traits::VariableSplit::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
Ostream &Str = Func->getContext()->getStrEmit();
......@@ -289,8 +290,8 @@ void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
}
void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
Ostream &Str) const {
void TargetX8664Traits::VariableSplit::dump(const Cfg *Func,
Ostream &Str) const {
if (!BuildDefs::dump())
return;
switch (Part) {
......@@ -309,7 +310,7 @@ void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
Str << ")";
}
} // namespace X86Internal
} // namespace X8664
} // end of namespace Ice
X86INSTS_DEFINE_STATIC_DATA(TargetX8664)
X86INSTS_DEFINE_STATIC_DATA(X8664, X8664::Traits)
src/IceInstX8664.h
......@@ -26,7 +26,9 @@
#include "IceDefs.h"
#include "IceInst.h"
#define X86NAMESPACE X8664
#include "IceInstX86Base.h"
#undef X86NAMESPACE
#include "IceOperand.h"
#include "IceTargetLoweringX8664Traits.h"
......
src/IceInstX86Base.h
This source diff could not be displayed because it is too large. You can view the blob instead.
src/IceInstX86BaseImpl.h
This source diff could not be displayed because it is too large. You can view the blob instead.
src/IceRegistersARM32.h
......@@ -21,6 +21,7 @@
#include "IceTypes.h"
namespace Ice {
namespace ARM32 {
class RegARM32 {
public:
......@@ -136,6 +137,7 @@ public:
// Extend enum RegClass with ARM32-specific register classes (if any).
enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
} // end of namespace ARM32
} // end of namespace Ice
#endif // SUBZERO_SRC_ICEREGISTERSARM32_H
src/IceRegistersMIPS32.h
......@@ -21,7 +21,7 @@
#include "IceTypes.h"
namespace Ice {
namespace MIPS32 {
namespace RegMIPS32 {
/// An enum of every register. The enum value may not match the encoding
......@@ -63,6 +63,7 @@ static inline GPRRegister getEncodedGPR(int32_t RegNum) {
// Extend enum RegClass with MIPS32-specific register classes (if any).
enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target };
} // end of namespace MIPS32
} // end of namespace Ice
#endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H
src/IceTargetLoweringARM32.cpp
......@@ -37,23 +37,24 @@
namespace ARM32 {
std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
return ::Ice::TargetARM32::create(Func);
return ::Ice::ARM32::TargetARM32::create(Func);
}
std::unique_ptr<::Ice::TargetDataLowering>
createTargetDataLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetDataARM32::create(Ctx);
return ::Ice::ARM32::TargetDataARM32::create(Ctx);
}
std::unique_ptr<::Ice::TargetHeaderLowering>
createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetHeaderARM32::create(Ctx);
return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
}
void staticInit() { ::Ice::TargetARM32::staticInit(); }
void staticInit() { ::Ice::ARM32::TargetARM32::staticInit(); }
} // end of namespace ARM32
namespace Ice {
namespace ARM32 {
namespace {
......@@ -6447,4 +6448,5 @@ llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
llvm::SmallBitVector TargetARM32::ScratchRegs;
} // end of namespace ARM32
} // end of namespace Ice
src/IceTargetLoweringARM32.h
......@@ -25,6 +25,7 @@
#include "llvm/ADT/SmallBitVector.h"
namespace Ice {
namespace ARM32 {
// Class encapsulating ARM cpu features / instruction set.
class TargetARM32Features {
......@@ -1206,6 +1207,7 @@ private:
TargetARM32Features CPUFeatures;
};
} // end of namespace ARM32
} // end of namespace Ice
#endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H
src/IceTargetLoweringMIPS32.cpp
......@@ -32,23 +32,24 @@
namespace MIPS32 {
std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
return ::Ice::TargetMIPS32::create(Func);
return ::Ice::MIPS32::TargetMIPS32::create(Func);
}
std::unique_ptr<::Ice::TargetDataLowering>
createTargetDataLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetDataMIPS32::create(Ctx);
return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx);
}
std::unique_ptr<::Ice::TargetHeaderLowering>
createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetHeaderMIPS32::create(Ctx);
return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx);
}
void staticInit() { ::Ice::TargetMIPS32::staticInit(); }
void staticInit() { ::Ice::MIPS32::TargetMIPS32::staticInit(); }
} // end of namespace MIPS32
namespace Ice {
namespace MIPS32 {
using llvm::isInt;
......@@ -1100,4 +1101,5 @@ llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
llvm::SmallBitVector TargetMIPS32::ScratchRegs;
} // end of namespace MIPS32
} // end of namespace Ice
src/IceTargetLoweringMIPS32.h
......@@ -23,6 +23,7 @@
#include "IceTargetLowering.h"
namespace Ice {
namespace MIPS32 {
class TargetMIPS32 : public TargetLowering {
TargetMIPS32() = delete;
......@@ -310,6 +311,7 @@ private:
~TargetHeaderMIPS32() = default;
};
} // end of namespace MIPS32
} // end of namespace Ice
#endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
src/IceTargetLoweringX8632.cpp
......@@ -16,27 +16,27 @@
#include "IceTargetLoweringX8632.h"
#include "IceTargetLoweringX8632Traits.h"
#include "IceTargetLoweringX86Base.h"
namespace X8632 {
std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
return ::Ice::TargetX8632::create(Func);
return ::Ice::X8632::TargetX8632::create(Func);
}
std::unique_ptr<::Ice::TargetDataLowering>
createTargetDataLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetDataX8632::create(Ctx);
return ::Ice::X8632::TargetDataX8632::create(Ctx);
}
std::unique_ptr<::Ice::TargetHeaderLowering>
createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetHeaderX8632::create(Ctx);
return ::Ice::X8632::TargetHeaderX8632::create(Ctx);
}
void staticInit() { ::Ice::TargetX8632::staticInit(); }
void staticInit() { ::Ice::X8632::TargetX8632::staticInit(); }
} // end of namespace X8632
namespace Ice {
namespace X8632 {
//------------------------------------------------------------------------------
// ______ ______ ______ __ ______ ______
......@@ -46,51 +46,46 @@ namespace Ice {
// \/_/ \/_/ /_/ \/_/\/_/ \/_/ \/_/ \/_____/
//
//------------------------------------------------------------------------------
namespace X86Internal {
const MachineTraits<TargetX8632>::TableFcmpType
MachineTraits<TargetX8632>::TableFcmp[] = {
const TargetX8632Traits::TableFcmpType TargetX8632Traits::TableFcmp[] = {
#define X(val, dflt, swapS, C1, C2, swapV, pred) \
{ \
dflt, swapS, X8632::Traits::Cond::C1, X8632::Traits::Cond::C2, swapV, \
X8632::Traits::Cond::pred \
} \
,
FCMPX8632_TABLE
FCMPX8632_TABLE
#undef X
};
const size_t MachineTraits<TargetX8632>::TableFcmpSize =
llvm::array_lengthof(TableFcmp);
const size_t TargetX8632Traits::TableFcmpSize = llvm::array_lengthof(TableFcmp);
const MachineTraits<TargetX8632>::TableIcmp32Type
MachineTraits<TargetX8632>::TableIcmp32[] = {
const TargetX8632Traits::TableIcmp32Type TargetX8632Traits::TableIcmp32[] = {
#define X(val, C_32, C1_64, C2_64, C3_64) \
{ X8632::Traits::Cond::C_32 } \
,
ICMPX8632_TABLE
ICMPX8632_TABLE
#undef X
};
const size_t MachineTraits<TargetX8632>::TableIcmp32Size =
const size_t TargetX8632Traits::TableIcmp32Size =
llvm::array_lengthof(TableIcmp32);
const MachineTraits<TargetX8632>::TableIcmp64Type
MachineTraits<TargetX8632>::TableIcmp64[] = {
const TargetX8632Traits::TableIcmp64Type TargetX8632Traits::TableIcmp64[] = {
#define X(val, C_32, C1_64, C2_64, C3_64) \
{ \
X8632::Traits::Cond::C1_64, X8632::Traits::Cond::C2_64, \
X8632::Traits::Cond::C3_64 \
} \
,
ICMPX8632_TABLE
ICMPX8632_TABLE
#undef X
};
const size_t MachineTraits<TargetX8632>::TableIcmp64Size =
const size_t TargetX8632Traits::TableIcmp64Size =
llvm::array_lengthof(TableIcmp64);
const MachineTraits<TargetX8632>::TableTypeX8632AttributesType
MachineTraits<TargetX8632>::TableTypeX8632Attributes[] = {
const TargetX8632Traits::TableTypeX8632AttributesType
TargetX8632Traits::TableTypeX8632Attributes[] = {
#define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld) \
{ IceType_##elementty } \
,
......@@ -98,26 +93,24 @@ const MachineTraits<TargetX8632>::TableTypeX8632AttributesType
#undef X
};
const size_t MachineTraits<TargetX8632>::TableTypeX8632AttributesSize =
const size_t TargetX8632Traits::TableTypeX8632AttributesSize =
llvm::array_lengthof(TableTypeX8632Attributes);
const uint32_t MachineTraits<TargetX8632>::X86_STACK_ALIGNMENT_BYTES = 16;
const char *MachineTraits<TargetX8632>::TargetName = "X8632";
const uint32_t TargetX8632Traits::X86_STACK_ALIGNMENT_BYTES = 16;
const char *TargetX8632Traits::TargetName = "X8632";
template <>
std::array<llvm::SmallBitVector, RCX86_NUM>
TargetX86Base<TargetX8632>::TypeToRegisterSet = {{}};
TargetX86Base<X8632::Traits>::TypeToRegisterSet = {{}};
template <>
std::array<llvm::SmallBitVector,
TargetX86Base<TargetX8632>::Traits::RegisterSet::Reg_NUM>
TargetX86Base<TargetX8632>::RegisterAliases = {{}};
TargetX86Base<X8632::Traits>::Traits::RegisterSet::Reg_NUM>
TargetX86Base<X8632::Traits>::RegisterAliases = {{}};
template <>
llvm::SmallBitVector
TargetX86Base<TargetX8632>::ScratchRegs = llvm::SmallBitVector();
} // end of namespace X86Internal
TargetX86Base<X8632::Traits>::ScratchRegs = llvm::SmallBitVector();
//------------------------------------------------------------------------------
// __ ______ __ __ ______ ______ __ __ __ ______
......@@ -1018,4 +1011,5 @@ ICETYPE_TABLE
} // end of namespace dummy3
} // end of anonymous namespace
} // end of namespace X8632
} // end of namespace Ice
src/IceTargetLoweringX8632.h
......@@ -18,16 +18,18 @@
#include "IceAssemblerX8632.h"
#include "IceDefs.h"
#include "IceInstX8632.h"
#include "IceRegistersX8632.h"
#include "IceTargetLowering.h"
#include "IceTargetLoweringX8632Traits.h"
#include "IceInstX8632.h"
#define X86NAMESPACE X8632
#include "IceTargetLoweringX86Base.h"
#undef X86NAMESPACE
#include "IceTargetLoweringX8632Traits.h"
namespace Ice {
namespace X8632 {
class TargetX8632 final
: public ::Ice::X86Internal::TargetX86Base<TargetX8632> {
class TargetX8632 final : public ::Ice::X8632::TargetX86Base<X8632::Traits> {
TargetX8632() = delete;
TargetX8632(const TargetX8632 &) = delete;
TargetX8632 &operator=(const TargetX8632 &) = delete;
......@@ -55,7 +57,7 @@ protected:
private:
ENABLE_MAKE_UNIQUE;
friend class ::Ice::X86Internal::TargetX86Base<TargetX8632>;
friend class X8632::TargetX86Base<X8632::Traits>;
Operand *createNaClReadTPSrcOperand() {
Constant *Zero = Ctx->getConstantZero(IceType_i32);
......@@ -108,6 +110,7 @@ private:
~TargetHeaderX8632() = default;
};
} // end of namespace X8632
} // end of namespace Ice
#endif // SUBZERO_SRC_ICETARGETLOWERINGX8632_H
src/IceTargetLoweringX8632Traits.h
......@@ -30,19 +30,16 @@
namespace Ice {
class TargetX8632;
namespace X8632 {
class AssemblerX8632;
} // end of namespace X8632
namespace X86Internal {
using namespace ::Ice::X86;
template <class Machine> struct Insts;
template <class Machine> struct MachineTraits;
template <class Machine> class TargetX86Base;
template <class Machine> class AssemblerX86Base;
template <> struct MachineTraits<TargetX8632> {
class TargetX8632;
struct TargetX8632Traits {
//----------------------------------------------------------------------------
// ______ ______ __ __
// /\ __ \/\ ___\/\ "-./ \
......@@ -51,6 +48,9 @@ template <> struct MachineTraits<TargetX8632> {
// \/_/\/_/\/_____/\/_/ \/_/
//
//----------------------------------------------------------------------------
static constexpr ::Ice::Assembler::AssemblerKind AsmKind =
::Ice::Assembler::Asm_X8632;
static constexpr bool Is64Bit = false;
static constexpr bool HasPopa = true;
static constexpr bool HasPusha = true;
......@@ -171,7 +171,7 @@ template <> struct MachineTraits<TargetX8632> {
((encoding_[0] & 0x07) == reg); // Register codes match.
}
template <class> friend class AssemblerX86Base;
friend class AssemblerX86Base<TargetX8632Traits>;
};
class Address : public Operand {
......@@ -752,10 +752,12 @@ public:
// \/_/\/_/ \/_/\/_____/ \/_/
//
//----------------------------------------------------------------------------
using Insts = ::Ice::X86Internal::Insts<TargetX8632>;
using Traits = TargetX8632Traits;
using Insts = ::Ice::X8632::Insts<Traits>;
using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8632>;
using Assembler = X8632::AssemblerX8632;
using TargetLowering = ::Ice::X8632::TargetX86Base<Traits>;
using ConcreteTarget = ::Ice::X8632::TargetX8632;
using Assembler = ::Ice::X8632::AssemblerX86Base<Traits>;
/// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem
/// and VariableSplit.
......@@ -932,10 +934,7 @@ public:
static uint8_t InstSegmentPrefixes[];
};
} // end of namespace X86Internal
namespace X8632 {
using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>;
using Traits = ::Ice::X8632::TargetX8632Traits;
} // end of namespace X8632
} // end of namespace Ice
......
src/IceTargetLoweringX8664.cpp
......@@ -16,27 +16,27 @@
#include "IceTargetLoweringX8664.h"
#include "IceTargetLoweringX8664Traits.h"
#include "IceTargetLoweringX86Base.h"
namespace X8664 {
std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
return ::Ice::TargetX8664::create(Func);
return ::Ice::X8664::TargetX8664::create(Func);
}
std::unique_ptr<::Ice::TargetDataLowering>
createTargetDataLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetDataX8664::create(Ctx);
return ::Ice::X8664::TargetDataX8664::create(Ctx);
}
std::unique_ptr<::Ice::TargetHeaderLowering>
createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
return ::Ice::TargetHeaderX8664::create(Ctx);
return ::Ice::X8664::TargetHeaderX8664::create(Ctx);
}
void staticInit() { ::Ice::TargetX8664::staticInit(); }
void staticInit() { ::Ice::X8664::TargetX8664::staticInit(); }
} // end of namespace X8664
namespace Ice {
namespace X8664 {
//------------------------------------------------------------------------------
// ______ ______ ______ __ ______ ______
......@@ -46,51 +46,46 @@ namespace Ice {
// \/_/ \/_/ /_/ \/_/\/_/ \/_/ \/_/ \/_____/
//
//------------------------------------------------------------------------------
namespace X86Internal {
const MachineTraits<TargetX8664>::TableFcmpType
MachineTraits<TargetX8664>::TableFcmp[] = {
const TargetX8664Traits::TableFcmpType TargetX8664Traits::TableFcmp[] = {
#define X(val, dflt, swapS, C1, C2, swapV, pred) \
{ \
dflt, swapS, X8664::Traits::Cond::C1, X8664::Traits::Cond::C2, swapV, \
X8664::Traits::Cond::pred \
} \
,
FCMPX8664_TABLE
FCMPX8664_TABLE
#undef X
};
const size_t MachineTraits<TargetX8664>::TableFcmpSize =
llvm::array_lengthof(TableFcmp);
const size_t TargetX8664Traits::TableFcmpSize = llvm::array_lengthof(TableFcmp);
const MachineTraits<TargetX8664>::TableIcmp32Type
MachineTraits<TargetX8664>::TableIcmp32[] = {
const TargetX8664Traits::TableIcmp32Type TargetX8664Traits::TableIcmp32[] = {
#define X(val, C_32, C1_64, C2_64, C3_64) \
{ X8664::Traits::Cond::C_32 } \
,
ICMPX8664_TABLE
ICMPX8664_TABLE
#undef X
};
const size_t MachineTraits<TargetX8664>::TableIcmp32Size =
const size_t TargetX8664Traits::TableIcmp32Size =
llvm::array_lengthof(TableIcmp32);
const MachineTraits<TargetX8664>::TableIcmp64Type
MachineTraits<TargetX8664>::TableIcmp64[] = {
const TargetX8664Traits::TableIcmp64Type TargetX8664Traits::TableIcmp64[] = {
#define X(val, C_32, C1_64, C2_64, C3_64) \
{ \
X8664::Traits::Cond::C1_64, X8664::Traits::Cond::C2_64, \
X8664::Traits::Cond::C3_64 \
} \
,
ICMPX8664_TABLE
ICMPX8664_TABLE
#undef X
};
const size_t MachineTraits<TargetX8664>::TableIcmp64Size =
const size_t TargetX8664Traits::TableIcmp64Size =
llvm::array_lengthof(TableIcmp64);
const MachineTraits<TargetX8664>::TableTypeX8664AttributesType
MachineTraits<TargetX8664>::TableTypeX8664Attributes[] = {
const TargetX8664Traits::TableTypeX8664AttributesType
TargetX8664Traits::TableTypeX8664Attributes[] = {
#define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld) \
{ IceType_##elementty } \
,
......@@ -98,26 +93,24 @@ const MachineTraits<TargetX8664>::TableTypeX8664AttributesType
#undef X
};
const size_t MachineTraits<TargetX8664>::TableTypeX8664AttributesSize =
const size_t TargetX8664Traits::TableTypeX8664AttributesSize =
llvm::array_lengthof(TableTypeX8664Attributes);
const uint32_t MachineTraits<TargetX8664>::X86_STACK_ALIGNMENT_BYTES = 16;
const char *MachineTraits<TargetX8664>::TargetName = "X8664";
const uint32_t TargetX8664Traits::X86_STACK_ALIGNMENT_BYTES = 16;
const char *TargetX8664Traits::TargetName = "X8664";
template <>
std::array<llvm::SmallBitVector, RCX86_NUM>
TargetX86Base<TargetX8664>::TypeToRegisterSet = {{}};
TargetX86Base<X8664::Traits>::TypeToRegisterSet = {{}};
template <>
std::array<llvm::SmallBitVector,
TargetX86Base<TargetX8664>::Traits::RegisterSet::Reg_NUM>
TargetX86Base<TargetX8664>::RegisterAliases = {{}};
TargetX86Base<X8664::Traits>::Traits::RegisterSet::Reg_NUM>
TargetX86Base<X8664::Traits>::RegisterAliases = {{}};
template <>
llvm::SmallBitVector
TargetX86Base<TargetX8664>::ScratchRegs = llvm::SmallBitVector();
} // end of namespace X86Internal
TargetX86Base<X8664::Traits>::ScratchRegs = llvm::SmallBitVector();
//------------------------------------------------------------------------------
// __ ______ __ __ ______ ______ __ __ __ ______
......@@ -1050,4 +1043,5 @@ ICETYPE_TABLE
} // end of namespace dummy3
} // end of anonymous namespace
} // end of namespace X8664
} // end of namespace Ice
src/IceTargetLoweringX8664.h
......@@ -21,13 +21,15 @@
#include "IceGlobalContext.h"
#include "IceInstX8664.h"
#include "IceTargetLowering.h"
#include "IceTargetLoweringX8664Traits.h"
#define X86NAMESPACE X8664
#include "IceTargetLoweringX86Base.h"
#undef X86NAMESPACE
#include "IceTargetLoweringX8664Traits.h"
namespace Ice {
namespace X8664 {
class TargetX8664 final
: public ::Ice::X86Internal::TargetX86Base<TargetX8664> {
class TargetX8664 final : public X8664::TargetX86Base<X8664::Traits> {
TargetX8664() = delete;
TargetX8664(const TargetX8664 &) = delete;
TargetX8664 &operator=(const TargetX8664 &) = delete;
......@@ -55,10 +57,10 @@ protected:
private:
ENABLE_MAKE_UNIQUE;
friend class ::Ice::X86Internal::TargetX86Base<TargetX8664>;
friend class X8664::TargetX86Base<X8664::Traits>;
explicit TargetX8664(Cfg *Func)
: ::Ice::X86Internal::TargetX86Base<TargetX8664>(Func) {}
: ::Ice::X8664::TargetX86Base<X8664::Traits>(Func) {}
Operand *createNaClReadTPSrcOperand() {
Variable *TDB = makeReg(IceType_i32);
......@@ -111,6 +113,7 @@ private:
explicit TargetHeaderX8664(GlobalContext *Ctx) : TargetHeaderLowering(Ctx) {}
};
} // end of namespace X8664
} // end of namespace Ice
#endif // SUBZERO_SRC_ICETARGETLOWERINGX8664_H
src/IceTargetLoweringX8664Traits.h
......@@ -31,19 +31,16 @@
namespace Ice {
class TargetX8664;
namespace X8664 {
class AssemblerX8664;
} // end of namespace X8664
using namespace ::Ice::X86;
namespace X86Internal {
template <class TraitsType> class AssemblerX86Base;
template <class TraitsType> struct Insts;
template <class TraitsType> class TargetX86Base;
template <class Machine> struct Insts;
template <class Machine> struct MachineTraits;
template <class Machine> class TargetX86Base;
class TargetX8664;
template <> struct MachineTraits<TargetX8664> {
struct TargetX8664Traits {
//----------------------------------------------------------------------------
// ______ ______ __ __
// /\ __ \/\ ___\/\ "-./ \
......@@ -52,6 +49,9 @@ template <> struct MachineTraits<TargetX8664> {
// \/_/\/_/\/_____/\/_/ \/_/
//
//----------------------------------------------------------------------------
static constexpr ::Ice::Assembler::AssemblerKind AsmKind =
::Ice::Assembler::Asm_X8632;
static constexpr bool Is64Bit = true;
static constexpr bool HasPopa = false;
static constexpr bool HasPusha = false;
......@@ -191,7 +191,7 @@ template <> struct MachineTraits<TargetX8664> {
(rm() == reg); // Register codes match.
}
template <class> friend class AssemblerX86Base;
friend class AssemblerX86Base<TargetX8664Traits>;
};
class Address : public Operand {
......@@ -801,10 +801,12 @@ public:
// \/_/\/_/ \/_/\/_____/ \/_/
//
//----------------------------------------------------------------------------
using Insts = ::Ice::X86Internal::Insts<TargetX8664>;
using Traits = TargetX8664Traits;
using Insts = ::Ice::X8664::Insts<Traits>;
using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8664>;
using Assembler = X8664::AssemblerX8664;
using TargetLowering = ::Ice::X8664::TargetX86Base<Traits>;
using ConcreteTarget = ::Ice::X8664::TargetX8664;
using Assembler = ::Ice::X8664::AssemblerX86Base<Traits>;
/// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem
/// and VariableSplit.
......@@ -972,10 +974,7 @@ public:
} TypeAttributes[];
};
} // end of namespace X86Internal
namespace X8664 {
using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
using Traits = ::Ice::X8664::TargetX8664Traits;
} // end of namespace X8664
} // end of namespace Ice
......
src/IceTargetLoweringX86Base.h
......@@ -27,12 +27,16 @@
#include <type_traits>
#include <utility>
#ifndef X86NAMESPACE
#error "You must define the X86 Target namespace."
#endif
namespace Ice {
namespace X86Internal {
namespace X86NAMESPACE {
template <class MachineTraits> class BoolFolding;
using namespace ::Ice::X86;
template <class Machine> struct MachineTraits {};
template <typename Traits> class BoolFolding;
/// TargetX86Base is a template for all X86 Targets, and it relies on the CRT
/// pattern for generating code, delegating to actual backends target-specific
......@@ -44,18 +48,34 @@ template <class Machine> struct MachineTraits {};
///
/// Note: Ideally, we should be able to
///
/// static_assert(std::is_base_of<TargetX86Base<Machine>, Machine>::value);
/// static_assert(std::is_base_of<TargetX86Base<TraitsType>,
/// Machine>::value);
///
/// but that does not work: the compiler does not know that Machine inherits
/// from TargetX86Base at this point in translation.
template <class Machine> class TargetX86Base : public TargetLowering {
template <typename TraitsType> class TargetX86Base : public TargetLowering {
TargetX86Base() = delete;
TargetX86Base(const TargetX86Base &) = delete;
TargetX86Base &operator=(const TargetX86Base &) = delete;
public:
using Traits = MachineTraits<Machine>;
using BoolFolding = ::Ice::X86Internal::BoolFolding<Traits>;
using Traits = TraitsType;
using BoolFolding = BoolFolding<Traits>;
using ConcreteTarget = typename Traits::ConcreteTarget;
using InstructionSetEnum = typename Traits::InstructionSet;
using BrCond = typename Traits::Cond::BrCond;
using CmppsCond = typename Traits::Cond::CmppsCond;
using X86Address = typename Traits::Address;
using X86Operand = typename Traits::X86Operand;
using X86OperandMem = typename Traits::X86OperandMem;
using SegmentRegisters = typename Traits::X86OperandMem::SegmentRegisters;
using SpillVariable = typename Traits::SpillVariable;
using InstX86Br = typename Traits::Insts::Br;
using InstX86FakeRMW = typename Traits::Insts::FakeRMW;
using InstX86Label = typename Traits::Insts::Label;
~TargetX86Base() override = default;
......@@ -156,11 +176,9 @@ public:
void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
size_t BasicFrameOffset, size_t StackAdjBytes,
size_t &InArgsSizeBytes);
typename Traits::Address stackVarToAsmOperand(const Variable *Var) const;
X86Address stackVarToAsmOperand(const Variable *Var) const;
typename Traits::InstructionSet getInstructionSet() const {
return InstructionSet;
}
InstructionSetEnum getInstructionSet() const { return InstructionSet; }
Operand *legalizeUndef(Operand *From, int32_t RegNum = Variable::NoRegister);
protected:
......@@ -186,7 +204,7 @@ protected:
void lowerSwitch(const InstSwitch *Inst) override;
void lowerUnreachable(const InstUnreachable *Inst) override;
void lowerOther(const Inst *Instr) override;
void lowerRMW(const typename Traits::Insts::FakeRMW *RMW);
void lowerRMW(const InstX86FakeRMW *RMW);
void prelowerPhis() override;
uint32_t getCallStackArgumentsSizeBytes(const std::vector<Type> &ArgTypes,
Type ReturnType);
......@@ -277,8 +295,8 @@ protected:
/// Turn a pointer operand into a memory operand that can be used by a real
/// load/store operation. Legalizes the operand as well. This is a nop if the
/// operand is already a legal memory operand.
typename Traits::X86OperandMem *formMemoryOperand(Operand *Ptr, Type Ty,
bool DoLegalize = true);
X86OperandMem *formMemoryOperand(Operand *Ptr, Type Ty,
bool DoLegalize = true);
Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
static Type stackSlotType();
......@@ -316,8 +334,8 @@ protected:
/// @}
/// Return a memory operand corresponding to a stack allocated Variable.
typename Traits::X86OperandMem *
getMemoryOperandForStackSlot(Type Ty, Variable *Slot, uint32_t Offset = 0);
X86OperandMem *getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
uint32_t Offset = 0);
void
makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
......@@ -330,13 +348,13 @@ protected:
void _adc(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Adc>(Dest, Src0);
}
void _adc_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _adc_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::AdcRMW>(DestSrc0, Src1);
}
void _add(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Add>(Dest, Src0);
}
void _add_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _add_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::AddRMW>(DestSrc0, Src1);
}
void _addps(Variable *Dest, Operand *Src0) {
......@@ -354,28 +372,25 @@ protected:
void _andps(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Andps>(Dest, Src0);
}
void _and_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _and_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::AndRMW>(DestSrc0, Src1);
}
void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) {
Context.insert<typename Traits::Insts::Blendvps>(Dest, Src0, Src1);
}
void _br(typename Traits::Cond::BrCond Condition, CfgNode *TargetTrue,
CfgNode *TargetFalse) {
Context.insert<typename Traits::Insts::Br>(
TargetTrue, TargetFalse, Condition, Traits::Insts::Br::Far);
void _br(BrCond Condition, CfgNode *TargetTrue, CfgNode *TargetFalse) {
Context.insert<InstX86Br>(TargetTrue, TargetFalse, Condition,
InstX86Br::Far);
}
void _br(CfgNode *Target) {
Context.insert<typename Traits::Insts::Br>(Target, Traits::Insts::Br::Far);
Context.insert<InstX86Br>(Target, InstX86Br::Far);
}
void _br(typename Traits::Cond::BrCond Condition, CfgNode *Target) {
Context.insert<typename Traits::Insts::Br>(Target, Condition,
Traits::Insts::Br::Far);
void _br(BrCond Condition, CfgNode *Target) {
Context.insert<InstX86Br>(Target, Condition, InstX86Br::Far);
}
void _br(typename Traits::Cond::BrCond Condition,
typename Traits::Insts::Label *Label,
typename Traits::Insts::Br::Mode Kind = Traits::Insts::Br::Near) {
Context.insert<typename Traits::Insts::Br>(Label, Condition, Kind);
void _br(BrCond Condition, InstX86Label *Label,
typename InstX86Br::Mode Kind = InstX86Br::Near) {
Context.insert<InstX86Br>(Label, Condition, Kind);
}
void _bsf(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Bsf>(Dest, Src0);
......@@ -389,15 +404,13 @@ protected:
void _cbwdq(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Cbwdq>(Dest, Src0);
}
void _cmov(Variable *Dest, Operand *Src0,
typename Traits::Cond::BrCond Condition) {
void _cmov(Variable *Dest, Operand *Src0, BrCond Condition) {
Context.insert<typename Traits::Insts::Cmov>(Dest, Src0, Condition);
}
void _cmp(Operand *Src0, Operand *Src1) {
Context.insert<typename Traits::Insts::Icmp>(Src0, Src1);
}
void _cmpps(Variable *Dest, Operand *Src0,
typename Traits::Cond::CmppsCond Condition) {
void _cmpps(Variable *Dest, Operand *Src0, CmppsCond Condition) {
Context.insert<typename Traits::Insts::Cmpps>(Dest, Src0, Condition);
}
void _cmpxchg(Operand *DestOrAddr, Variable *Eax, Variable *Desired,
......@@ -409,8 +422,8 @@ protected:
_set_dest_redefined();
Context.insert<InstFakeUse>(Eax);
}
void _cmpxchg8b(typename Traits::X86OperandMem *Addr, Variable *Edx,
Variable *Eax, Variable *Ecx, Variable *Ebx, bool Locked) {
void _cmpxchg8b(X86OperandMem *Addr, Variable *Edx, Variable *Eax,
Variable *Ecx, Variable *Ebx, bool Locked) {
Context.insert<typename Traits::Insts::Cmpxchg8b>(Addr, Edx, Eax, Ecx, Ebx,
Locked);
// Mark edx, and eax as possibly modified by cmpxchg8b.
......@@ -533,7 +546,7 @@ protected:
void _orps(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Orps>(Dest, Src0);
}
void _or_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _or_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::OrRMW>(DestSrc0, Src1);
}
void _padd(Variable *Dest, Operand *Src0) {
......@@ -605,10 +618,10 @@ protected:
void _sbb(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Sbb>(Dest, Src0);
}
void _sbb_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _sbb_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::SbbRMW>(DestSrc0, Src1);
}
void _setcc(Variable *Dest, typename Traits::Cond::BrCond Condition) {
void _setcc(Variable *Dest, BrCond Condition) {
Context.insert<typename Traits::Insts::Setcc>(Dest, Condition);
}
void _shl(Variable *Dest, Operand *Src0) {
......@@ -629,19 +642,19 @@ protected:
void _sqrtss(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Sqrtss>(Dest, Src0);
}
void _store(Operand *Value, typename Traits::X86Operand *Mem) {
void _store(Operand *Value, X86Operand *Mem) {
Context.insert<typename Traits::Insts::Store>(Value, Mem);
}
void _storep(Variable *Value, typename Traits::X86OperandMem *Mem) {
void _storep(Variable *Value, X86OperandMem *Mem) {
Context.insert<typename Traits::Insts::StoreP>(Value, Mem);
}
void _storeq(Variable *Value, typename Traits::X86OperandMem *Mem) {
void _storeq(Variable *Value, X86OperandMem *Mem) {
Context.insert<typename Traits::Insts::StoreQ>(Value, Mem);
}
void _sub(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Sub>(Dest, Src0);
}
void _sub_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _sub_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::SubRMW>(DestSrc0, Src1);
}
void _subps(Variable *Dest, Operand *Src0) {
......@@ -679,7 +692,7 @@ protected:
void _xorps(Variable *Dest, Operand *Src0) {
Context.insert<typename Traits::Insts::Xorps>(Dest, Src0);
}
void _xor_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
void _xor_rmw(X86OperandMem *DestSrc0, Operand *Src1) {
Context.insert<typename Traits::Insts::XorRMW>(DestSrc0, Src1);
}
......@@ -717,8 +730,7 @@ protected:
bool optimizeScalarMul(Variable *Dest, Operand *Src0, int32_t Src1);
void findRMW();
typename Traits::InstructionSet InstructionSet =
Traits::InstructionSet::Begin;
InstructionSetEnum InstructionSet = Traits::InstructionSet::Begin;
bool IsEbpBasedFrame = false;
bool NeedsStackAlignment = false;
size_t SpillAreaSizeBytes = 0;
......@@ -736,8 +748,8 @@ protected:
/// Randomize a given immediate operand
Operand *randomizeOrPoolImmediate(Constant *Immediate,
int32_t RegNum = Variable::NoRegister);
typename Traits::X86OperandMem *
randomizeOrPoolImmediate(typename Traits::X86OperandMem *MemOperand,
X86OperandMem *
randomizeOrPoolImmediate(X86OperandMem *MemOperand,
int32_t RegNum = Variable::NoRegister);
bool RandomizationPoolingPaused = false;
......@@ -755,13 +767,15 @@ private:
/// Method **exactly** (i.e., no argument promotion is performed.)
template <typename Ret, typename... Args>
typename std::enable_if<!std::is_void<Ret>::value, Ret>::type
dispatchToConcrete(Ret (Machine::*Method)(Args...), Args &&... args) {
return (static_cast<Machine *>(this)->*Method)(std::forward<Args>(args)...);
dispatchToConcrete(Ret (ConcreteTarget::*Method)(Args...), Args &&... args) {
return (static_cast<ConcreteTarget *>(this)->*Method)(
std::forward<Args>(args)...);
}
template <typename... Args>
void dispatchToConcrete(void (Machine::*Method)(Args...), Args &&... args) {
(static_cast<Machine *>(this)->*Method)(std::forward<Args>(args)...);
void dispatchToConcrete(void (ConcreteTarget::*Method)(Args...),
Args &&... args) {
(static_cast<ConcreteTarget *>(this)->*Method)(std::forward<Args>(args)...);
}
void lowerShift64(InstArithmetic::OpKind Op, Operand *Src0Lo, Operand *Src0Hi,
......@@ -775,8 +789,7 @@ private:
/// Emit a setcc instruction if Consumer == nullptr; otherwise emit a
/// specialized version of Consumer.
void setccOrConsumer(typename Traits::Cond::BrCond Condition, Variable *Dest,
const Inst *Consumer);
void setccOrConsumer(BrCond Condition, Variable *Dest, const Inst *Consumer);
/// Emit a mov [1|0] instruction if Consumer == nullptr; otherwise emit a
/// specialized version of Consumer.
......@@ -788,10 +801,10 @@ private:
void lowerSelectVector(const InstSelect *Inst);
/// Helpers for select lowering.
void lowerSelectMove(Variable *Dest, typename Traits::Cond::BrCond Cond,
Operand *SrcT, Operand *SrcF);
void lowerSelectIntMove(Variable *Dest, typename Traits::Cond::BrCond Cond,
Operand *SrcT, Operand *SrcF);
void lowerSelectMove(Variable *Dest, BrCond Cond, Operand *SrcT,
Operand *SrcF);
void lowerSelectIntMove(Variable *Dest, BrCond Cond, Operand *SrcT,
Operand *SrcF);
/// Generic helper to move an arbitrary type from Src to Dest.
void lowerMove(Variable *Dest, Operand *Src, bool IsRedefinition);
......@@ -813,7 +826,7 @@ private:
BoolFolding FoldingInfo;
};
} // end of namespace X86Internal
} // end of namespace X86NAMESPACE
} // end of namespace Ice
#include "IceTargetLoweringX86BaseImpl.h"
......
src/IceTargetLoweringX86BaseImpl.h
This source diff could not be displayed because it is too large. You can view the blob instead.
src/IceTargetLoweringX86RegClass.h
......@@ -18,7 +18,7 @@
#include "IceOperand.h" // RC_Target
namespace Ice {
namespace X86Internal {
namespace X86 {
// Extend enum RegClass with x86-specific register classes.
enum RegClassX86 : uint8_t {
......@@ -30,7 +30,7 @@ enum RegClassX86 : uint8_t {
RCX86_NUM
};
} // end of namespace X86Internal
} // end of namespace X86
} // end of namespace Ice
#endif // SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H
unittest/AssemblerX8632/TestUtil.h
......@@ -15,6 +15,7 @@
#define ASSEMBLERX8632_TESTUTIL_H_
#include "IceAssemblerX8632.h"
#include "IceDefs.h"
#include "gtest/gtest.h"
......@@ -31,14 +32,14 @@ protected:
using Cond = AssemblerX8632::Traits::Cond;
using GPRRegister = AssemblerX8632::Traits::GPRRegister;
using ByteRegister = AssemblerX8632::Traits::ByteRegister;
using Label = ::Ice::X86Internal::Label;
using Label = ::Ice::X8632::Label;
using Traits = AssemblerX8632::Traits;
using XmmRegister = AssemblerX8632::Traits::XmmRegister;
using X87STRegister = AssemblerX8632::Traits::X87STRegister;
AssemblerX8632TestBase() { reset(); }
void reset() { Assembler.reset(new AssemblerX8632()); }
void reset() { Assembler = makeUnique<AssemblerX8632>(); }
AssemblerX8632 *assembler() const { return Assembler.get(); }
......
unittest/AssemblerX8664/TestUtil.h
......@@ -135,7 +135,7 @@ protected:
AssemblerX8664TestBase() { reset(); }
void reset() { Assembler.reset(new AssemblerX8664()); }
void reset() { Assembler = makeUnique<AssemblerX8664>(); }
AssemblerX8664 *assembler() const { return Assembler.get(); }
......
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