Subzero. Code organization.

src/IceAssemblerX8632.h

@@ -16,47 +16,24 @@
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// \brief Implements the Assembler class for x86-32.
+/// \brief Instantiates the Assembler for X86-32.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEASSEMBLERX8632_H
 #define SUBZERO_SRC_ICEASSEMBLERX8632_H
 
-#include "IceAssembler.h"
+#define X86NAMESPACE X8632
 #include "IceAssemblerX86Base.h"
-#include "IceDefs.h"
-#include "IceOperand.h"
+#undef X86NAMESPACE
 #include "IceTargetLoweringX8632Traits.h"
-#include "IceTypes.h"
-#include "IceUtils.h"
 
 namespace Ice {
-
-class TargetX8632;
-
 namespace X8632 {
 
-using Immediate = ::Ice::X86Internal::Immediate;
-using Label = ::Ice::X86Internal::Label;
-
-class AssemblerX8632 : public X86Internal::AssemblerX86Base<TargetX8632> {
-  AssemblerX8632(const AssemblerX8632 &) = delete;
-  AssemblerX8632 &operator=(const AssemblerX8632 &) = delete;
-
-public:
-  explicit AssemblerX8632(bool use_far_branches = false)
-      : X86Internal::AssemblerX86Base<TargetX8632>(Asm_X8632,
-                                                   use_far_branches) {}
-  ~AssemblerX8632() override = default;
-
-  static bool classof(const Assembler *Asm) {
-    return Asm->getKind() == Asm_X8632;
-  }
-
-private:
-  ENABLE_MAKE_UNIQUE;
-};
+using AssemblerX8632 = AssemblerX86Base<X8632::Traits>;
+using Label = AssemblerX8632::Label;
+using Immediate = AssemblerX8632::Immediate;
 
 } // end of namespace X8632
 } // end of namespace Ice

src/IceAssemblerX8664.h

@@ -16,47 +16,24 @@
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// \brief Implements the Assembler class for x86-64.
+/// \brief Instantiates the Assembler for X86-64.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEASSEMBLERX8664_H
 #define SUBZERO_SRC_ICEASSEMBLERX8664_H
 
-#include "IceAssembler.h"
+#define X86NAMESPACE X8664
 #include "IceAssemblerX86Base.h"
-#include "IceDefs.h"
-#include "IceOperand.h"
+#undef X86NAMESPACE
 #include "IceTargetLoweringX8664Traits.h"
-#include "IceTypes.h"
-#include "IceUtils.h"
 
 namespace Ice {
-
-class TargetX8664;
-
 namespace X8664 {
 
-using Immediate = ::Ice::X86Internal::Immediate;
-using Label = ::Ice::X86Internal::Label;
-
-class AssemblerX8664 : public X86Internal::AssemblerX86Base<TargetX8664> {
-  AssemblerX8664(const AssemblerX8664 &) = delete;
-  AssemblerX8664 &operator=(const AssemblerX8664 &) = delete;
-
-public:
-  explicit AssemblerX8664(bool use_far_branches = false)
-      : X86Internal::AssemblerX86Base<TargetX8664>(Asm_X8664,
-                                                   use_far_branches) {}
-  ~AssemblerX8664() override = default;
-
-  static bool classof(const Assembler *Asm) {
-    return Asm->getKind() == Asm_X8664;
-  }
-
-private:
-  ENABLE_MAKE_UNIQUE;
-};
+using AssemblerX8664 = AssemblerX86Base<X8664::Traits>;
+using Label = AssemblerX8664::Label;
+using Immediate = AssemblerX8664::Immediate;
 
 } // end of namespace X8664
 } // end of namespace Ice

src/IceInstARM32.cpp

@@ -24,6 +24,7 @@
 #include "IceTargetLoweringARM32.h"
 
 namespace Ice {
+namespace ARM32 {
 
 namespace {
 
@@ -2151,4 +2152,5 @@ template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
+} // end of namespace ARM32
 } // end of namespace Ice

src/IceInstARM32.h

@@ -25,6 +25,7 @@
 #include "IceOperand.h"
 
 namespace Ice {
+namespace ARM32 {
 
 class TargetARM32;
 
@@ -1376,6 +1377,7 @@ template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
+} // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H

src/IceInstMIPS32.cpp

@@ -23,6 +23,7 @@
 #include <limits>
 
 namespace Ice {
+namespace MIPS32 {
 
 bool OperandMIPS32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) {
   (void)SignExt;
@@ -274,4 +275,5 @@ void InstMIPS32Mov::emitSingleDestSingleSource(const Cfg *Func) const {
   getSrc(0)->emit(Func);
 }
 
+} // end of namespace MIPS32
 } // end of namespace Ice

src/IceInstMIPS32.h

@@ -25,6 +25,7 @@
 #include "IceOperand.h"
 
 namespace Ice {
+namespace MIPS32 {
 
 class TargetMIPS32;
 
@@ -395,6 +396,7 @@ private:
   Variable *DestHi = nullptr;
 };
 
+} // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTMIPS32_H

src/IceInstX8632.cpp

@@ -28,10 +28,10 @@
 
 namespace Ice {
 
-namespace X86Internal {
+namespace X8632 {
 
-const MachineTraits<TargetX8632>::InstBrAttributesType
-    MachineTraits<TargetX8632>::InstBrAttributes[] = {
+const TargetX8632Traits::InstBrAttributesType
+    TargetX8632Traits::InstBrAttributes[] = {
 #define X(val, encode, opp, dump, emit)                                        \
   { X8632::Traits::Cond::opp, dump, emit }                                     \
   ,
@@ -39,8 +39,8 @@ const MachineTraits<TargetX8632>::InstBrAttributesType
 #undef X
 };
 
-const MachineTraits<TargetX8632>::InstCmppsAttributesType
-    MachineTraits<TargetX8632>::InstCmppsAttributes[] = {
+const TargetX8632Traits::InstCmppsAttributesType
+    TargetX8632Traits::InstCmppsAttributes[] = {
 #define X(val, emit)                                                           \
   { emit }                                                                     \
   ,
@@ -48,8 +48,8 @@ const MachineTraits<TargetX8632>::InstCmppsAttributesType
 #undef X
 };
 
-const MachineTraits<TargetX8632>::TypeAttributesType
-    MachineTraits<TargetX8632>::TypeAttributes[] = {
+const TargetX8632Traits::TypeAttributesType
+    TargetX8632Traits::TypeAttributes[] = {
 #define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld)             \
   { cvt, sdss, pdps, spsd, pack, width, fld }                                  \
   ,
@@ -57,27 +57,28 @@ const MachineTraits<TargetX8632>::TypeAttributesType
 #undef X
 };
 
-const char *MachineTraits<TargetX8632>::InstSegmentRegNames[] = {
+const char *TargetX8632Traits::InstSegmentRegNames[] = {
 #define X(val, name, prefix) name,
     SEG_REGX8632_TABLE
 #undef X
 };
 
-uint8_t MachineTraits<TargetX8632>::InstSegmentPrefixes[] = {
+uint8_t TargetX8632Traits::InstSegmentPrefixes[] = {
 #define X(val, name, prefix) prefix,
     SEG_REGX8632_TABLE
 #undef X
 };
 
-void MachineTraits<TargetX8632>::X86Operand::dump(const Cfg *,
-                                                  Ostream &Str) const {
+void TargetX8632Traits::X86Operand::dump(const Cfg *, Ostream &Str) const {
   if (BuildDefs::dump())
     Str << "<OperandX8632>";
 }
 
-MachineTraits<TargetX8632>::X86OperandMem::X86OperandMem(
-    Cfg *Func, Type Ty, Variable *Base, Constant *Offset, Variable *Index,
-    uint16_t Shift, SegmentRegisters SegmentReg)
+TargetX8632Traits::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
+                                                Variable *Base,
+                                                Constant *Offset,
+                                                Variable *Index, uint16_t Shift,
+                                                SegmentRegisters SegmentReg)
     : X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
       Shift(Shift), SegmentReg(SegmentReg), Randomized(false) {
   assert(Shift <= 3);
@@ -99,8 +100,9 @@ MachineTraits<TargetX8632>::X86OperandMem::X86OperandMem(
 }
 
 namespace {
-static int32_t GetRematerializableOffset(Variable *Var,
-                                         const Ice::TargetX8632 *Target) {
+static int32_t
+GetRematerializableOffset(Variable *Var,
+                          const Ice::X8632::TargetX8632 *Target) {
   int32_t Disp = Var->getStackOffset();
   SizeT RegNum = static_cast<SizeT>(Var->getRegNum());
   if (RegNum == Target->getFrameReg()) {
@@ -112,10 +114,11 @@ static int32_t GetRematerializableOffset(Variable *Var,
 }
 } // end of anonymous namespace
 
-void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const {
+void TargetX8632Traits::X86OperandMem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  const auto *Target = static_cast<const Ice::TargetX8632 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
   // If the base is rematerializable, we need to replace it with the correct
   // physical register (esp or ebp), and update the Offset.
   int32_t Disp = 0;
@@ -166,7 +169,7 @@ void MachineTraits<TargetX8632>::X86OperandMem::emit(const Cfg *Func) const {
   }
 }
 
-void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
+void TargetX8632Traits::X86OperandMem::dump(const Cfg *Func,
                                             Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
@@ -177,7 +180,8 @@ void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
   bool Dumped = false;
   Str << "[";
   int32_t Disp = 0;
-  const auto *Target = static_cast<const Ice::TargetX8632 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
   if (getBase() && getBase()->isRematerializable()) {
     Disp += GetRematerializableOffset(getBase(), Target);
   }
@@ -230,20 +234,20 @@ void MachineTraits<TargetX8632>::X86OperandMem::dump(const Cfg *Func,
   Str << "]";
 }
 
-void MachineTraits<TargetX8632>::X86OperandMem::emitSegmentOverride(
-    MachineTraits<TargetX8632>::Assembler *Asm) const {
+void TargetX8632Traits::X86OperandMem::emitSegmentOverride(
+    TargetX8632Traits::Assembler *Asm) const {
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Asm->emitSegmentOverride(X8632::Traits::InstSegmentPrefixes[SegmentReg]);
   }
 }
 
-MachineTraits<TargetX8632>::Address
-MachineTraits<TargetX8632>::X86OperandMem::toAsmAddress(
-    MachineTraits<TargetX8632>::Assembler *Asm,
+TargetX8632Traits::Address TargetX8632Traits::X86OperandMem::toAsmAddress(
+    TargetX8632Traits::Assembler *Asm,
     const Ice::TargetLowering *TargetLowering) const {
   int32_t Disp = 0;
-  const auto *Target = static_cast<const Ice::TargetX8632 *>(TargetLowering);
+  const auto *Target =
+      static_cast<const ::Ice::X8632::TargetX8632 *>(TargetLowering);
   if (getBase() && getBase()->isRematerializable()) {
     Disp += GetRematerializableOffset(getBase(), Target);
   }
@@ -284,8 +288,8 @@ MachineTraits<TargetX8632>::X86OperandMem::toAsmAddress(
   }
 }
 
-MachineTraits<TargetX8632>::Address
-MachineTraits<TargetX8632>::VariableSplit::toAsmAddress(const Cfg *Func) const {
+TargetX8632Traits::Address
+TargetX8632Traits::VariableSplit::toAsmAddress(const Cfg *Func) const {
   assert(!Var->hasReg());
   const ::Ice::TargetLowering *Target = Func->getTarget();
   int32_t Offset = Var->getStackOffset() + getOffset();
@@ -293,7 +297,7 @@ MachineTraits<TargetX8632>::VariableSplit::toAsmAddress(const Cfg *Func) const {
                                 Offset, AssemblerFixup::NoFixup);
 }
 
-void MachineTraits<TargetX8632>::VariableSplit::emit(const Cfg *Func) const {
+void TargetX8632Traits::VariableSplit::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
@@ -307,7 +311,7 @@ void MachineTraits<TargetX8632>::VariableSplit::emit(const Cfg *Func) const {
   Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
 }
 
-void MachineTraits<TargetX8632>::VariableSplit::dump(const Cfg *Func,
+void TargetX8632Traits::VariableSplit::dump(const Cfg *Func,
                                             Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
@@ -327,7 +331,7 @@ void MachineTraits<TargetX8632>::VariableSplit::dump(const Cfg *Func,
   Str << ")";
 }
 
-} // namespace X86Internal
+} // namespace X8632
 } // end of namespace Ice
 
-X86INSTS_DEFINE_STATIC_DATA(TargetX8632)
+X86INSTS_DEFINE_STATIC_DATA(X8632, X8632::Traits)

src/IceInstX8632.h

@@ -28,7 +28,9 @@
 
 #include "IceDefs.h"
 #include "IceInst.h"
+#define X86NAMESPACE X8632
 #include "IceInstX86Base.h"
+#undef X86NAMESPACE
 #include "IceOperand.h"
 #include "IceTargetLoweringX8632Traits.h"
 

src/IceInstX8664.cpp

@@ -29,10 +29,10 @@
 
 namespace Ice {
 
-namespace X86Internal {
+namespace X8664 {
 
-const MachineTraits<TargetX8664>::InstBrAttributesType
-    MachineTraits<TargetX8664>::InstBrAttributes[] = {
+const TargetX8664Traits::InstBrAttributesType
+    TargetX8664Traits::InstBrAttributes[] = {
 #define X(val, encode, opp, dump, emit)                                        \
   { X8664::Traits::Cond::opp, dump, emit }                                     \
   ,
@@ -40,8 +40,8 @@ const MachineTraits<TargetX8664>::InstBrAttributesType
 #undef X
 };
 
-const MachineTraits<TargetX8664>::InstCmppsAttributesType
-    MachineTraits<TargetX8664>::InstCmppsAttributes[] = {
+const TargetX8664Traits::InstCmppsAttributesType
+    TargetX8664Traits::InstCmppsAttributes[] = {
 #define X(val, emit)                                                           \
   { emit }                                                                     \
   ,
@@ -49,8 +49,8 @@ const MachineTraits<TargetX8664>::InstCmppsAttributesType
 #undef X
 };
 
-const MachineTraits<TargetX8664>::TypeAttributesType
-    MachineTraits<TargetX8664>::TypeAttributes[] = {
+const TargetX8664Traits::TypeAttributesType
+    TargetX8664Traits::TypeAttributes[] = {
 #define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld)             \
   { cvt, sdss, pdps, spsd, pack, width, fld }                                  \
   ,
@@ -58,17 +58,15 @@ const MachineTraits<TargetX8664>::TypeAttributesType
 #undef X
 };
 
-void MachineTraits<TargetX8664>::X86Operand::dump(const Cfg *,
-                                                  Ostream &Str) const {
+void TargetX8664Traits::X86Operand::dump(const Cfg *, Ostream &Str) const {
   if (BuildDefs::dump())
     Str << "<OperandX8664>";
 }
 
-MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
+TargetX8664Traits::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
                                                 Variable *Base,
                                                 Constant *Offset,
-                                                         Variable *Index,
-                                                         uint16_t Shift)
+                                                Variable *Index, uint16_t Shift)
     : X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
       Shift(Shift) {
   assert(Shift <= 3);
@@ -90,8 +88,9 @@ MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
 }
 
 namespace {
-static int32_t getRematerializableOffset(Variable *Var,
-                                         const Ice::TargetX8664 *Target) {
+static int32_t
+getRematerializableOffset(Variable *Var,
+                          const ::Ice::X8664::TargetX8664 *Target) {
   int32_t Disp = Var->getStackOffset();
   SizeT RegNum = static_cast<SizeT>(Var->getRegNum());
   if (RegNum == Target->getFrameReg()) {
@@ -103,10 +102,11 @@ static int32_t getRematerializableOffset(Variable *Var,
 }
 } // end of anonymous namespace
 
-void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
+void TargetX8664Traits::X86OperandMem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  const auto *Target = static_cast<const Ice::TargetX8664 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
   // If the base is rematerializable, we need to replace it with the correct
   // physical register (stack or base pointer), and update the Offset.
   int32_t Disp = 0;
@@ -164,14 +164,15 @@ void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
   }
 }
 
-void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
+void TargetX8664Traits::X86OperandMem::dump(const Cfg *Func,
                                             Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
   bool Dumped = false;
   Str << "[";
   int32_t Disp = 0;
-  const auto *Target = static_cast<const Ice::TargetX8664 *>(Func->getTarget());
+  const auto *Target =
+      static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
   if (getBase() && getBase()->isRematerializable()) {
     Disp += getRematerializableOffset(getBase(), Target);
   }
@@ -223,11 +224,11 @@ void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
   Str << "]";
 }
 
-MachineTraits<TargetX8664>::Address
-MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
-    MachineTraits<TargetX8664>::Assembler *Asm,
+TargetX8664Traits::Address TargetX8664Traits::X86OperandMem::toAsmAddress(
+    TargetX8664Traits::Assembler *Asm,
     const Ice::TargetLowering *TargetLowering) const {
-  const auto *Target = static_cast<const Ice::TargetX8664 *>(TargetLowering);
+  const auto *Target =
+      static_cast<const ::Ice::X8664::TargetX8664 *>(TargetLowering);
   int32_t Disp = 0;
   if (getBase() && getBase()->isRematerializable()) {
     Disp += getRematerializableOffset(getBase(), Target);
@@ -266,8 +267,8 @@ MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
   }
 }
 
-MachineTraits<TargetX8664>::Address
-MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
+TargetX8664Traits::Address
+TargetX8664Traits::VariableSplit::toAsmAddress(const Cfg *Func) const {
   assert(!Var->hasReg());
   const ::Ice::TargetLowering *Target = Func->getTarget();
   int32_t Offset = Var->getStackOffset() + getOffset();
@@ -275,7 +276,7 @@ MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
                                 Offset, AssemblerFixup::NoFixup);
 }
 
-void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
+void TargetX8664Traits::VariableSplit::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
@@ -289,7 +290,7 @@ void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
   Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
 }
 
-void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
+void TargetX8664Traits::VariableSplit::dump(const Cfg *Func,
                                             Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
@@ -309,7 +310,7 @@ void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
   Str << ")";
 }
 
-} // namespace X86Internal
+} // namespace X8664
 } // end of namespace Ice
 
-X86INSTS_DEFINE_STATIC_DATA(TargetX8664)
+X86INSTS_DEFINE_STATIC_DATA(X8664, X8664::Traits)

src/IceInstX8664.h

@@ -26,7 +26,9 @@
 
 #include "IceDefs.h"
 #include "IceInst.h"
+#define X86NAMESPACE X8664
 #include "IceInstX86Base.h"
+#undef X86NAMESPACE
 #include "IceOperand.h"
 #include "IceTargetLoweringX8664Traits.h"
 

src/IceRegistersARM32.h

@@ -21,6 +21,7 @@
 #include "IceTypes.h"
 
 namespace Ice {
+namespace ARM32 {
 
 class RegARM32 {
 public:
@@ -136,6 +137,7 @@ public:
 // Extend enum RegClass with ARM32-specific register classes (if any).
 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
 
+} // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H

src/IceRegistersMIPS32.h

@@ -21,7 +21,7 @@
 #include "IceTypes.h"
 
 namespace Ice {
-
+namespace MIPS32 {
 namespace RegMIPS32 {
 
 /// An enum of every register. The enum value may not match the encoding
@@ -63,6 +63,7 @@ static inline GPRRegister getEncodedGPR(int32_t RegNum) {
 // Extend enum RegClass with MIPS32-specific register classes (if any).
 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target };
 
+} // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H

src/IceTargetLoweringARM32.cpp

@@ -37,23 +37,24 @@
 
 namespace ARM32 {
 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
-  return ::Ice::TargetARM32::create(Func);
+  return ::Ice::ARM32::TargetARM32::create(Func);
 }
 
 std::unique_ptr<::Ice::TargetDataLowering>
 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetDataARM32::create(Ctx);
+  return ::Ice::ARM32::TargetDataARM32::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetHeaderARM32::create(Ctx);
+  return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
-void staticInit() { ::Ice::TargetARM32::staticInit(); }
+void staticInit() { ::Ice::ARM32::TargetARM32::staticInit(); }
 } // end of namespace ARM32
 
 namespace Ice {
+namespace ARM32 {
 
 namespace {
 
@@ -6447,4 +6448,5 @@ llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
+} // end of namespace ARM32
 } // end of namespace Ice

src/IceTargetLoweringARM32.h

@@ -25,6 +25,7 @@
 #include "llvm/ADT/SmallBitVector.h"
 
 namespace Ice {
+namespace ARM32 {
 
 // Class encapsulating ARM cpu features / instruction set.
 class TargetARM32Features {
@@ -1206,6 +1207,7 @@ private:
   TargetARM32Features CPUFeatures;
 };
 
+} // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H

src/IceTargetLoweringMIPS32.cpp

@@ -32,23 +32,24 @@
 
 namespace MIPS32 {
 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
-  return ::Ice::TargetMIPS32::create(Func);
+  return ::Ice::MIPS32::TargetMIPS32::create(Func);
 }
 
 std::unique_ptr<::Ice::TargetDataLowering>
 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetDataMIPS32::create(Ctx);
+  return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetHeaderMIPS32::create(Ctx);
+  return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx);
 }
 
-void staticInit() { ::Ice::TargetMIPS32::staticInit(); }
+void staticInit() { ::Ice::MIPS32::TargetMIPS32::staticInit(); }
 } // end of namespace MIPS32
 
 namespace Ice {
+namespace MIPS32 {
 
 using llvm::isInt;
 
@@ -1100,4 +1101,5 @@ llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 llvm::SmallBitVector TargetMIPS32::ScratchRegs;
 
+} // end of namespace MIPS32
 } // end of namespace Ice

src/IceTargetLoweringMIPS32.h

@@ -23,6 +23,7 @@
 #include "IceTargetLowering.h"
 
 namespace Ice {
+namespace MIPS32 {
 
 class TargetMIPS32 : public TargetLowering {
   TargetMIPS32() = delete;
@@ -310,6 +311,7 @@ private:
   ~TargetHeaderMIPS32() = default;
 };
 
+} // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H

src/IceTargetLoweringX8632.cpp

@@ -16,27 +16,27 @@
 #include "IceTargetLoweringX8632.h"
 
 #include "IceTargetLoweringX8632Traits.h"
-#include "IceTargetLoweringX86Base.h"
 
 namespace X8632 {
 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
-  return ::Ice::TargetX8632::create(Func);
+  return ::Ice::X8632::TargetX8632::create(Func);
 }
 
 std::unique_ptr<::Ice::TargetDataLowering>
 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetDataX8632::create(Ctx);
+  return ::Ice::X8632::TargetDataX8632::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetHeaderX8632::create(Ctx);
+  return ::Ice::X8632::TargetHeaderX8632::create(Ctx);
 }
 
-void staticInit() { ::Ice::TargetX8632::staticInit(); }
+void staticInit() { ::Ice::X8632::TargetX8632::staticInit(); }
 } // end of namespace X8632
 
 namespace Ice {
+namespace X8632 {
 
 //------------------------------------------------------------------------------
 //      ______   ______     ______     __     ______   ______
@@ -46,9 +46,7 @@ namespace Ice {
 //         \/_/   \/_/ /_/   \/_/\/_/   \/_/     \/_/   \/_____/
 //
 //------------------------------------------------------------------------------
-namespace X86Internal {
-const MachineTraits<TargetX8632>::TableFcmpType
-    MachineTraits<TargetX8632>::TableFcmp[] = {
+const TargetX8632Traits::TableFcmpType TargetX8632Traits::TableFcmp[] = {
 #define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
   {                                                                            \
     dflt, swapS, X8632::Traits::Cond::C1, X8632::Traits::Cond::C2, swapV,      \
@@ -59,11 +57,9 @@ const MachineTraits<TargetX8632>::TableFcmpType
 #undef X
 };
 
-const size_t MachineTraits<TargetX8632>::TableFcmpSize =
-    llvm::array_lengthof(TableFcmp);
+const size_t TargetX8632Traits::TableFcmpSize = llvm::array_lengthof(TableFcmp);
 
-const MachineTraits<TargetX8632>::TableIcmp32Type
-    MachineTraits<TargetX8632>::TableIcmp32[] = {
+const TargetX8632Traits::TableIcmp32Type TargetX8632Traits::TableIcmp32[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
   { X8632::Traits::Cond::C_32 }                                                \
   ,
@@ -71,11 +67,10 @@ const MachineTraits<TargetX8632>::TableIcmp32Type
 #undef X
 };
 
-const size_t MachineTraits<TargetX8632>::TableIcmp32Size =
+const size_t TargetX8632Traits::TableIcmp32Size =
     llvm::array_lengthof(TableIcmp32);
 
-const MachineTraits<TargetX8632>::TableIcmp64Type
-    MachineTraits<TargetX8632>::TableIcmp64[] = {
+const TargetX8632Traits::TableIcmp64Type TargetX8632Traits::TableIcmp64[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
   {                                                                            \
     X8632::Traits::Cond::C1_64, X8632::Traits::Cond::C2_64,                    \
@@ -86,11 +81,11 @@ const MachineTraits<TargetX8632>::TableIcmp64Type
 #undef X
 };
 
-const size_t MachineTraits<TargetX8632>::TableIcmp64Size =
+const size_t TargetX8632Traits::TableIcmp64Size =
     llvm::array_lengthof(TableIcmp64);
 
-const MachineTraits<TargetX8632>::TableTypeX8632AttributesType
-    MachineTraits<TargetX8632>::TableTypeX8632Attributes[] = {
+const TargetX8632Traits::TableTypeX8632AttributesType
+    TargetX8632Traits::TableTypeX8632Attributes[] = {
 #define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld)             \
   { IceType_##elementty }                                                      \
   ,
@@ -98,26 +93,24 @@ const MachineTraits<TargetX8632>::TableTypeX8632AttributesType
 #undef X
 };
 
-const size_t MachineTraits<TargetX8632>::TableTypeX8632AttributesSize =
+const size_t TargetX8632Traits::TableTypeX8632AttributesSize =
     llvm::array_lengthof(TableTypeX8632Attributes);
 
-const uint32_t MachineTraits<TargetX8632>::X86_STACK_ALIGNMENT_BYTES = 16;
-const char *MachineTraits<TargetX8632>::TargetName = "X8632";
+const uint32_t TargetX8632Traits::X86_STACK_ALIGNMENT_BYTES = 16;
+const char *TargetX8632Traits::TargetName = "X8632";
 
 template <>
 std::array<llvm::SmallBitVector, RCX86_NUM>
-    TargetX86Base<TargetX8632>::TypeToRegisterSet = {{}};
+    TargetX86Base<X8632::Traits>::TypeToRegisterSet = {{}};
 
 template <>
 std::array<llvm::SmallBitVector,
-           TargetX86Base<TargetX8632>::Traits::RegisterSet::Reg_NUM>
-    TargetX86Base<TargetX8632>::RegisterAliases = {{}};
+           TargetX86Base<X8632::Traits>::Traits::RegisterSet::Reg_NUM>
+    TargetX86Base<X8632::Traits>::RegisterAliases = {{}};
 
 template <>
 llvm::SmallBitVector
-    TargetX86Base<TargetX8632>::ScratchRegs = llvm::SmallBitVector();
-
-} // end of namespace X86Internal
+    TargetX86Base<X8632::Traits>::ScratchRegs = llvm::SmallBitVector();
 
 //------------------------------------------------------------------------------
 //     __      ______  __     __  ______  ______  __  __   __  ______
@@ -1018,4 +1011,5 @@ ICETYPE_TABLE
 } // end of namespace dummy3
 } // end of anonymous namespace
 
+} // end of namespace X8632
 } // end of namespace Ice

src/IceTargetLoweringX8632.h

@@ -18,16 +18,18 @@
 
 #include "IceAssemblerX8632.h"
 #include "IceDefs.h"
-#include "IceInstX8632.h"
 #include "IceRegistersX8632.h"
 #include "IceTargetLowering.h"
-#include "IceTargetLoweringX8632Traits.h"
+#include "IceInstX8632.h"
+#define X86NAMESPACE X8632
 #include "IceTargetLoweringX86Base.h"
+#undef X86NAMESPACE
+#include "IceTargetLoweringX8632Traits.h"
 
 namespace Ice {
+namespace X8632 {
 
-class TargetX8632 final
-    : public ::Ice::X86Internal::TargetX86Base<TargetX8632> {
+class TargetX8632 final : public ::Ice::X8632::TargetX86Base<X8632::Traits> {
   TargetX8632() = delete;
   TargetX8632(const TargetX8632 &) = delete;
   TargetX8632 &operator=(const TargetX8632 &) = delete;
@@ -55,7 +57,7 @@ protected:
 
 private:
   ENABLE_MAKE_UNIQUE;
-  friend class ::Ice::X86Internal::TargetX86Base<TargetX8632>;
+  friend class X8632::TargetX86Base<X8632::Traits>;
 
   Operand *createNaClReadTPSrcOperand() {
     Constant *Zero = Ctx->getConstantZero(IceType_i32);
@@ -108,6 +110,7 @@ private:
   ~TargetHeaderX8632() = default;
 };
 
+} // end of namespace X8632
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632_H

src/IceTargetLoweringX8632Traits.h

@@ -30,19 +30,16 @@
 
 namespace Ice {
 
-class TargetX8632;
-
 namespace X8632 {
-class AssemblerX8632;
-} // end of namespace X8632
-
-namespace X86Internal {
+using namespace ::Ice::X86;
 
 template <class Machine> struct Insts;
-template <class Machine> struct MachineTraits;
 template <class Machine> class TargetX86Base;
+template <class Machine> class AssemblerX86Base;
 
-template <> struct MachineTraits<TargetX8632> {
+class TargetX8632;
+
+struct TargetX8632Traits {
   //----------------------------------------------------------------------------
   //     ______  ______  __    __
   //    /\  __ \/\  ___\/\ "-./  \
@@ -51,6 +48,9 @@ template <> struct MachineTraits<TargetX8632> {
   //      \/_/\/_/\/_____/\/_/  \/_/
   //
   //----------------------------------------------------------------------------
+  static constexpr ::Ice::Assembler::AssemblerKind AsmKind =
+      ::Ice::Assembler::Asm_X8632;
+
   static constexpr bool Is64Bit = false;
   static constexpr bool HasPopa = true;
   static constexpr bool HasPusha = true;
@@ -171,7 +171,7 @@ template <> struct MachineTraits<TargetX8632> {
              ((encoding_[0] & 0x07) == reg); // Register codes match.
     }
 
-    template <class> friend class AssemblerX86Base;
+    friend class AssemblerX86Base<TargetX8632Traits>;
   };
 
   class Address : public Operand {
@@ -752,10 +752,12 @@ public:
   //      \/_/\/_/ \/_/\/_____/  \/_/
   //
   //----------------------------------------------------------------------------
-  using Insts = ::Ice::X86Internal::Insts<TargetX8632>;
+  using Traits = TargetX8632Traits;
+  using Insts = ::Ice::X8632::Insts<Traits>;
 
-  using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8632>;
-  using Assembler = X8632::AssemblerX8632;
+  using TargetLowering = ::Ice::X8632::TargetX86Base<Traits>;
+  using ConcreteTarget = ::Ice::X8632::TargetX8632;
+  using Assembler = ::Ice::X8632::AssemblerX86Base<Traits>;
 
   /// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem
   /// and VariableSplit.
@@ -932,10 +934,7 @@ public:
   static uint8_t InstSegmentPrefixes[];
 };
 
-} // end of namespace X86Internal
-
-namespace X8632 {
-using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>;
+using Traits = ::Ice::X8632::TargetX8632Traits;
 } // end of namespace X8632
 
 } // end of namespace Ice

src/IceTargetLoweringX8664.cpp

@@ -16,27 +16,27 @@
 #include "IceTargetLoweringX8664.h"
 
 #include "IceTargetLoweringX8664Traits.h"
-#include "IceTargetLoweringX86Base.h"
 
 namespace X8664 {
 std::unique_ptr<::Ice::TargetLowering> createTargetLowering(::Ice::Cfg *Func) {
-  return ::Ice::TargetX8664::create(Func);
+  return ::Ice::X8664::TargetX8664::create(Func);
 }
 
 std::unique_ptr<::Ice::TargetDataLowering>
 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetDataX8664::create(Ctx);
+  return ::Ice::X8664::TargetDataX8664::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
-  return ::Ice::TargetHeaderX8664::create(Ctx);
+  return ::Ice::X8664::TargetHeaderX8664::create(Ctx);
 }
 
-void staticInit() { ::Ice::TargetX8664::staticInit(); }
+void staticInit() { ::Ice::X8664::TargetX8664::staticInit(); }
 } // end of namespace X8664
 
 namespace Ice {
+namespace X8664 {
 
 //------------------------------------------------------------------------------
 //      ______   ______     ______     __     ______   ______
@@ -46,9 +46,7 @@ namespace Ice {
 //         \/_/   \/_/ /_/   \/_/\/_/   \/_/     \/_/   \/_____/
 //
 //------------------------------------------------------------------------------
-namespace X86Internal {
-const MachineTraits<TargetX8664>::TableFcmpType
-    MachineTraits<TargetX8664>::TableFcmp[] = {
+const TargetX8664Traits::TableFcmpType TargetX8664Traits::TableFcmp[] = {
 #define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
   {                                                                            \
     dflt, swapS, X8664::Traits::Cond::C1, X8664::Traits::Cond::C2, swapV,      \
@@ -59,11 +57,9 @@ const MachineTraits<TargetX8664>::TableFcmpType
 #undef X
 };
 
-const size_t MachineTraits<TargetX8664>::TableFcmpSize =
-    llvm::array_lengthof(TableFcmp);
+const size_t TargetX8664Traits::TableFcmpSize = llvm::array_lengthof(TableFcmp);
 
-const MachineTraits<TargetX8664>::TableIcmp32Type
-    MachineTraits<TargetX8664>::TableIcmp32[] = {
+const TargetX8664Traits::TableIcmp32Type TargetX8664Traits::TableIcmp32[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
   { X8664::Traits::Cond::C_32 }                                                \
   ,
@@ -71,11 +67,10 @@ const MachineTraits<TargetX8664>::TableIcmp32Type
 #undef X
 };
 
-const size_t MachineTraits<TargetX8664>::TableIcmp32Size =
+const size_t TargetX8664Traits::TableIcmp32Size =
     llvm::array_lengthof(TableIcmp32);
 
-const MachineTraits<TargetX8664>::TableIcmp64Type
-    MachineTraits<TargetX8664>::TableIcmp64[] = {
+const TargetX8664Traits::TableIcmp64Type TargetX8664Traits::TableIcmp64[] = {
 #define X(val, C_32, C1_64, C2_64, C3_64)                                      \
   {                                                                            \
     X8664::Traits::Cond::C1_64, X8664::Traits::Cond::C2_64,                    \
@@ -86,11 +81,11 @@ const MachineTraits<TargetX8664>::TableIcmp64Type
 #undef X
 };
 
-const size_t MachineTraits<TargetX8664>::TableIcmp64Size =
+const size_t TargetX8664Traits::TableIcmp64Size =
     llvm::array_lengthof(TableIcmp64);
 
-const MachineTraits<TargetX8664>::TableTypeX8664AttributesType
-    MachineTraits<TargetX8664>::TableTypeX8664Attributes[] = {
+const TargetX8664Traits::TableTypeX8664AttributesType
+    TargetX8664Traits::TableTypeX8664Attributes[] = {
 #define X(tag, elementty, cvt, sdss, pdps, spsd, pack, width, fld)             \
   { IceType_##elementty }                                                      \
   ,
@@ -98,26 +93,24 @@ const MachineTraits<TargetX8664>::TableTypeX8664AttributesType
 #undef X
 };
 
-const size_t MachineTraits<TargetX8664>::TableTypeX8664AttributesSize =
+const size_t TargetX8664Traits::TableTypeX8664AttributesSize =
     llvm::array_lengthof(TableTypeX8664Attributes);
 
-const uint32_t MachineTraits<TargetX8664>::X86_STACK_ALIGNMENT_BYTES = 16;
-const char *MachineTraits<TargetX8664>::TargetName = "X8664";
+const uint32_t TargetX8664Traits::X86_STACK_ALIGNMENT_BYTES = 16;
+const char *TargetX8664Traits::TargetName = "X8664";
 
 template <>
 std::array<llvm::SmallBitVector, RCX86_NUM>
-    TargetX86Base<TargetX8664>::TypeToRegisterSet = {{}};
+    TargetX86Base<X8664::Traits>::TypeToRegisterSet = {{}};
 
 template <>
 std::array<llvm::SmallBitVector,
-           TargetX86Base<TargetX8664>::Traits::RegisterSet::Reg_NUM>
-    TargetX86Base<TargetX8664>::RegisterAliases = {{}};
+           TargetX86Base<X8664::Traits>::Traits::RegisterSet::Reg_NUM>
+    TargetX86Base<X8664::Traits>::RegisterAliases = {{}};
 
 template <>
 llvm::SmallBitVector
-    TargetX86Base<TargetX8664>::ScratchRegs = llvm::SmallBitVector();
-
-} // end of namespace X86Internal
+    TargetX86Base<X8664::Traits>::ScratchRegs = llvm::SmallBitVector();
 
 //------------------------------------------------------------------------------
 //     __      ______  __     __  ______  ______  __  __   __  ______
@@ -1050,4 +1043,5 @@ ICETYPE_TABLE
 } // end of namespace dummy3
 } // end of anonymous namespace
 
+} // end of namespace X8664
 } // end of namespace Ice

src/IceTargetLoweringX8664.h

@@ -21,13 +21,15 @@
 #include "IceGlobalContext.h"
 #include "IceInstX8664.h"
 #include "IceTargetLowering.h"
-#include "IceTargetLoweringX8664Traits.h"
+#define X86NAMESPACE X8664
 #include "IceTargetLoweringX86Base.h"
+#undef X86NAMESPACE
+#include "IceTargetLoweringX8664Traits.h"
 
 namespace Ice {
+namespace X8664 {
 
-class TargetX8664 final
-    : public ::Ice::X86Internal::TargetX86Base<TargetX8664> {
+class TargetX8664 final : public X8664::TargetX86Base<X8664::Traits> {
   TargetX8664() = delete;
   TargetX8664(const TargetX8664 &) = delete;
   TargetX8664 &operator=(const TargetX8664 &) = delete;
@@ -55,10 +57,10 @@ protected:
 
 private:
   ENABLE_MAKE_UNIQUE;
-  friend class ::Ice::X86Internal::TargetX86Base<TargetX8664>;
+  friend class X8664::TargetX86Base<X8664::Traits>;
 
   explicit TargetX8664(Cfg *Func)
-      : ::Ice::X86Internal::TargetX86Base<TargetX8664>(Func) {}
+      : ::Ice::X8664::TargetX86Base<X8664::Traits>(Func) {}
 
   Operand *createNaClReadTPSrcOperand() {
     Variable *TDB = makeReg(IceType_i32);
@@ -111,6 +113,7 @@ private:
   explicit TargetHeaderX8664(GlobalContext *Ctx) : TargetHeaderLowering(Ctx) {}
 };
 
+} // end of namespace X8664
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664_H

src/IceTargetLoweringX8664Traits.h

@@ -31,19 +31,16 @@
 
 namespace Ice {
 
-class TargetX8664;
-
 namespace X8664 {
-class AssemblerX8664;
-} // end of namespace X8664
+using namespace ::Ice::X86;
 
-namespace X86Internal {
+template <class TraitsType> class AssemblerX86Base;
+template <class TraitsType> struct Insts;
+template <class TraitsType> class TargetX86Base;
 
-template <class Machine> struct Insts;
-template <class Machine> struct MachineTraits;
-template <class Machine> class TargetX86Base;
+class TargetX8664;
 
-template <> struct MachineTraits<TargetX8664> {
+struct TargetX8664Traits {
   //----------------------------------------------------------------------------
   //     ______  ______  __    __
   //    /\  __ \/\  ___\/\ "-./  \
@@ -52,6 +49,9 @@ template <> struct MachineTraits<TargetX8664> {
   //      \/_/\/_/\/_____/\/_/  \/_/
   //
   //----------------------------------------------------------------------------
+  static constexpr ::Ice::Assembler::AssemblerKind AsmKind =
+      ::Ice::Assembler::Asm_X8632;
+
   static constexpr bool Is64Bit = true;
   static constexpr bool HasPopa = false;
   static constexpr bool HasPusha = false;
@@ -191,7 +191,7 @@ template <> struct MachineTraits<TargetX8664> {
              (rm() == reg); // Register codes match.
     }
 
-    template <class> friend class AssemblerX86Base;
+    friend class AssemblerX86Base<TargetX8664Traits>;
   };
 
   class Address : public Operand {
@@ -801,10 +801,12 @@ public:
   //      \/_/\/_/ \/_/\/_____/  \/_/
   //
   //----------------------------------------------------------------------------
-  using Insts = ::Ice::X86Internal::Insts<TargetX8664>;
+  using Traits = TargetX8664Traits;
+  using Insts = ::Ice::X8664::Insts<Traits>;
 
-  using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8664>;
-  using Assembler = X8664::AssemblerX8664;
+  using TargetLowering = ::Ice::X8664::TargetX86Base<Traits>;
+  using ConcreteTarget = ::Ice::X8664::TargetX8664;
+  using Assembler = ::Ice::X8664::AssemblerX86Base<Traits>;
 
   /// X86Operand extends the Operand hierarchy. Its subclasses are X86OperandMem
   /// and VariableSplit.
@@ -972,10 +974,7 @@ public:
   } TypeAttributes[];
 };
 
-} // end of namespace X86Internal
-
-namespace X8664 {
-using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
+using Traits = ::Ice::X8664::TargetX8664Traits;
 } // end of namespace X8664
 
 } // end of namespace Ice

src/IceTargetLoweringX86RegClass.h

@@ -18,7 +18,7 @@
 #include "IceOperand.h" // RC_Target
 
 namespace Ice {
-namespace X86Internal {
+namespace X86 {
 
 // Extend enum RegClass with x86-specific register classes.
 enum RegClassX86 : uint8_t {
@@ -30,7 +30,7 @@ enum RegClassX86 : uint8_t {
   RCX86_NUM
 };
 
-} // end of namespace X86Internal
+} // end of namespace X86
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H

unittest/AssemblerX8632/TestUtil.h

@@ -15,6 +15,7 @@
 #define ASSEMBLERX8632_TESTUTIL_H_
 
 #include "IceAssemblerX8632.h"
+#include "IceDefs.h"
 
 #include "gtest/gtest.h"
 
@@ -31,14 +32,14 @@ protected:
   using Cond = AssemblerX8632::Traits::Cond;
   using GPRRegister = AssemblerX8632::Traits::GPRRegister;
   using ByteRegister = AssemblerX8632::Traits::ByteRegister;
-  using Label = ::Ice::X86Internal::Label;
+  using Label = ::Ice::X8632::Label;
   using Traits = AssemblerX8632::Traits;
   using XmmRegister = AssemblerX8632::Traits::XmmRegister;
   using X87STRegister = AssemblerX8632::Traits::X87STRegister;
 
   AssemblerX8632TestBase() { reset(); }
 
-  void reset() { Assembler.reset(new AssemblerX8632()); }
+  void reset() { Assembler = makeUnique<AssemblerX8632>(); }
 
   AssemblerX8632 *assembler() const { return Assembler.get(); }
 

unittest/AssemblerX8664/TestUtil.h

@@ -135,7 +135,7 @@ protected:
 
   AssemblerX8664TestBase() { reset(); }
 
-  void reset() { Assembler.reset(new AssemblerX8664()); }
+  void reset() { Assembler = makeUnique<AssemblerX8664>(); }
 
   AssemblerX8664 *assembler() const { return Assembler.get(); }