Commit 4c2153b1 by Karl Schimpf

emit add/sub registers instructions in integrated ARM assembler.

Also cleans up comments and condition violations for all implemented ARM instructions. BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1411873002 .
parent 659cc4f2
...@@ -158,6 +158,8 @@ class Operand : public ValueObject { ...@@ -158,6 +158,8 @@ class Operand : public ValueObject {
} }
#endif #endif
#if 0
// Moved to encodeShiftRotateImm5()
// Data-processing operands - Logical shift/rotate by immediate. // Data-processing operands - Logical shift/rotate by immediate.
Operand(Register rm, Shift shift, uint32_t shift_imm) { Operand(Register rm, Shift shift, uint32_t shift_imm) {
ASSERT(shift_imm < (1 << kShiftImmBits)); ASSERT(shift_imm < (1 << kShiftImmBits));
...@@ -166,6 +168,7 @@ class Operand : public ValueObject { ...@@ -166,6 +168,7 @@ class Operand : public ValueObject {
static_cast<uint32_t>(shift) << kShiftShift | static_cast<uint32_t>(shift) << kShiftShift |
static_cast<uint32_t>(rm); static_cast<uint32_t>(rm);
} }
#endif
// Data-processing operands - Logical shift/rotate by register. // Data-processing operands - Logical shift/rotate by register.
Operand(Register rm, Shift shift, Register rs) { Operand(Register rm, Shift shift, Register rs) {
......
; Show that we know how to translate add. ; Show that we know how to translate add.
; TODO(kschimpf) Currently only know how to test add 1 to R0.
; NOTE: We use -O2 to get rid of memory stores. ; NOTE: We use -O2 to get rid of memory stores.
...@@ -17,7 +16,7 @@ define internal i32 @add1ToR0(i32 %p) { ...@@ -17,7 +16,7 @@ define internal i32 @add1ToR0(i32 %p) {
; ASM-LABEL: add1ToR0: ; ASM-LABEL: add1ToR0:
; ASM: add r0, r0, #1 ; ASM: add r0, r0, #1
; ASM: bx lr ; ASM-NEXT: bx lr
; IASM-LABEL: add1ToR0: ; IASM-LABEL: add1ToR0:
; IASM: .byte 0x1 ; IASM: .byte 0x1
...@@ -25,3 +24,18 @@ define internal i32 @add1ToR0(i32 %p) { ...@@ -25,3 +24,18 @@ define internal i32 @add1ToR0(i32 %p) {
; IASM-NEXT: .byte 0x80 ; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0xe2 ; IASM-NEXT: .byte 0xe2
define internal i32 @Add2Regs(i32 %p1, i32 %p2) {
%v = add i32 %p1, %p2
ret i32 %v
}
; ASM-LABEL: Add2Regs:
; ASM: add r0, r0, r1
; ASM-NEXT: bx lr
; IASM-LABEL: Add2Regs:
; IASM: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0xe0
; Show that we know how to translate instruction sub. ; Show that we know how to translate instruction sub.
; TODO(kschimpf) Currently only know how to test subtract 1 from R0.
; NOTE: We use -O2 to get rid of memory stores. ; NOTE: We use -O2 to get rid of memory stores.
...@@ -25,3 +24,20 @@ define internal i32 @sub1FromR0(i32 %p) { ...@@ -25,3 +24,20 @@ define internal i32 @sub1FromR0(i32 %p) {
; IASM-NEXT: .byte 0x40 ; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0xe2 ; IASM-NEXT: .byte 0xe2
define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
%v = sub i32 %p1, %p2
ret i32 %v
}
; ASM-LABEL: Sub2Regs:
; ASM: sub r0, r0, r1
; ASM-NEXT: bx lr
; IASM-LABEL: Sub2Regs:
; IASM: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0xe0
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