Add vector VEOR instruction to the integrated ARM assembler.

src/DartARM32/assembler_arm.cc

@@ -1301,12 +1301,12 @@ void Assembler::vshlqu(OperandSize sz,
   EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
 }
 
-
+#if 0
+// Moved to ARM32::AssemblerARM32::veorq()
 void Assembler::veorq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
 }
 
-#if 0
 // Moved to ARM32::AssemblerARM32::vorrq()
 void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);

src/DartARM32/assembler_arm.h

@@ -716,9 +716,10 @@ class Assembler : public ValueObject {
   void vrsqrteqs(QRegister qd, QRegister qm);
   void vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm);
 
-  void veorq(QRegister qd, QRegister qn, QRegister qm);
 #if 0
   // Moved to ARM32::AssemblerARM32::vorrq()
+  void veorq(QRegister qd, QRegister qn, QRegister qm);
+  // Moved to ARM32::AssemblerARM32::vorrq()
   void vorrq(QRegister qd, QRegister qn, QRegister qm);
 #endif
   void vornq(QRegister qd, QRegister qn, QRegister qm);

src/IceAssemblerARM32.cpp

@@ -2471,6 +2471,13 @@ void AssemblerARM32::veord(const Operand *OpDd, const Operand *OpDn,
   emitInst(Encoding);
 }
 
+void AssemblerARM32::veorq(const Operand *OpQd, const Operand *OpQn,
+                           const Operand *OpQm) {
+  constexpr const char *Veorq = "veorq";
+  constexpr IValueT VeorqOpcode = B24 | B8 | B4;
+  emitSIMDqqq(VeorqOpcode, IceType_i8, OpQd, OpQn, OpQm, Veorq);
+}
+
 void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VLDR - ARM section A8.8.333, encoding A1.

src/IceAssemblerARM32.h

@@ -377,6 +377,8 @@ public:
 
   void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm);
 
+  void veorq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm);
+
   void vldrd(const Operand *OpDd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetInfo &TInfo);
 

src/IceInstARM32.cpp

@@ -680,8 +680,8 @@ template <> void InstARM32Veor::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   if (isVectorType(Dest->getType())) {
-    // TODO(kschimpf): Add support for this case
-    emitUsingTextFixup(Func);
+    Asm->veorq(Dest, getSrc(0), getSrc(1));
+    assert(!Asm->needsTextFixup());
     return;
   }
   assert(Dest->getType() == IceType_f64);

src/IceTargetLoweringARM32.cpp

@@ -2989,6 +2989,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
   }
   case InstArithmetic::Xor: {
     Variable *Src0R = Srcs.src0R(this);
+    assert(isIntegerType(DestTy));
     if (isVectorType(DestTy)) {
       Variable *Src1R = legalizeToReg(Src1);
       _veor(T, Src0R, Src1R);

tests_lit/assembler/arm32/xor-vec.ll

@@ -30,7 +30,7 @@ entry:
 
 ; ASM:     veor.i32        q0, q0, q1
 ; DIS:   0:       f3000152
-; IASM:     veor.i32
+; IASM-NOT:     veor.i32
 
   ret <4 x i32> %res
 }
@@ -45,7 +45,7 @@ entry:
 
 ; ASM:     veor.i16        q0, q0, q1
 ; DIS:   10:       f3000152
-; IASM:     veor.i16
+; IASM-NOT:     veor.i16
 
   ret <8 x i16> %res
 }
@@ -60,7 +60,7 @@ entry:
 
 ; ASM:     veor.i8        q0, q0, q1
 ; DIS:   20:       f3000152
-; IASM:     veor.i8
+; IASM-NOT:     veor.i8
 
   ret <16 x i8> %res
 }
@@ -79,7 +79,7 @@ entry:
 
 ; ASM:     veor.i32        q0, q0, q1
 ; DIS:   30:       f3000152
-; IASM:     veor.i32
+; IASM-NOT:     veor.i32
 
   ret <4 x i1> %res
 }
@@ -94,7 +94,7 @@ entry:
 
 ; ASM:     veor.i16        q0, q0, q1
 ; DIS:   40:       f3000152
-; IASM:     veor.i16
+; IASM-NOT:     veor.i16
 
   ret <8 x i1> %res
 }
@@ -109,7 +109,7 @@ entry:
 
 ; ASM:     veor.i8        q0, q0, q1
 ; DIS:   50:       f3000152
-; IASM:     veor.i8
+; IASM-NOT:     veor.i8
 
   ret <16 x i1> %res
 }