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Commit 62d367bd by Karl Schimpf
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Add EOR(register) and EOR(immediate) to ARM integrated assembler.

Also factor out code to process arguments for data operations into new method Arm32::Assembler32::emitType01(). BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1406153011 .
parent 9c08bee8
Showing with 259 additions and 200 deletions
src/DartARM32/assembler_arm.cc
......@@ -192,11 +192,12 @@ void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
}
#endif
#if 0
// Moved to ARM32::AssemberARM32::eor()
void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
}
#if 0
// Moved to ARM32::AssemberARM32::sub()
void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
......
src/DartARM32/assembler_arm.h
......@@ -444,9 +444,10 @@ class Assembler : public ValueObject {
void and_(Register rd, Register rn, Operand o, Condition cond = AL);
#endif
#if 0
// Moved to ARM32::AssemblerARM32::eor()
void eor(Register rd, Register rn, Operand o, Condition cond = AL);
#if 0
// Moved to ARM32::AssemberARM32::sub()
void sub(Register rd, Register rn, Operand o, Condition cond = AL);
void subs(Register rd, Register rn, Operand o, Condition cond = AL);
......
src/IceAssemblerARM32.cpp
......@@ -354,6 +354,51 @@ void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Type,
emitInst(Encoding);
}
void AssemblerARM32::emitType01(IValueT Opcode, const Operand *OpRd,
const Operand *OpRn, const Operand *OpSrc1,
bool SetFlags, CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of add.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// XXX (register)
// xxx{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
//
// cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Imm5 = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd,
Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// XXX (Immediate)
// xxx{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd,
Src1Value);
return;
}
}
}
void AssemblerARM32::emitType05(CondARM32::Cond Cond, IOffsetT Offset,
bool Link) {
// cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and
......@@ -411,137 +456,59 @@ void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
void AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
// ADC (register) - ARM section 18.8.2, encoding A1:
// adc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
//
// cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
//
// ADC (Immediate) - ARM section A8.8.1, encoding A1:
// adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
constexpr IValueT Adc = B2 | B0; // 0101
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of adc.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// ADC (register) - ARM section 18.8.2, encoding A1:
// adc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
//
// cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Imm5 = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, Adc, SetFlags, Rn, Rd, Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// ADC (Immediate) - ARM section A8.8.1, encoding A1:
// adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, Adc, SetFlags, Rn, Rd, Src1Value);
return;
}
};
emitType01(Adc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
void AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
// ADD (register) - ARM section A8.8.7, encoding A1:
// add{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
// ADD (Sp plus register) - ARM section A8.8.11, encoding A1:
// add{s}<c> sp, <Rn>, <Rm>{, <shiff>}
//
// cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
//
// ADD (Immediate) - ARM section A8.8.5, encoding A1:
// add{s}<c> <Rd>, <Rn>, #<RotatedImm8>
// ADD (SP plus immediate) - ARM section A8.8.9, encoding A1.
// add{s}<c> <Rd>, sp, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
constexpr IValueT Add = B2; // 0100
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of add.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// ADD (register) - ARM section A8.8.7, encoding A1:
// add{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
// ADD (Sp plus register) - ARM section A8.8.11, encoding A1:
// add{s}<c> sp, <Rn>, <Rm>{, <shiff>}
//
// cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Imm5 = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, Add, SetFlags, Rn, Rd, Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// ADD (Immediate) - ARM section A8.8.5, encoding A1:
// add{s}<c> <Rd>, <Rn>, #<RotatedImm8>
// ADD (SP plus immediate) - ARM section A8.8.9, encoding A1.
// add{s}<c> <Rd>, sp, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, Add, SetFlags, Rn, Rd, Src1Value);
return;
}
}
emitType01(Add, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
void AssemblerARM32::and_(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
// AND (register) - ARM section A8.8.14, encoding A1:
// and{s}<c> <Rd>, <Rn>{, <shift>}
//
// cccc0000000snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
//
// AND (Immediate) - ARM section A8.8.13, encoding A1:
// and{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
constexpr IValueT And = 0; // 0000
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of add.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// AND (register) - ARM section A8.8.14, encoding A1:
// and{s}<c> <Rd>, <Rn>{, <shift>}
//
// cccc0000000snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Imm5 = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, And, SetFlags, Rn, Rd, Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// AND (Immediate) - ARM section A8.8.13, encoding A1:
// and{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, And, SetFlags, Rn, Rd, Src1Value);
return;
}
}
emitType01(And, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
void AssemblerARM32::b(Label *L, CondARM32::Cond Cond) {
......@@ -573,6 +540,24 @@ void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
emitInst(Encoding);
}
void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
// EOR (register) - ARM section A*.8.47, encoding A1:
// eor{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
//
// cccc0000001snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
//
// EOR (Immediate) - ARM section A8.*.46, encoding A1:
// eor{s}<c> <Rd>, <Rn>, #RotatedImm8
//
// cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
constexpr IValueT Eor = B0; // 0001
emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
void AssemblerARM32::ldr(const Operand *OpRt, const Operand *OpAddress,
CondARM32::Cond Cond) {
IValueT Rt;
......@@ -691,45 +676,19 @@ void AssemblerARM32::movt(const Operand *OpRd, const Operand *OpSrc,
void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
// SBC (register) - ARM section 18.8.162, encoding A1:
// sbc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
//
// cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
//
// SBC (Immediate) - ARM section A8.8.161, encoding A1:
// sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
constexpr IValueT Sbc = B2 | B1; // 0110
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of sbc.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// SBC (register) - ARM section 18.8.162, encoding A1:
// sbc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
//
// cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Imm5 = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, Sbc, SetFlags, Rn, Rd, Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// SBC (Immediate) - ARM section A8.8.161, encoding A1:
// sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, Sbc, SetFlags, Rn, Rd, Src1Value);
return;
}
};
emitType01(Sbc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
......@@ -840,49 +799,23 @@ void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
// SUB (register) - ARM section A8.8.223, encoding A1:
// sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
// SUB (SP minus register): See ARM section 8.8.226, encoding A1:
// sub{s}<c> <Rd>, sp, <Rm>{, <Shift>}
//
// cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiiii=shift, tt=ShiftKind, and s=SetFlags.
//
// Sub (Immediate) - ARM section A8.8.222, encoding A1:
// sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
// Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
// sub{s}<c> sp, <Rn>, #<RotatedImm8>
//
// cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8
constexpr IValueT Sub = B1; // 0010
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of sub.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// SUB (register) - ARM section A8.8.223, encoding A1:
// sub{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
// SUB (SP minus register): See ARM section 8.8.226, encoding A1:
// sub{s}<c> <Rd>, sp, <Rm>{, <Shift>}
//
// cccc0000010snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiiii=shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Shift = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Shift);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, Sub, SetFlags, Rn, Rd, Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// Sub (Immediate) - ARM section A8.8.222, encoding A1:
// sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
// Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
// sub{s}<c> sp, <Rn>, #<RotatedImm8>
//
// cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
if (Rd == RegARM32::Encoded_Reg_pc)
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
return;
}
}
emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
} // end of namespace ARM32
......
src/IceAssemblerARM32.h
......@@ -150,6 +150,9 @@ public:
void bkpt(uint16_t Imm16);
void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
bool SetFlags, CondARM32::Cond Cond);
void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
......@@ -196,6 +199,11 @@ private:
void emitType01(CondARM32::Cond Cond, IValueT Type, IValueT Opcode,
bool SetCc, IValueT Rn, IValueT Rd, IValueT imm12);
// Converts arguments to appropriate representation on a data operation,
// and then calls emitType01 above.
void emitType01(IValueT Opcode, const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags, CondARM32::Cond Cond);
void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link);
// Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
......
src/IceInstARM32.cpp
......@@ -365,6 +365,13 @@ template <> void InstARM32And::emitIAS(const Cfg *Func) const {
emitUsingTextFixup(Func);
}
template <> void InstARM32Eor::emitIAS(const Cfg *Func) const {
ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
Asm->eor(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
if (Asm->needsTextFixup())
emitUsingTextFixup(Func);
}
template <> void InstARM32Orr::emitIAS(const Cfg *Func) const {
ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
Asm->orr(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
......
tests_lit/assembler/arm32/eor.ll 0 → 100644
; Show that we know how to translate eor.
; NOTE: We use -O2 to get rid of memory stores.
; REQUIRES: allow_dump
; Compile using standalone assembler.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
; RUN: | FileCheck %s --check-prefix=ASM
; Show bytes in assembled standalone code.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
; Compile using integrated assembler.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
; RUN: | FileCheck %s --check-prefix=IASM
; Show bytes in assembled integrated code.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
define internal i32 @Eor1WithR0(i32 %p) {
%v = xor i32 %p, 1
ret i32 %v
}
; ASM-LABEL:Eor1WithR0:
; ASM-NEXT:.LEor1WithR0$__0:
; ASM-NEXT: eor r0, r0, #1
; DIS-LABEL:00000000 <Eor1WithR0>:
; DIS-NEXT: 0: e2200001
; IASM-LABEL:Eor1WithR0:
; IASM-NEXT:.LEor1WithR0$__0:
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0xe2
define internal i32 @Eor2Regs(i32 %p1, i32 %p2) {
%v = xor i32 %p1, %p2
ret i32 %v
}
; ASM-LABEL:Eor2Regs:
; ASM-NEXT:.LEor2Regs$__0:
; ASM-NEXT: eor r0, r0, r1
; DIS-LABEL:00000010 <Eor2Regs>:
; DIS-NEXT: 10: e0200001
; IASM-LABEL:Eor2Regs:
; IASM-NEXT:.LEor2Regs$__0:
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0xe0
define internal i64 @EorI64WithR0R1(i64 %p) {
%v = xor i64 %p, 1
ret i64 %v
}
; ASM-LABEL:EorI64WithR0R1:
; ASM-NEXT:.LEorI64WithR0R1$__0:
; ASM-NEXT: eor r0, r0, #1
; ASM-NEXT: eor r1, r1, #0
; DIS-LABEL:00000020 <EorI64WithR0R1>:
; DIS-NEXT: 20: e2200001
; DIS-NEXT: 24: e2211000
; IASM-LABEL:EorI64WithR0R1:
; IASM-NEXT:.LEorI64WithR0R1$__0:
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0xe2
define internal i64 @EorI64Regs(i64 %p1, i64 %p2) {
%v = xor i64 %p1, %p2
ret i64 %v
}
; ASM-LABEL:EorI64Regs:
; ASM-NEXT:.LEorI64Regs$__0:
; ASM-NEXT: eor r0, r0, r2
; ASM-NEXT: eor r1, r1, r3
; DIS-LABEL:00000030 <EorI64Regs>:
; DIS-NEXT: 30: e0200002
; DIS-NEXT: 34: e0211003
; IASM-LABEL:EorI64Regs:
; IASM-NEXT:.LEorI64Regs$__0:
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0xe0
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