Add CLZ instruction to the ARM integrated assembler.

src/DartARM32/assembler_arm.cc

@@ -317,8 +317,8 @@ void Assembler::mvn(Register rd, Operand o, Condition cond) {
 void Assembler::mvns(Register rd, Operand o, Condition cond) {
   EmitType01(cond, o.type(), MVN, 1, R0, rd, o);
 }
-#endif
 
+// Moved to ARM32::AssemblerARM32::clz()
 void Assembler::clz(Register rd, Register rm, Condition cond) {
   ASSERT(rd != kNoRegister);
   ASSERT(rm != kNoRegister);
@@ -332,8 +332,6 @@ void Assembler::clz(Register rd, Register rm, Condition cond) {
   Emit(encoding);
 }
 
-
-#if 0
 // Moved to ARM32::AssemblerARM32::movw()
 void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
   ASSERT(cond != kNoCondition);

src/DartARM32/assembler_arm.h

@@ -513,13 +513,13 @@ class Assembler : public ValueObject {
   // Moved to ARM32::IceAssemblerARM32::mvn()
   void mvn(Register rd, Operand o, Condition cond = AL);
   void mvns(Register rd, Operand o, Condition cond = AL);
-#endif
 
   // Miscellaneous data-processing instructions.
+  // Moved to ARM32::AssemblerARM32::clz()
   void clz(Register rd, Register rm, Condition cond = AL);
 
   // Multiply instructions.
-#if 0
+
   // Moved to ARM32::AssemblerARM32::mul()
   void mul(Register rd, Register rn, Register rm, Condition cond = AL);
   void muls(Register rd, Register rn, Register rm, Condition cond = AL);

src/IceAssemblerARM32.cpp

@@ -1088,6 +1088,30 @@ void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   emitInst(Encoding);
 }
 
+void AssemblerARM32::clz(const Operand *OpRd, const Operand *OpSrc,
+                         CondARM32::Cond Cond) {
+  // CLZ - ARM section A8.8.33, encoding A1:
+  //   clz<c> <Rd> <Rm>
+  //
+  // cccc000101101111dddd11110001mmmm where cccc=Cond, dddd=Rd, and mmmm=Rm.
+  constexpr const char *ClzName = "clz";
+  constexpr const char *RdName = "Rd";
+  constexpr const char *RmName = "Rm";
+  IValueT Rd = encodeRegister(OpRd, RdName, ClzName);
+  verifyRegDefined(Rd, RdName, ClzName);
+  verifyRegNotPc(Rd, RdName, ClzName);
+  IValueT Rm = encodeRegister(OpSrc, RmName, ClzName);
+  verifyRegDefined(Rm, RmName, ClzName);
+  verifyRegNotPc(Rm, RmName, ClzName);
+  verifyCondDefined(Cond, ClzName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr IValueT PredefinedBits =
+      B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4;
+  const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) |
+                           (Rd << kRdShift) | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::cmn(const Operand *OpRn, const Operand *OpSrc1,
                          CondARM32::Cond Cond) {
   // CMN (immediate) - ARM section A8.8.34, encoding A1:

src/IceAssemblerARM32.h

@@ -205,6 +205,8 @@ public:
 
   void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
 
+  void clz(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+
   void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);

src/IceInstARM32.cpp

@@ -1250,6 +1250,14 @@ template <> void InstARM32Movt::emitIAS(const Cfg *Func) const {
     emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32Clz::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  Asm->clz(getDest(), getSrc(0), getPredicate());
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Mvn::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();

tests_lit/assembler/arm32/clz.ll

+; Show that we know how to translate clz.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+
+define internal i32 @testClz(i32 %a) {
+; ASM-LABEL:testClz:
+; DIS-LABEL:00000000 <testClz>:
+; IASM-LABEL:testClz:
+
+entry:
+; ASM-NEXT:.LtestClz$entry:
+; IASM-NEXT:.LtestClz$entry:
+
+; ASM-NEXT:     sub     sp, sp, #8
+; DIS-NEXT:   0:        e24dd008
+; IASM-NEXT:	.byte 0x8
+; IASM-NEXT:	.byte 0xd0
+; IASM-NEXT:	.byte 0x4d
+; IASM-NEXT:	.byte 0xe2
+
+; ASM-NEXT:     str     r0, [sp, #4]
+; ASM-NEXT:     # [sp, #4] = def.pseudo 
+; DIS-NEXT:   4:        e58d0004
+; IASM-NEXT:	.byte 0x4
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x8d
+; IASM-NEXT:	.byte 0xe5
+
+  %x = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
+
+; ASM-NEXT:     ldr     r0, [sp, #4]
+; DIS-NEXT:   8:        e59d0004
+; IASM-NEXT:	.byte 0x4
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x9d
+; IASM-NEXT:	.byte 0xe5
+
+; ASM-NEXT:     clz     r0, r0
+; DIS-NEXT:   c:        e16f0f10
+; IASM-NEXT:	.byte 0x10
+; IASM-NEXT:	.byte 0xf
+; IASM-NEXT:	.byte 0x6f
+; IASM-NEXT:	.byte 0xe1
+
+  ret i32 %x
+}