First patch for Mips subzero compiler

Makefile.standalone

@@ -187,6 +187,7 @@ SRCS = \
 	IceTargetLowering.cpp \
 	IceTargetLoweringARM32.cpp \
 	IceTargetLoweringX8632.cpp \
+	IceTargetLoweringMIPS32.cpp \
 	IceThreading.cpp \
 	IceTimerTree.cpp \
 	IceTranslator.cpp \

src/IceClFlags.cpp

@@ -136,7 +136,10 @@ cl::opt<Ice::TargetArch> TargetArch(
         clEnumValN(Ice::Target_X8664, "x86_64", "x86-64 (same as x8664)"),
         clEnumValN(Ice::Target_ARM32, "arm", "arm32"),
         clEnumValN(Ice::Target_ARM32, "arm32", "arm32 (same as arm)"),
-        clEnumValN(Ice::Target_ARM64, "arm64", "arm64"), clEnumValEnd));
+        clEnumValN(Ice::Target_ARM64, "arm64", "arm64"),
+        clEnumValN(Ice::Target_MIPS32, "mips", "mips32"),
+        clEnumValN(Ice::Target_MIPS32, "mips32", "mips32 (same as mips)"),
+        clEnumValEnd));
 cl::opt<Ice::TargetInstructionSet> TargetInstructionSet(
     "mattr", cl::desc("Target architecture attributes"),
     cl::init(Ice::X86InstructionSet_SSE2),

src/IceInstMIPS32.def

+//===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS32 insts --*- C++ -*-===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines properties of MIPS32 instructions in the form of x-macros.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICEINSTMIPS32_DEF
+#define SUBZERO_SRC_ICEINSTMIPS32_DEF
+
+// NOTE: PC and SP are not considered isInt, to avoid register allocating.
+// TODO (reed kotler). This needs to be scrubbed and is a placeholder to get
+// the Mips skeleton in.
+//
+#define REGMIPS32_GPR_TABLE                                                    \
+  /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \
+  X(Reg_ZERO,     = 0,          "zero",  0, 0, 0, 0, 0, 0)                     \
+  X(Reg_AT,       = Reg_ZERO + 1,   "at",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_V0,       = Reg_ZERO + 2,   "v0",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_V1,       = Reg_ZERO + 3,   "v1",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_A0,       = Reg_ZERO + 4,   "a0",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_A1,       = Reg_ZERO + 5,   "a1",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_A2,       = Reg_ZERO + 6,   "a2",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_A3,       = Reg_ZERO + 7,   "a3",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T0,       = Reg_ZERO + 8,   "t0",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T1,       = Reg_ZERO + 9,   "t1",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T2,       = Reg_ZERO + 10,  "t2",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T3,       = Reg_ZERO + 11,  "t3",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T4,       = Reg_ZERO + 12,  "t4",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T5,       = Reg_ZERO + 14,  "t5",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T6,       = Reg_ZERO + 14,  "t6",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T7,       = Reg_ZERO + 15,  "t7",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_S0,       = Reg_ZERO + 16,  "s0",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S1,       = Reg_ZERO + 17,  "s1",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S2,       = Reg_ZERO + 18,  "s2",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S3,       = Reg_ZERO + 19,  "s3",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S4,       = Reg_ZERO + 20,  "s4",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S5,       = Reg_ZERO + 21,  "s5",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S6,       = Reg_ZERO + 22,  "s6",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_S7,       = Reg_ZERO + 23,  "s7",    0, 1, 0, 0, 1, 0)                 \
+  X(Reg_T8,       = Reg_ZERO + 23,  "t8",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_T9,       = Reg_ZERO + 25,  "t9",    1, 0, 0, 0, 1, 0)                 \
+  X(Reg_K0,       = Reg_ZERO + 26,  "k0",    0, 0, 0, 0, 0, 0)                 \
+  X(Reg_K1,       = Reg_ZERO + 27,  "k1",    0, 0, 0, 0, 0, 0)                 \
+  X(Reg_GP,       = Reg_ZERO + 28,  "gp",    0, 0, 0, 0, 0, 0)                 \
+  X(Reg_SP,       = Reg_ZERO + 29,  "sp",    0, 0, 1, 0, 0, 0)                 \
+  X(Reg_FP,       = Reg_ZERO + 30,  "fp",    0, 0, 0, 1, 0, 0)                 \
+  X(Reg_RA,       = Reg_ZERO + 31,  "ra",    0, 1, 0, 0, 0, 0)                 \
+//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+//          isInt, isFP)
+
+// TODO(reed kotler): List FP registers etc.
+// Be able to grab even registers, and the corresponding odd register
+// for each even register.
+
+// We also provide a combined table, so that there is a namespace where
+// all of the registers are considered and have distinct numberings.
+// This is in contrast to the above, where the "encode" is based on how
+// the register numbers will be encoded in binaries and values can overlap.
+#define REGMIPS32_TABLE                                                  \
+  /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \
+  REGMIPS32_GPR_TABLE
+//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+//          isInt, isFP)
+
+#define REGMIPS32_TABLE_BOUNDS                                                 \
+  /* val, init */                                                              \
+  X(Reg_GPR_First, = Reg_ZERO)                                                 \
+  X(Reg_GPR_Last,  = Reg_RA)
+//define X(val, init)
+
+// TODO(reed kotler): add condition code tables, etc.
+
+
+#endif // SUBZERO_SRC_ICEINSTMIPS32_DEF

src/IceInstMIPS32.h

+//===- subzero/src/IceInstMIPS32.h - MIPS32 machine instrs --*- C++ -*-===    //
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the InstMIPS32 and OperandMIPS32 classes and
+// their subclasses.  This represents the machine instructions and
+// operands used for MIPS32 code selection.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICEINSTMIPS32_H
+#define SUBZERO_SRC_ICEINSTMIPS32_H
+
+#include "IceDefs.h"
+
+namespace Ice {
+
+class TargetMIPS32;
+// Fill this in.
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICEINSTMIPS32_H

src/IceRegistersMIPS32.h

+//===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the registers and their encodings for MIPS32.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICEREGISTERSMIPS32_H
+#define SUBZERO_SRC_ICEREGISTERSMIPS32_H
+
+#include "IceDefs.h"
+#include "IceInstMIPS32.def"
+#include "IceTypes.h"
+
+namespace Ice {
+
+namespace RegMIPS32 {
+
+// An enum of every register. The enum value may not match the encoding
+// used to binary encode register operands in instructions.
+enum AllRegisters {
+#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
+          isFP)                                                                \
+  val,
+  REGMIPS32_TABLE
+#undef X
+      Reg_NUM,
+#define X(val, init) val init,
+  REGMIPS32_TABLE_BOUNDS
+#undef X
+};
+
+// An enum of GPR Registers. The enum value does match the encoding used
+// to binary encode register operands in instructions.
+enum GPRRegister {
+#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
+          isFP)                                                                \
+  Encoded_##val encode,
+  REGMIPS32_GPR_TABLE
+#undef X
+      Encoded_Not_GPR = -1
+};
+
+// TODO(jvoung): Floating point and vector registers...
+// Need to model overlap and difference in encoding too.
+
+static inline GPRRegister getEncodedGPR(int32_t RegNum) {
+  assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last);
+  return GPRRegister(RegNum - Reg_GPR_First);
+}
+
+} // end of namespace RegMIPS32
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H

src/IceTargetLowering.cpp

@@ -17,12 +17,14 @@
 
 #include "IceAssemblerARM32.h"
 #include "IceAssemblerX8632.h"
+#include "assembler_mips32.h"
 #include "IceCfg.h" // setError()
 #include "IceCfgNode.h"
 #include "IceOperand.h"
 #include "IceRegAlloc.h"
 #include "IceTargetLowering.h"
 #include "IceTargetLoweringARM32.h"
+#include "IceTargetLoweringMIPS32.h"
 #include "IceTargetLoweringX8632.h"
 
 namespace Ice {

src/IceTargetLoweringMIPS32.def

+//===- subzero/src/IceTargetLoweringMIPS32.def -MIPS32 X-macros -*- C++ -*-===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines certain patterns for lowering to MIPS32 target
+// instructions, in the form of x-macros.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGMIPS32_DEF
+#define SUBZERO_SRC_ICETARGETLOWERINGMIPS32_DEF
+
+// TODO(reed kotler): Fill out comparison tables, etc. for 32/64-bit compares.
+
+#endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_DEF

src/IceTargetLoweringMIPS32.h

+//===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the TargetLoweringMIPS32 class, which implements the
+// TargetLowering interface for the MIPS 32-bit architecture.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
+#define SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H
+
+#include "IceDefs.h"
+#include "IceInstMIPS32.h"
+#include "IceRegistersMIPS32.h"
+#include "IceTargetLowering.h"
+
+namespace Ice {
+
+class TargetMIPS32 : public TargetLowering {
+  TargetMIPS32() = delete;
+  TargetMIPS32(const TargetMIPS32 &) = delete;
+  TargetMIPS32 &operator=(const TargetMIPS32 &) = delete;
+
+public:
+  // TODO(jvoung): return a unique_ptr.
+  static TargetMIPS32 *create(Cfg *Func) { return new TargetMIPS32(Func); }
+
+  void translateOm1() override;
+  void translateO2() override;
+  bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
+
+  SizeT getNumRegisters() const override { return RegMIPS32::Reg_NUM; }
+  Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
+  IceString getRegName(SizeT RegNum, Type Ty) const override;
+  llvm::SmallBitVector getRegisterSet(RegSetMask Include,
+                                      RegSetMask Exclude) const override;
+  const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
+    return TypeToRegisterSet[Ty];
+  }
+  bool hasFramePointer() const override { return UsesFramePointer; }
+  SizeT getFrameOrStackReg() const override {
+    return UsesFramePointer ? RegMIPS32::Reg_FP : RegMIPS32::Reg_SP;
+  }
+  size_t typeWidthInBytesOnStack(Type Ty) const override {
+    // Round up to the next multiple of 4 bytes.  In particular, i1,
+    // i8, and i16 are rounded up to 4 bytes.
+    return (typeWidthInBytes(Ty) + 3) & ~3;
+  }
+  void emitVariable(const Variable *Var) const override;
+
+  const char *getConstantPrefix() const final { return ""; }
+  void emit(const ConstantUndef *C) const final {
+    llvm::report_fatal_error("Not yet implemented");
+  }
+  void emit(const ConstantInteger32 *C) const final {
+    llvm::report_fatal_error("Not yet implemented");
+  }
+  void emit(const ConstantInteger64 *C) const final {
+    llvm::report_fatal_error("Not yet implemented");
+  }
+  void emit(const ConstantFloat *C) const final {
+    llvm::report_fatal_error("Not yet implemented");
+  }
+  void emit(const ConstantDouble *C) const final {
+    llvm::report_fatal_error("Not yet implemented");
+  }
+
+  void lowerArguments() override;
+  void addProlog(CfgNode *Node) override;
+  void addEpilog(CfgNode *Node) override;
+
+protected:
+  explicit TargetMIPS32(Cfg *Func);
+
+  void postLower() override;
+
+  void lowerAlloca(const InstAlloca *Inst) override;
+  void lowerArithmetic(const InstArithmetic *Inst) override;
+  void lowerAssign(const InstAssign *Inst) override;
+  void lowerBr(const InstBr *Inst) override;
+  void lowerCall(const InstCall *Inst) override;
+  void lowerCast(const InstCast *Inst) override;
+  void lowerExtractElement(const InstExtractElement *Inst) override;
+  void lowerFcmp(const InstFcmp *Inst) override;
+  void lowerIcmp(const InstIcmp *Inst) override;
+  void lowerIntrinsicCall(const InstIntrinsicCall *Inst) override;
+  void lowerInsertElement(const InstInsertElement *Inst) override;
+  void lowerLoad(const InstLoad *Inst) override;
+  void lowerPhi(const InstPhi *Inst) override;
+  void lowerRet(const InstRet *Inst) override;
+  void lowerSelect(const InstSelect *Inst) override;
+  void lowerStore(const InstStore *Inst) override;
+  void lowerSwitch(const InstSwitch *Inst) override;
+  void lowerUnreachable(const InstUnreachable *Inst) override;
+  void prelowerPhis() override;
+  void lowerPhiAssignments(CfgNode *Node,
+                           const AssignList &Assignments) override;
+  void doAddressOptLoad() override;
+  void doAddressOptStore() override;
+  void randomlyInsertNop(float Probability) override;
+  void makeRandomRegisterPermutation(
+      llvm::SmallVectorImpl<int32_t> &Permutation,
+      const llvm::SmallBitVector &ExcludeRegisters) const override;
+
+  static Type stackSlotType();
+
+  bool UsesFramePointer;
+  bool NeedsStackAlignment;
+  llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
+  llvm::SmallBitVector ScratchRegs;
+  llvm::SmallBitVector RegsUsed;
+  VarList PhysicalRegisters[IceType_NUM];
+  static IceString RegNames[];
+
+private:
+  ~TargetMIPS32() override {}
+};
+
+class TargetDataMIPS32 : public TargetDataLowering {
+  TargetDataMIPS32() = delete;
+  TargetDataMIPS32(const TargetDataMIPS32 &) = delete;
+  TargetDataMIPS32 &operator=(const TargetDataMIPS32 &) = delete;
+
+public:
+  static TargetDataLowering *create(GlobalContext *Ctx) {
+    return new TargetDataMIPS32(Ctx);
+  }
+
+  void lowerGlobals(std::unique_ptr<VariableDeclarationList> Vars) const final;
+  void lowerConstants() const final;
+
+protected:
+  explicit TargetDataMIPS32(GlobalContext *Ctx);
+
+private:
+  void lowerGlobal(const VariableDeclaration &Var) const;
+  ~TargetDataMIPS32() override {}
+  template <typename T> static void emitConstantPool(GlobalContext *Ctx);
+};
+
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H

src/IceTypes.def

@@ -26,6 +26,7 @@
   X(Target_X8664, "x86-64", true,  EM_X86_64,  0)                        \
   X(Target_ARM32, "arm32",  false, EM_ARM,     EF_ARM_EABI_VER5)         \
   X(Target_ARM64, "arm64",  true,  EM_AARCH64, 0)                        \
+  X(Target_MIPS32,"mips32", false, EM_MIPS,    0)                        \
   //#define X(tag, str, is_elf64, e_machine, e_flags)
 
 #define ICETYPE_TABLE                                                    \

src/assembler_mips32.h

+//===- subzero/src/assembler_mips.h - Assembler for MIPS --------*- C++ -*-===//
+//
+// Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
+// for details. All rights reserved. Use of this source code is governed by a
+// BSD-style license that can be found in the LICENSE file.
+//
+// Modified by the Subzero authors.
+//
+//===----------------------------------------------------------------------===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Assembler class for MIPS32.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ASSEMBLER_MIPS32_H
+#define SUBZERO_SRC_ASSEMBLER_MIPS32_H
+
+#include "IceAssembler.h"
+#include "IceDefs.h"
+#include "IceFixups.h"
+
+namespace Ice {
+namespace MIPS32 {
+
+class AssemblerMIPS32 : public Assembler {
+  AssemblerMIPS32(const AssemblerMIPS32 &) = delete;
+  AssemblerMIPS32 &operator=(const AssemblerMIPS32 &) = delete;
+
+public:
+  explicit AssemblerMIPS32(bool use_far_branches = false) : Assembler() {
+    // This mode is only needed and implemented for MIPS32 and ARM.
+    assert(!use_far_branches);
+    (void)use_far_branches;
+  }
+  ~AssemblerMIPS32() override = default;
+
+  void alignFunction() override {
+    llvm::report_fatal_error("Not yet implemented.");
+  }
+
+  SizeT getBundleAlignLog2Bytes() const override { return 4; }
+
+  const char *getNonExecPadDirective() const override { return ".TBD"; }
+
+  llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override {
+    llvm::report_fatal_error("Not yet implemented.");
+  }
+
+  void padWithNop(intptr_t Padding) override {
+    (void)Padding;
+    llvm::report_fatal_error("Not yet implemented.");
+  }
+
+  void bindCfgNodeLabel(SizeT NodeNumber) override {
+    (void)NodeNumber;
+    llvm::report_fatal_error("Not yet implemented.");
+  }
+
+  bool fixupIsPCRel(FixupKind Kind) const override {
+    (void)Kind;
+    llvm::report_fatal_error("Not yet implemented.");
+  }
+};
+
+} // end of namespace MIPS32
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ASSEMBLER_MIPS32_H