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swiftshader
Commit 7d0b8a3e by Nicolas Capens Committed by Nicolas Capens
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Compile only the target architecture LLVM backend.

Reactor is a run-time code generator so it only needs to support the CPU architecture for which it is being compiled. This reduces (static) compile time and potentially the binary size. Bug b/115344057 Change-Id: Id25dd986a888af5175d43c33e4c60bb3e4733eda Reviewed-on: https://swiftshader-review.googlesource.com/c/22128Tested-by: 's avatarNicolas Capens <nicolascapens@google.com> Reviewed-by: 's avatarAlexis Hétu <sugoi@google.com>
parent 2337f06c
Showing with 236 additions and 222 deletions
CMakeLists.txt
...@@ -1317,228 +1317,6 @@ set(LLVM_LIST ...@@ -1317,228 +1317,6 @@ set(LLVM_LIST
${LLVM_DIR}/lib/Target/TargetLoweringObjectFile.cpp ${LLVM_DIR}/lib/Target/TargetLoweringObjectFile.cpp
${LLVM_DIR}/lib/Target/TargetMachine.cpp ${LLVM_DIR}/lib/Target/TargetMachine.cpp
${LLVM_DIR}/lib/Target/TargetMachineC.cpp ${LLVM_DIR}/lib/Target/TargetMachineC.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ISelLowering.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64FastISel.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64InstrInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64PromoteConstant.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
${LLVM_DIR}/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64InstructionSelector.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64A53Fix835769.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64TargetMachine.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CallLowering.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64Subtarget.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64TargetObjectFile.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64RegisterInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
${LLVM_DIR}/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
${LLVM_DIR}/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
${LLVM_DIR}/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ConditionalCompares.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64LegalizerInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64StorePairSuppress.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
${LLVM_DIR}/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
${LLVM_DIR}/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64MCInstLower.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CollectLOH.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64AsmPrinter.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CondBrTuning.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64FrameLowering.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64MacroFusion.cpp
${LLVM_DIR}/lib/Target/ARM/ARMConstantIslandPass.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
${LLVM_DIR}/lib/Target/ARM/ThumbRegisterInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMMachineFunctionInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMFrameLowering.cpp
${LLVM_DIR}/lib/Target/ARM/ARMBaseRegisterInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMCallLowering.cpp
${LLVM_DIR}/lib/Target/ARM/ARMTargetMachine.cpp
${LLVM_DIR}/lib/Target/ARM/ARMBaseInstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb1FrameLowering.cpp
${LLVM_DIR}/lib/Target/ARM/ARMRegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/ARM/Utils/ARMBaseInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMComputeBlockSize.cpp
${LLVM_DIR}/lib/Target/ARM/ARMSelectionDAGInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMInstructionSelector.cpp
${LLVM_DIR}/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
${LLVM_DIR}/lib/Target/ARM/ARMTargetObjectFile.cpp
${LLVM_DIR}/lib/Target/ARM/ARMISelLowering.cpp
${LLVM_DIR}/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
${LLVM_DIR}/lib/Target/ARM/ARMExpandPseudoInsts.cpp
${LLVM_DIR}/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMInstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/MLxExpansionPass.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb2SizeReduction.cpp
${LLVM_DIR}/lib/Target/ARM/ARMConstantPoolValue.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb2InstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMRegisterInfo.cpp
${LLVM_DIR}/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
${LLVM_DIR}/lib/Target/ARM/ARMSubtarget.cpp
${LLVM_DIR}/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
${LLVM_DIR}/lib/Target/ARM/ARMParallelDSP.cpp
${LLVM_DIR}/lib/Target/ARM/ARMISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/ARM/A15SDOptimizer.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb2ITBlockPass.cpp
${LLVM_DIR}/lib/Target/ARM/ARMFastISel.cpp
${LLVM_DIR}/lib/Target/ARM/ARMMacroFusion.cpp
${LLVM_DIR}/lib/Target/ARM/ARMAsmPrinter.cpp
${LLVM_DIR}/lib/Target/ARM/ARMMCInstLower.cpp
${LLVM_DIR}/lib/Target/ARM/ARMHazardRecognizer.cpp
${LLVM_DIR}/lib/Target/ARM/ARMCodeGenPrepare.cpp
${LLVM_DIR}/lib/Target/ARM/ARMTargetTransformInfo.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb1InstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMLegalizerInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
${LLVM_DIR}/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
${LLVM_DIR}/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16FrameLowering.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16HardFloat.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16HardFloatInfo.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16InstrInfo.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16ISelLowering.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16RegisterInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsAnalyzeImmediate.cpp
${LLVM_DIR}/lib/Target/Mips/MipsAsmPrinter.cpp
${LLVM_DIR}/lib/Target/Mips/MipsCallLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsCCState.cpp
${LLVM_DIR}/lib/Target/Mips/MipsConstantIslandPass.cpp
${LLVM_DIR}/lib/Target/Mips/MipsDelaySlotFiller.cpp
${LLVM_DIR}/lib/Target/Mips/MipsExpandPseudo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsFastISel.cpp
${LLVM_DIR}/lib/Target/Mips/MipsInstrInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsInstructionSelector.cpp
${LLVM_DIR}/lib/Target/Mips/MipsISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/MipsISelLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsFrameLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsLegalizerInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsBranchExpansion.cpp
${LLVM_DIR}/lib/Target/Mips/MipsMCInstLower.cpp
${LLVM_DIR}/lib/Target/Mips/MipsMachineFunction.cpp
${LLVM_DIR}/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/MipsOptimizePICCall.cpp
${LLVM_DIR}/lib/Target/Mips/MipsOs16.cpp
${LLVM_DIR}/lib/Target/Mips/MipsRegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsRegisterInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEFrameLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEInstrInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEISelLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSERegisterInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSubtarget.cpp
${LLVM_DIR}/lib/Target/Mips/MipsTargetMachine.cpp
${LLVM_DIR}/lib/Target/Mips/MipsTargetObjectFile.cpp
${LLVM_DIR}/lib/Target/Mips/MicroMipsSizeReduction.cpp
${LLVM_DIR}/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
${LLVM_DIR}/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
${LLVM_DIR}/lib/Target/X86/AsmParser/X86AsmParser.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86InstComments.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp
${LLVM_DIR}/lib/Target/X86/ShadowCallStack.cpp
${LLVM_DIR}/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
${LLVM_DIR}/lib/Target/X86/Utils/X86ShuffleDecode.cpp
${LLVM_DIR}/lib/Target/X86/X86AsmPrinter.cpp
${LLVM_DIR}/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
${LLVM_DIR}/lib/Target/X86/X86CallFrameOptimization.cpp
${LLVM_DIR}/lib/Target/X86/X86CallLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86CallingConv.cpp
${LLVM_DIR}/lib/Target/X86/X86CmovConversion.cpp
${LLVM_DIR}/lib/Target/X86/X86DomainReassignment.cpp
${LLVM_DIR}/lib/Target/X86/X86EvexToVex.cpp
${LLVM_DIR}/lib/Target/X86/X86ExpandPseudo.cpp
${LLVM_DIR}/lib/Target/X86/X86FastISel.cpp
${LLVM_DIR}/lib/Target/X86/X86FixupBWInsts.cpp
${LLVM_DIR}/lib/Target/X86/X86FixupLEAs.cpp
${LLVM_DIR}/lib/Target/X86/X86FixupSetCC.cpp
${LLVM_DIR}/lib/Target/X86/X86FlagsCopyLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86FloatingPoint.cpp
${LLVM_DIR}/lib/Target/X86/X86FrameLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86ISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/X86/X86ISelLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86IndirectBranchTracking.cpp
${LLVM_DIR}/lib/Target/X86/X86InstrFMA3Info.cpp
${LLVM_DIR}/lib/Target/X86/X86InstrFoldTables.cpp
${LLVM_DIR}/lib/Target/X86/X86InstrInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86InstructionSelector.cpp
${LLVM_DIR}/lib/Target/X86/X86InterleavedAccess.cpp
${LLVM_DIR}/lib/Target/X86/X86LegalizerInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86MCInstLower.cpp
${LLVM_DIR}/lib/Target/X86/X86MachineFunctionInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86MacroFusion.cpp
${LLVM_DIR}/lib/Target/X86/X86OptimizeLEAs.cpp
${LLVM_DIR}/lib/Target/X86/X86PadShortFunction.cpp
${LLVM_DIR}/lib/Target/X86/X86RegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86RegisterInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86RetpolineThunks.cpp
${LLVM_DIR}/lib/Target/X86/X86SelectionDAGInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86ShuffleDecodeConstantPool.cpp
${LLVM_DIR}/lib/Target/X86/X86SpeculativeLoadHardening.cpp
${LLVM_DIR}/lib/Target/X86/X86Subtarget.cpp
${LLVM_DIR}/lib/Target/X86/X86TargetMachine.cpp
${LLVM_DIR}/lib/Target/X86/X86TargetObjectFile.cpp
${LLVM_DIR}/lib/Target/X86/X86TargetTransformInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86VZeroUpper.cpp
${LLVM_DIR}/lib/Target/X86/X86WinAllocaExpander.cpp
${LLVM_DIR}/lib/Target/X86/X86WinEHState.cpp
${LLVM_DIR}/lib/Transforms/InstCombine/InstCombineAddSub.cpp ${LLVM_DIR}/lib/Transforms/InstCombine/InstCombineAddSub.cpp
${LLVM_DIR}/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp ${LLVM_DIR}/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
${LLVM_DIR}/lib/Transforms/InstCombine/InstCombineCalls.cpp ${LLVM_DIR}/lib/Transforms/InstCombine/InstCombineCalls.cpp
...@@ -1681,6 +1459,242 @@ set(LLVM_LIST ...@@ -1681,6 +1459,242 @@ set(LLVM_LIST
${LLVM_DIR}/lib/Transforms/Utils/ValueMapper.cpp ${LLVM_DIR}/lib/Transforms/Utils/ValueMapper.cpp
) )
if(ARCH STREQUAL "x86" OR ARCH STREQUAL "x86_64")
list(APPEND LLVM_LIST
${LLVM_DIR}/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
${LLVM_DIR}/lib/Target/X86/AsmParser/X86AsmParser.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86InstComments.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp
${LLVM_DIR}/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp
${LLVM_DIR}/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp
${LLVM_DIR}/lib/Target/X86/ShadowCallStack.cpp
${LLVM_DIR}/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
${LLVM_DIR}/lib/Target/X86/Utils/X86ShuffleDecode.cpp
${LLVM_DIR}/lib/Target/X86/X86AsmPrinter.cpp
${LLVM_DIR}/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
${LLVM_DIR}/lib/Target/X86/X86CallFrameOptimization.cpp
${LLVM_DIR}/lib/Target/X86/X86CallLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86CallingConv.cpp
${LLVM_DIR}/lib/Target/X86/X86CmovConversion.cpp
${LLVM_DIR}/lib/Target/X86/X86DomainReassignment.cpp
${LLVM_DIR}/lib/Target/X86/X86EvexToVex.cpp
${LLVM_DIR}/lib/Target/X86/X86ExpandPseudo.cpp
${LLVM_DIR}/lib/Target/X86/X86FastISel.cpp
${LLVM_DIR}/lib/Target/X86/X86FixupBWInsts.cpp
${LLVM_DIR}/lib/Target/X86/X86FixupLEAs.cpp
${LLVM_DIR}/lib/Target/X86/X86FixupSetCC.cpp
${LLVM_DIR}/lib/Target/X86/X86FlagsCopyLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86FloatingPoint.cpp
${LLVM_DIR}/lib/Target/X86/X86FrameLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86ISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/X86/X86ISelLowering.cpp
${LLVM_DIR}/lib/Target/X86/X86IndirectBranchTracking.cpp
${LLVM_DIR}/lib/Target/X86/X86InstrFMA3Info.cpp
${LLVM_DIR}/lib/Target/X86/X86InstrFoldTables.cpp
${LLVM_DIR}/lib/Target/X86/X86InstrInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86InstructionSelector.cpp
${LLVM_DIR}/lib/Target/X86/X86InterleavedAccess.cpp
${LLVM_DIR}/lib/Target/X86/X86LegalizerInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86MCInstLower.cpp
${LLVM_DIR}/lib/Target/X86/X86MachineFunctionInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86MacroFusion.cpp
${LLVM_DIR}/lib/Target/X86/X86OptimizeLEAs.cpp
${LLVM_DIR}/lib/Target/X86/X86PadShortFunction.cpp
${LLVM_DIR}/lib/Target/X86/X86RegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86RegisterInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86RetpolineThunks.cpp
${LLVM_DIR}/lib/Target/X86/X86SelectionDAGInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86ShuffleDecodeConstantPool.cpp
${LLVM_DIR}/lib/Target/X86/X86SpeculativeLoadHardening.cpp
${LLVM_DIR}/lib/Target/X86/X86Subtarget.cpp
${LLVM_DIR}/lib/Target/X86/X86TargetMachine.cpp
${LLVM_DIR}/lib/Target/X86/X86TargetObjectFile.cpp
${LLVM_DIR}/lib/Target/X86/X86TargetTransformInfo.cpp
${LLVM_DIR}/lib/Target/X86/X86VZeroUpper.cpp
${LLVM_DIR}/lib/Target/X86/X86WinAllocaExpander.cpp
${LLVM_DIR}/lib/Target/X86/X86WinEHState.cpp
)
elseif(ARCH STREQUAL "mipsel" OR ARCH STREQUAL "mips64el")
list(APPEND LLVM_LIST
${LLVM_DIR}/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
${LLVM_DIR}/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
${LLVM_DIR}/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16FrameLowering.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16HardFloat.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16HardFloatInfo.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16InstrInfo.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16ISelLowering.cpp
${LLVM_DIR}/lib/Target/Mips/Mips16RegisterInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsAnalyzeImmediate.cpp
${LLVM_DIR}/lib/Target/Mips/MipsAsmPrinter.cpp
${LLVM_DIR}/lib/Target/Mips/MipsCallLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsCCState.cpp
${LLVM_DIR}/lib/Target/Mips/MipsConstantIslandPass.cpp
${LLVM_DIR}/lib/Target/Mips/MipsDelaySlotFiller.cpp
${LLVM_DIR}/lib/Target/Mips/MipsExpandPseudo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsFastISel.cpp
${LLVM_DIR}/lib/Target/Mips/MipsInstrInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsInstructionSelector.cpp
${LLVM_DIR}/lib/Target/Mips/MipsISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/MipsISelLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsFrameLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsLegalizerInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsBranchExpansion.cpp
${LLVM_DIR}/lib/Target/Mips/MipsMCInstLower.cpp
${LLVM_DIR}/lib/Target/Mips/MipsMachineFunction.cpp
${LLVM_DIR}/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/MipsOptimizePICCall.cpp
${LLVM_DIR}/lib/Target/Mips/MipsOs16.cpp
${LLVM_DIR}/lib/Target/Mips/MipsRegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsRegisterInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEFrameLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEInstrInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSEISelLowering.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSERegisterInfo.cpp
${LLVM_DIR}/lib/Target/Mips/MipsSubtarget.cpp
${LLVM_DIR}/lib/Target/Mips/MipsTargetMachine.cpp
${LLVM_DIR}/lib/Target/Mips/MipsTargetObjectFile.cpp
${LLVM_DIR}/lib/Target/Mips/MicroMipsSizeReduction.cpp
${LLVM_DIR}/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
)
elseif(ARCH STREQUAL "aarch64")
list(APPEND LLVM_LIST
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
${LLVM_DIR}/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ISelLowering.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64FastISel.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64InstrInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64PromoteConstant.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
${LLVM_DIR}/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64InstructionSelector.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64A53Fix835769.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64TargetMachine.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CallLowering.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64Subtarget.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64TargetObjectFile.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64RegisterInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
${LLVM_DIR}/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
${LLVM_DIR}/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
${LLVM_DIR}/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ConditionalCompares.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64LegalizerInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64StorePairSuppress.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
${LLVM_DIR}/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
${LLVM_DIR}/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64MCInstLower.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CollectLOH.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64AsmPrinter.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64CondBrTuning.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64FrameLowering.cpp
${LLVM_DIR}/lib/Target/AArch64/AArch64MacroFusion.cpp
)
elseif(ARCH STREQUAL "arm")
list(APPEND LLVM_LIST
${LLVM_DIR}/lib/Target/ARM/ARMConstantIslandPass.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
${LLVM_DIR}/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
${LLVM_DIR}/lib/Target/ARM/ThumbRegisterInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMMachineFunctionInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMFrameLowering.cpp
${LLVM_DIR}/lib/Target/ARM/ARMBaseRegisterInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMCallLowering.cpp
${LLVM_DIR}/lib/Target/ARM/ARMTargetMachine.cpp
${LLVM_DIR}/lib/Target/ARM/ARMBaseInstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb1FrameLowering.cpp
${LLVM_DIR}/lib/Target/ARM/ARMRegisterBankInfo.cpp
${LLVM_DIR}/lib/Target/ARM/Utils/ARMBaseInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMComputeBlockSize.cpp
${LLVM_DIR}/lib/Target/ARM/ARMSelectionDAGInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMInstructionSelector.cpp
${LLVM_DIR}/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
${LLVM_DIR}/lib/Target/ARM/ARMTargetObjectFile.cpp
${LLVM_DIR}/lib/Target/ARM/ARMISelLowering.cpp
${LLVM_DIR}/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
${LLVM_DIR}/lib/Target/ARM/ARMExpandPseudoInsts.cpp
${LLVM_DIR}/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMInstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/MLxExpansionPass.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb2SizeReduction.cpp
${LLVM_DIR}/lib/Target/ARM/ARMConstantPoolValue.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb2InstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMRegisterInfo.cpp
${LLVM_DIR}/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
${LLVM_DIR}/lib/Target/ARM/ARMSubtarget.cpp
${LLVM_DIR}/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
${LLVM_DIR}/lib/Target/ARM/ARMParallelDSP.cpp
${LLVM_DIR}/lib/Target/ARM/ARMISelDAGToDAG.cpp
${LLVM_DIR}/lib/Target/ARM/A15SDOptimizer.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb2ITBlockPass.cpp
${LLVM_DIR}/lib/Target/ARM/ARMFastISel.cpp
${LLVM_DIR}/lib/Target/ARM/ARMMacroFusion.cpp
${LLVM_DIR}/lib/Target/ARM/ARMAsmPrinter.cpp
${LLVM_DIR}/lib/Target/ARM/ARMMCInstLower.cpp
${LLVM_DIR}/lib/Target/ARM/ARMHazardRecognizer.cpp
${LLVM_DIR}/lib/Target/ARM/ARMCodeGenPrepare.cpp
${LLVM_DIR}/lib/Target/ARM/ARMTargetTransformInfo.cpp
${LLVM_DIR}/lib/Target/ARM/Thumb1InstrInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMLegalizerInfo.cpp
${LLVM_DIR}/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
)
endif()
set(LLVM_INCLUDE_DIR "") set(LLVM_INCLUDE_DIR "")
if(WIN32) if(WIN32)
......
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