Rename legalizeToVar to the more accurate legalizeToReg.

src/IceTargetLoweringARM32.cpp

@@ -1027,7 +1027,7 @@ void TargetARM32::lowerAlloca(const InstAlloca *Inst) {
 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi))
     return;
-  Variable *SrcLoReg = legalizeToVar(SrcLo);
+  Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm_unreachable("Unexpected type");
@@ -1066,7 +1066,7 @@ void TargetARM32::lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R,
                                DivInstr DivFunc, const char *DivHelperName,
                                bool IsRemainder) {
   div0Check(Dest->getType(), Src1, nullptr);
-  Variable *Src1R = legalizeToVar(Src1);
+  Variable *Src1R = legalizeToReg(Src1);
   Variable *T0R = Src0R;
   Variable *T1R = Src1R;
   if (Dest->getType() != IceType_i32) {
@@ -1163,8 +1163,8 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
     }
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
-    Variable *Src0RLo = legalizeToVar(loOperand(Src0));
-    Variable *Src0RHi = legalizeToVar(hiOperand(Src0));
+    Variable *Src0RLo = legalizeToReg(loOperand(Src0));
+    Variable *Src0RHi = legalizeToReg(hiOperand(Src0));
     Operand *Src1Lo = loOperand(Src1);
     Operand *Src1Hi = hiOperand(Src1);
     Variable *T_Lo = makeReg(DestLo->getType());
@@ -1236,8 +1236,8 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
       Variable *T_Acc = makeReg(IceType_i32);
       Variable *T_Acc1 = makeReg(IceType_i32);
       Variable *T_Hi1 = makeReg(IceType_i32);
-      Variable *Src1RLo = legalizeToVar(Src1Lo);
-      Variable *Src1RHi = legalizeToVar(Src1Hi);
+      Variable *Src1RLo = legalizeToReg(Src1Lo);
+      Variable *Src1RHi = legalizeToReg(Src1Hi);
       _mul(T_Acc, Src0RLo, Src1RHi);
       _mla(T_Acc1, Src1RLo, Src0RHi, T_Acc);
       _umull(T_Lo, T_Hi1, Src0RLo, Src1RLo);
@@ -1264,7 +1264,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
       // and saturate to the range 0-32, so the negative value will
       // saturate to 32.
       Variable *T_Hi = makeReg(IceType_i32);
-      Variable *Src1RLo = legalizeToVar(Src1Lo);
+      Variable *Src1RLo = legalizeToReg(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
       Variable *T_C2 = makeReg(IceType_i32);
@@ -1303,7 +1303,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
       // right shifts should also be arithmetic.
       bool IsAshr = Inst->getOp() == InstArithmetic::Ashr;
       Variable *T_Lo = makeReg(IceType_i32);
-      Variable *Src1RLo = legalizeToVar(Src1Lo);
+      Variable *Src1RLo = legalizeToReg(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
       Variable *T_C2 = makeReg(IceType_i32);
@@ -1353,7 +1353,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
     return;
   }
   // Dest->getType() is a non-i64 scalar.
-  Variable *Src0R = legalizeToVar(Src0);
+  Variable *Src0R = legalizeToReg(Src0);
   Variable *T = makeReg(Dest->getType());
   // Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
@@ -1413,7 +1413,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
     _mov(Dest, T);
     return;
   case InstArithmetic::Mul: {
-    Variable *Src1R = legalizeToVar(Src1RF);
+    Variable *Src1R = legalizeToReg(Src1RF);
     _mul(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
@@ -1502,7 +1502,7 @@ void TargetARM32::lowerBr(const InstBr *Inst) {
   Operand *Cond = Inst->getCondition();
   // TODO(jvoung): Handle folding opportunities.
 
-  Variable *Src0R = legalizeToVar(Cond);
+  Variable *Src0R = legalizeToReg(Cond);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0R, Zero);
   _br(Inst->getTargetTrue(), Inst->getTargetFalse(), CondARM32::NE);
@@ -1596,7 +1596,7 @@ void TargetARM32::lowerCall(const InstCall *Instr) {
 
   // Copy arguments to be passed in registers to the appropriate registers.
   for (auto &GPRArg : GPRArgs) {
-    Variable *Reg = legalizeToVar(GPRArg.first, GPRArg.second);
+    Variable *Reg = legalizeToReg(GPRArg.first, GPRArg.second);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
@@ -1722,11 +1722,11 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else if (Src0->getType() == IceType_i1) {
-        Variable *Src0R = legalizeToVar(Src0);
+        Variable *Src0R = legalizeToReg(Src0);
         _lsl(T_Lo, Src0R, ShiftAmt);
         _asr(T_Lo, T_Lo, ShiftAmt);
       } else {
-        Variable *Src0R = legalizeToVar(Src0);
+        Variable *Src0R = legalizeToReg(Src0);
         _sxt(T_Lo, Src0R);
       }
       _mov(DestLo, T_Lo);
@@ -1744,7 +1744,7 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
       // lsl t1, src_reg, 31
       // asr t1, t1, 31
       // dst = t1
-      Variable *Src0R = legalizeToVar(Src0);
+      Variable *Src0R = legalizeToReg(Src0);
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
       Variable *T = makeReg(Dest->getType());
       _lsl(T, Src0R, ShiftAmt);
@@ -1752,7 +1752,7 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
       _mov(Dest, T);
     } else {
       // t1 = sxt src; dst = t1
-      Variable *Src0R = legalizeToVar(Src0);
+      Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _sxt(T, Src0R);
       _mov(Dest, T);
@@ -1774,7 +1774,7 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else {
-        Variable *Src0R = legalizeToVar(Src0);
+        Variable *Src0R = legalizeToReg(Src0);
         _uxt(T_Lo, Src0R);
       }
       if (Src0->getType() == IceType_i1) {
@@ -1798,7 +1798,7 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
       _mov(Dest, T);
     } else {
       // t1 = uxt src; dst = t1
-      Variable *Src0R = legalizeToVar(Src0);
+      Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
@@ -1912,13 +1912,13 @@ void TargetARM32::lowerIcmp(const InstIcmp *Inst) {
     Variable *Src0Lo, *Src0Hi;
     Operand *Src1LoRF, *Src1HiRF;
     if (TableIcmp64[Index].Swapped) {
-      Src0Lo = legalizeToVar(loOperand(Src1));
-      Src0Hi = legalizeToVar(hiOperand(Src1));
+      Src0Lo = legalizeToReg(loOperand(Src1));
+      Src0Hi = legalizeToReg(hiOperand(Src1));
       Src1LoRF = legalize(loOperand(Src0), Legal_Reg | Legal_Flex);
       Src1HiRF = legalize(hiOperand(Src0), Legal_Reg | Legal_Flex);
     } else {
-      Src0Lo = legalizeToVar(loOperand(Src0));
-      Src0Hi = legalizeToVar(hiOperand(Src0));
+      Src0Lo = legalizeToReg(loOperand(Src0));
+      Src0Hi = legalizeToReg(hiOperand(Src0));
       Src1LoRF = legalize(loOperand(Src1), Legal_Reg | Legal_Flex);
       Src1HiRF = legalize(hiOperand(Src1), Legal_Reg | Legal_Flex);
     }
@@ -1977,13 +1977,13 @@ void TargetARM32::lowerIcmp(const InstIcmp *Inst) {
   if (ShiftAmt) {
     ShiftConst = Ctx->getConstantInt32(ShiftAmt);
     Src0R = makeReg(IceType_i32);
-    _lsl(Src0R, legalizeToVar(Src0), ShiftConst);
+    _lsl(Src0R, legalizeToReg(Src0), ShiftConst);
   } else {
-    Src0R = legalizeToVar(Src0);
+    Src0R = legalizeToReg(Src0);
   }
   _mov(T, Zero);
   if (ShiftAmt) {
-    Variable *Src1R = legalizeToVar(Src1);
+    Variable *Src1R = legalizeToReg(Src1);
     OperandARM32FlexReg *Src1RShifted = OperandARM32FlexReg::create(
         Func, IceType_i32, Src1R, OperandARM32::LSL, ShiftConst);
     _cmp(Src0R, Src1RShifted);
@@ -2037,8 +2037,8 @@ void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
     Type Ty = Val->getType();
     if (Ty == IceType_i64) {
       Val = legalizeUndef(Val);
-      Variable *Val_Lo = legalizeToVar(loOperand(Val));
-      Variable *Val_Hi = legalizeToVar(hiOperand(Val));
+      Variable *Val_Lo = legalizeToReg(loOperand(Val));
+      Variable *Val_Hi = legalizeToReg(hiOperand(Val));
       Variable *T_Lo = makeReg(IceType_i32);
       Variable *T_Hi = makeReg(IceType_i32);
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
@@ -2049,7 +2049,7 @@ void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
       _mov(DestHi, T_Lo);
     } else {
       assert(Ty == IceType_i32 || Ty == IceType_i16);
-      Variable *ValR = legalizeToVar(Val);
+      Variable *ValR = legalizeToReg(Val);
       Variable *T = makeReg(Ty);
       _rev(T, ValR);
       if (Val->getType() == IceType_i16) {
@@ -2090,10 +2090,10 @@ void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
     Variable *ValHiR = nullptr;
     if (Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
-      ValLoR = legalizeToVar(loOperand(Val));
-      ValHiR = legalizeToVar(hiOperand(Val));
+      ValLoR = legalizeToReg(loOperand(Val));
+      ValHiR = legalizeToReg(hiOperand(Val));
     } else {
-      ValLoR = legalizeToVar(Val);
+      ValLoR = legalizeToReg(Val);
     }
     lowerCLZ(Instr->getDest(), ValLoR, ValHiR);
     return;
@@ -2105,8 +2105,8 @@ void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
     Variable *ValHiR = nullptr;
     if (Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
-      ValLoR = legalizeToVar(loOperand(Val));
-      ValHiR = legalizeToVar(hiOperand(Val));
+      ValLoR = legalizeToReg(loOperand(Val));
+      ValHiR = legalizeToReg(hiOperand(Val));
       Variable *TLo = makeReg(IceType_i32);
       Variable *THi = makeReg(IceType_i32);
       _rbit(TLo, ValLoR);
@@ -2114,7 +2114,7 @@ void TargetARM32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
       ValLoR = THi;
       ValHiR = TLo;
     } else {
-      ValLoR = legalizeToVar(Val);
+      ValLoR = legalizeToReg(Val);
       Variable *T = makeReg(IceType_i32);
       _rbit(T, ValLoR);
       ValLoR = T;
@@ -2272,8 +2272,8 @@ void TargetARM32::lowerRet(const InstRet *Inst) {
     Operand *Src0 = Inst->getRetValue();
     if (Src0->getType() == IceType_i64) {
       Src0 = legalizeUndef(Src0);
-      Variable *R0 = legalizeToVar(loOperand(Src0), RegARM32::Reg_r0);
-      Variable *R1 = legalizeToVar(hiOperand(Src0), RegARM32::Reg_r1);
+      Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0);
+      Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1);
       Reg = R0;
       Context.insert(InstFakeUse::create(Func, R1));
     } else if (isScalarFloatingType(Src0->getType())) {
@@ -2317,7 +2317,7 @@ void TargetARM32::lowerSelect(const InstSelect *Inst) {
   }
   // TODO(jvoung): handle folding opportunities.
   // cmp cond, #0; mov t, SrcF; mov_cond t, SrcT; mov dest, t
-  Variable *CmpOpnd0 = legalizeToVar(Condition);
+  Variable *CmpOpnd0 = legalizeToReg(Condition);
   Operand *CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
   _cmp(CmpOpnd0, CmpOpnd1);
   CondARM32::Cond Cond = CondARM32::NE;
@@ -2358,14 +2358,14 @@ void TargetARM32::lowerStore(const InstStore *Inst) {
 
   if (Ty == IceType_i64) {
     Value = legalizeUndef(Value);
-    Variable *ValueHi = legalizeToVar(hiOperand(Value));
-    Variable *ValueLo = legalizeToVar(loOperand(Value));
+    Variable *ValueHi = legalizeToReg(hiOperand(Value));
+    Variable *ValueLo = legalizeToReg(loOperand(Value));
     _str(ValueHi, llvm::cast<OperandARM32Mem>(hiOperand(NewAddr)));
     _str(ValueLo, llvm::cast<OperandARM32Mem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     UnimplementedError(Func->getContext()->getFlags());
   } else {
-    Variable *ValueR = legalizeToVar(Value);
+    Variable *ValueR = legalizeToReg(Value);
     _str(ValueR, NewAddr);
   }
 }
@@ -2381,8 +2381,8 @@ void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   SizeT NumCases = Inst->getNumCases();
   if (Src0->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
-    Variable *Src0Lo = legalizeToVar(loOperand(Src0));
-    Variable *Src0Hi = legalizeToVar(hiOperand(Src0));
+    Variable *Src0Lo = legalizeToReg(loOperand(Src0));
+    Variable *Src0Hi = legalizeToReg(hiOperand(Src0));
     for (SizeT I = 0; I < NumCases; ++I) {
       Operand *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
       Operand *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
@@ -2397,7 +2397,7 @@ void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   }
 
   // 32 bit integer
-  Variable *Src0Var = legalizeToVar(Src0);
+  Variable *Src0Var = legalizeToReg(Src0);
   for (SizeT I = 0; I < NumCases; ++I) {
     Operand *Value = Ctx->getConstantInt32(Inst->getValue(I));
     Value = legalize(Value, Legal_Reg | Legal_Flex);
@@ -2465,10 +2465,10 @@ Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
-      RegBase = legalizeToVar(Base);
+      RegBase = legalizeToReg(Base);
     }
     if (Index) {
-      RegIndex = legalizeToVar(Index);
+      RegIndex = legalizeToReg(Index);
     }
     // Create a new operand if there was a change.
     if (Base != RegBase || Index != RegIndex) {
@@ -2583,7 +2583,7 @@ Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
-Variable *TargetARM32::legalizeToVar(Operand *From, int32_t RegNum) {
+Variable *TargetARM32::legalizeToReg(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
@@ -2620,7 +2620,7 @@ OperandARM32Mem *TargetARM32::formMemoryOperand(Operand *Operand, Type Ty) {
   // If we didn't do address mode optimization, then we only
   // have a base/offset to work with. ARM always requires a base
   // register, so just use that to hold the operand.
-  Variable *Base = legalizeToVar(Operand);
+  Variable *Base = legalizeToReg(Operand);
   return OperandARM32Mem::create(
       Func, Ty, Base,
       llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32)));

src/IceTargetLoweringARM32.h

@@ -149,7 +149,7 @@ protected:
   typedef uint32_t LegalMask;
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
-  Variable *legalizeToVar(Operand *From, int32_t RegNum = Variable::NoRegister);
+  Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
 
   Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);

src/IceTargetLoweringX86Base.h

@@ -246,7 +246,7 @@ protected:
   typedef uint32_t LegalMask;
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
-  Variable *legalizeToVar(Operand *From, int32_t RegNum = Variable::NoRegister);
+  Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   /// Legalize the first source operand for use in the cmp instruction.
   Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
   /// Turn a pointer operand into a memory operand that can be

src/IceTargetLoweringX86BaseImpl.h

@@ -1650,7 +1650,7 @@ void TargetX86Base<Machine>::lowerArithmetic(const InstArithmetic *Inst) {
     // TODO: Trap on integer divide and integer modulo by zero.
     // See: https://code.google.com/p/nativeclient/issues/detail?id=3899
     if (llvm::isa<typename Traits::X86OperandMem>(Src1))
-      Src1 = legalizeToVar(Src1);
+      Src1 = legalizeToReg(Src1);
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
@@ -1827,21 +1827,21 @@ void TargetX86Base<Machine>::lowerArithmetic(const InstArithmetic *Inst) {
   case InstArithmetic::Shl:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
+      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
     _shl(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Lshr:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
+      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
     _shr(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Ashr:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
+      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
     _sar(T, Src1);
     _mov(Dest, T);
     break;
@@ -2186,7 +2186,7 @@ void TargetX86Base<Machine>::lowerCall(const InstCall *Instr) {
   // before any stack adjustment is done.
   for (SizeT i = 0, NumXmmArgs = XmmArgs.size(); i < NumXmmArgs; ++i) {
     Variable *Reg =
-        legalizeToVar(XmmArgs[i], Traits::RegisterSet::Reg_xmm0 + i);
+        legalizeToReg(XmmArgs[i], Traits::RegisterSet::Reg_xmm0 + i);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
@@ -2483,7 +2483,7 @@ void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
              Inst->getSrc(0)->getType() == IceType_v4f32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Tps2dq);
       _movp(Dest, T);
@@ -2560,7 +2560,7 @@ void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
              Inst->getSrc(0)->getType() == IceType_v4i32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Dq2ps);
       _movp(Dest, T);
@@ -2775,7 +2775,7 @@ void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
     case IceType_v16i8:
     case IceType_v4i32:
     case IceType_v4f32: {
-      _movp(Dest, legalizeToVar(Src0));
+      _movp(Dest, legalizeToReg(Src0));
     } break;
     }
     break;
@@ -2804,7 +2804,7 @@ void TargetX86Base<Machine>::lowerExtractElement(
   if (CanUsePextr && Ty != IceType_v4f32) {
     // Use pextrb, pextrw, or pextrd.
     Constant *Mask = Ctx->getConstantInt32(Index);
-    Variable *SourceVectR = legalizeToVar(SourceVectNotLegalized);
+    Variable *SourceVectR = legalizeToReg(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
@@ -2816,7 +2816,7 @@ void TargetX86Base<Machine>::lowerExtractElement(
       T = makeReg(Ty);
       _pshufd(T, legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem), Mask);
     } else {
-      T = legalizeToVar(SourceVectNotLegalized);
+      T = legalizeToReg(SourceVectNotLegalized);
     }
 
     if (InVectorElementTy == IceType_i32) {
@@ -2838,7 +2838,7 @@ void TargetX86Base<Machine>::lowerExtractElement(
     // support for legalizing to mem is implemented.
     Variable *Slot = Func->template makeVariable(Ty);
     Slot->setWeight(RegWeight::Zero);
-    _movp(Slot, legalizeToVar(SourceVectNotLegalized));
+    _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the element in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
@@ -2889,7 +2889,7 @@ void TargetX86Base<Machine>::lowerFcmp(const InstFcmp *Inst) {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
 
       switch (Condition) {
       default: {
@@ -3038,13 +3038,13 @@ void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
       break;
     case InstIcmp::Eq: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpeq(T, Src1RM);
     } break;
     case InstIcmp::Ne: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpeq(T, Src1RM);
       Variable *MinusOne = makeVectorOfMinusOnes(Ty);
@@ -3053,7 +3053,7 @@ void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
     case InstIcmp::Ugt:
     case InstIcmp::Sgt: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpgt(T, Src1RM);
     } break;
@@ -3061,7 +3061,7 @@ void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
     case InstIcmp::Sge: {
       // !(Src1RM > Src0RM)
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       _movp(T, Src1RM);
       _pcmpgt(T, Src0RM);
       Variable *MinusOne = makeVectorOfMinusOnes(Ty);
@@ -3070,7 +3070,7 @@ void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
     case InstIcmp::Ult:
     case InstIcmp::Slt: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       _movp(T, Src1RM);
       _pcmpgt(T, Src0RM);
     } break;
@@ -3078,7 +3078,7 @@ void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
     case InstIcmp::Sle: {
       // !(Src0RM > Src1RM)
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpgt(T, Src1RM);
       Variable *MinusOne = makeVectorOfMinusOnes(Ty);
@@ -3173,7 +3173,7 @@ void TargetX86Base<Machine>::lowerInsertElement(const InstInsertElement *Inst) {
 
     if (InVectorElementTy == IceType_f32) {
       // ElementR will be in an XMM register since it is floating point.
-      ElementR = legalizeToVar(ElementToInsertNotLegalized);
+      ElementR = legalizeToReg(ElementToInsertNotLegalized);
     } else {
       // Copy an integer to an XMM register.
       Operand *T = legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
@@ -3237,13 +3237,13 @@ void TargetX86Base<Machine>::lowerInsertElement(const InstInsertElement *Inst) {
     // support for legalizing to mem is implemented.
     Variable *Slot = Func->template makeVariable(Ty);
     Slot->setWeight(RegWeight::Zero);
-    _movp(Slot, legalizeToVar(SourceVectNotLegalized));
+    _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
-    _store(legalizeToVar(ElementToInsertNotLegalized), Loc);
+    _store(legalizeToReg(ElementToInsertNotLegalized), Loc);
 
     Variable *T = makeReg(Ty);
     _movp(T, Slot);
@@ -3400,8 +3400,8 @@ void TargetX86Base<Machine>::lowerIntrinsicCall(
     // argument must be a register. Use rotate left for 16-bit bswap.
     if (Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
-      Variable *T_Lo = legalizeToVar(loOperand(Val));
-      Variable *T_Hi = legalizeToVar(hiOperand(Val));
+      Variable *T_Lo = legalizeToReg(loOperand(Val));
+      Variable *T_Hi = legalizeToReg(hiOperand(Val));
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _bswap(T_Lo);
@@ -3409,7 +3409,7 @@ void TargetX86Base<Machine>::lowerIntrinsicCall(
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else if (Val->getType() == IceType_i32) {
-      Variable *T = legalizeToVar(Val);
+      Variable *T = legalizeToReg(Val);
       _bswap(T);
       _mov(Dest, T);
     } else {
@@ -3487,9 +3487,9 @@ void TargetX86Base<Machine>::lowerIntrinsicCall(
     // Src is an f32 or f64, we need to make sure it's in a register.
     if (isVectorType(Ty)) {
       if (llvm::isa<typename Traits::X86OperandMem>(Src))
-        Src = legalizeToVar(Src);
+        Src = legalizeToReg(Src);
     } else {
-      Src = legalizeToVar(Src);
+      Src = legalizeToReg(Src);
     }
     _pand(T, Src);
     if (isVectorType(Ty))
@@ -3619,7 +3619,7 @@ void TargetX86Base<Machine>::lowerAtomicCmpxchg(Variable *DestPrev,
   _mov(T_eax, Expected);
   typename Traits::X86OperandMem *Addr =
       formMemoryOperand(Ptr, Expected->getType());
-  Variable *DesiredReg = legalizeToVar(Desired);
+  Variable *DesiredReg = legalizeToReg(Desired);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
@@ -3961,7 +3961,7 @@ void TargetX86Base<Machine>::lowerCountZeros(bool Cttz, Type Ty, Variable *Dest,
   Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
   Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   // Will be using "test" on this, so we need a registerized variable.
-  Variable *SecondVar = legalizeToVar(SecondVal);
+  Variable *SecondVar = legalizeToReg(SecondVal);
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
@@ -4273,15 +4273,15 @@ void TargetX86Base<Machine>::lowerRet(const InstRet *Inst) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
       Variable *eax =
-          legalizeToVar(loOperand(Src0), Traits::RegisterSet::Reg_eax);
+          legalizeToReg(loOperand(Src0), Traits::RegisterSet::Reg_eax);
       Variable *edx =
-          legalizeToVar(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
+          legalizeToReg(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (isScalarFloatingType(Src0->getType())) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
-      Reg = legalizeToVar(Src0, Traits::RegisterSet::Reg_xmm0);
+      Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0);
     } else {
       _mov(Reg, Src0, Traits::RegisterSet::Reg_eax);
     }
@@ -4461,7 +4461,7 @@ void TargetX86Base<Machine>::lowerStore(const InstStore *Inst) {
     _store(ValueLo,
            llvm::cast<typename Traits::X86OperandMem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
-    _storep(legalizeToVar(Value), NewAddr);
+    _storep(legalizeToReg(Value), NewAddr);
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
@@ -4542,7 +4542,7 @@ void TargetX86Base<Machine>::lowerCaseCluster(const CaseCluster &Case,
       Index = makeReg(getPointerType());
       _movzx(Index, RangeIndex);
     } else {
-      Index = legalizeToVar(RangeIndex);
+      Index = legalizeToReg(RangeIndex);
     }
 
     constexpr RelocOffsetT RelocOffset = 0;
@@ -4553,7 +4553,7 @@ void TargetX86Base<Machine>::lowerCaseCluster(const CaseCluster &Case,
     uint16_t Shift = typeWidthInBytesLog2(getPointerType());
     // TODO(ascull): remove need for legalize by allowing null base in memop
     auto *MemTarget = Traits::X86OperandMem::create(
-        Func, getPointerType(), legalizeToVar(Base), Offset, Index, Shift);
+        Func, getPointerType(), legalizeToReg(Base), Offset, Index, Shift);
     Variable *Target = nullptr;
     _mov(Target, MemTarget);
     _jmp(Target);
@@ -4597,8 +4597,8 @@ void TargetX86Base<Machine>::lowerSwitch(const InstSwitch *Inst) {
       Operand *Src0Lo = loOperand(Src0);
       Operand *Src0Hi = hiOperand(Src0);
       if (NumCases >= 2) {
-        Src0Lo = legalizeToVar(Src0Lo);
-        Src0Hi = legalizeToVar(Src0Hi);
+        Src0Lo = legalizeToReg(Src0Lo);
+        Src0Hi = legalizeToReg(Src0Hi);
       } else {
         Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
         Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
@@ -4620,7 +4620,7 @@ void TargetX86Base<Machine>::lowerSwitch(const InstSwitch *Inst) {
     // OK, we'll be slightly less naive by forcing Src into a physical
     // register if there are 2 or more uses.
     if (NumCases >= 2)
-      Src0 = legalizeToVar(Src0);
+      Src0 = legalizeToReg(Src0);
     else
       Src0 = legalize(Src0, Legal_Reg | Legal_Mem);
     for (SizeT I = 0; I < NumCases; ++I) {
@@ -4649,8 +4649,8 @@ void TargetX86Base<Machine>::lowerSwitch(const InstSwitch *Inst) {
       // This might be handled by a higher level lowering of switches.
       SizeT NumCases = Inst->getNumCases();
       if (NumCases >= 2) {
-        Src0Lo = legalizeToVar(Src0Lo);
-        Src0Hi = legalizeToVar(Src0Hi);
+        Src0Lo = legalizeToReg(Src0Lo);
+        Src0Hi = legalizeToReg(Src0Hi);
       } else {
         Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
         Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
@@ -4690,7 +4690,7 @@ void TargetX86Base<Machine>::lowerSwitch(const InstSwitch *Inst) {
   }
 
   // Going to be using multiple times so get it in a register early
-  Variable *Comparison = legalizeToVar(Src0);
+  Variable *Comparison = legalizeToReg(Src0);
 
   // A span is over the clusters
   struct SearchSpan {
@@ -4800,7 +4800,7 @@ void TargetX86Base<Machine>::eliminateNextVectorSextInstruction(
     if (NextCast->getCastKind() == InstCast::Sext &&
         NextCast->getSrc(0) == SignExtendedResult) {
       NextCast->setDeleted();
-      _movp(NextCast->getDest(), legalizeToVar(SignExtendedResult));
+      _movp(NextCast->getDest(), legalizeToReg(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
@@ -5198,10 +5198,10 @@ Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
-      RegBase = legalizeToVar(Base);
+      RegBase = legalizeToReg(Base);
     }
     if (Index) {
-      RegIndex = legalizeToVar(Index);
+      RegIndex = legalizeToReg(Index);
     }
     if (Base != RegBase || Index != RegIndex) {
       Mem = Traits::X86OperandMem::create(Func, Ty, RegBase, Mem->getOffset(),
@@ -5280,7 +5280,7 @@ Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
 
 /// Provide a trivial wrapper to legalize() for this common usage.
 template <class Machine>
-Variable *TargetX86Base<Machine>::legalizeToVar(Operand *From, int32_t RegNum) {
+Variable *TargetX86Base<Machine>::legalizeToReg(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }