Commit ac186fd7 by Karl Schimpf

Fix issues raised in CL 1645683003 by stichnot.

See CL https://codereview.chromium.org/1645683003 BUG=None R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1641753003 .
parent e1b6574f
...@@ -928,9 +928,7 @@ void Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) { ...@@ -928,9 +928,7 @@ void Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) { void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
} }
#endif
#if 0
// Moved to Arm32::AssemblerARM32::vmovs() // Moved to Arm32::AssemblerARM32::vmovs()
bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) { bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
if (TargetCPUFeatures::arm_version() != ARMv7) { if (TargetCPUFeatures::arm_version() != ARMv7) {
......
...@@ -2413,7 +2413,7 @@ void AssemblerARM32::vmovd(const Operand *OpDd, ...@@ -2413,7 +2413,7 @@ void AssemblerARM32::vmovd(const Operand *OpDd,
emitVFPddd(Cond, OpcodePlusImm8, Dd, D0, D0); emitVFPddd(Cond, OpcodePlusImm8, Dd, D0, D0);
} }
void AssemblerARM32::vmovdd(const Operand *OpDd, const Operand *OpDm, void AssemblerARM32::vmovdd(const Operand *OpDd, const Variable *OpDm,
CondARM32::Cond Cond) { CondARM32::Cond Cond) {
// VMOV (register) - ARM section A8.8.340, encoding A2: // VMOV (register) - ARM section A8.8.340, encoding A2:
// vmov<c>.f64 <Dd>, <Sm> // vmov<c>.f64 <Dd>, <Sm>
...@@ -2462,7 +2462,7 @@ void AssemblerARM32::vmovs(const Operand *OpSd, ...@@ -2462,7 +2462,7 @@ void AssemblerARM32::vmovs(const Operand *OpSd,
emitVFPsss(Cond, OpcodePlusImm8, Sd, S0, S0); emitVFPsss(Cond, OpcodePlusImm8, Sd, S0, S0);
} }
void AssemblerARM32::vmovss(const Operand *OpSd, const Operand *OpSm, void AssemblerARM32::vmovss(const Operand *OpSd, const Variable *OpSm,
CondARM32::Cond Cond) { CondARM32::Cond Cond) {
// VMOV (register) - ARM section A8.8.340, encoding A2: // VMOV (register) - ARM section A8.8.340, encoding A2:
// vmov<c>.f32 <Sd>, <Sm> // vmov<c>.f32 <Sd>, <Sm>
......
...@@ -385,14 +385,14 @@ public: ...@@ -385,14 +385,14 @@ public:
void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm, void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm,
CondARM32::Cond Cond); CondARM32::Cond Cond);
void vmovdd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond); void vmovdd(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond);
void vmovrs(const Operand *OpRt, const Operand *OpSn, CondARM32::Cond Cond); void vmovrs(const Operand *OpRt, const Operand *OpSn, CondARM32::Cond Cond);
void vmovs(const Operand *OpSn, const OperandARM32FlexFpImm *OpFpImm, void vmovs(const Operand *OpSn, const OperandARM32FlexFpImm *OpFpImm,
CondARM32::Cond Cond); CondARM32::Cond Cond);
void vmovss(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond); void vmovss(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond);
void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond); void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond);
......
...@@ -1073,7 +1073,7 @@ void InstARM32Mov::emitMultiDestSingleSource(const Cfg *Func) const { ...@@ -1073,7 +1073,7 @@ void InstARM32Mov::emitMultiDestSingleSource(const Cfg *Func) const {
assert(DestHi->hasReg()); assert(DestHi->hasReg());
assert(DestLo->hasReg()); assert(DestLo->hasReg());
assert(llvm::isa<Variable>(Src) && Src->hasReg()); assert(Src->hasReg());
Str << "\t" Str << "\t"
"vmov" << getPredicate() << "\t"; "vmov" << getPredicate() << "\t";
...@@ -1173,8 +1173,8 @@ void InstARM32Mov::emitIASScalarVFPMove(const Cfg *Func) const { ...@@ -1173,8 +1173,8 @@ void InstARM32Mov::emitIASScalarVFPMove(const Cfg *Func) const {
assert(false && "Do not know how to emit scalar FP move for type."); assert(false && "Do not know how to emit scalar FP move for type.");
break; break;
case IceType_f32: case IceType_f32:
if (llvm::isa<Variable>(Src0)) { if (const auto *Var = llvm::dyn_cast<Variable>(Src0)) {
Asm->vmovss(Dest, Src0, getPredicate()); Asm->vmovss(Dest, Var, getPredicate());
return; return;
} else if (const auto *FpImm = } else if (const auto *FpImm =
llvm::dyn_cast<OperandARM32FlexFpImm>(Src0)) { llvm::dyn_cast<OperandARM32FlexFpImm>(Src0)) {
...@@ -1184,8 +1184,8 @@ void InstARM32Mov::emitIASScalarVFPMove(const Cfg *Func) const { ...@@ -1184,8 +1184,8 @@ void InstARM32Mov::emitIASScalarVFPMove(const Cfg *Func) const {
assert(!Asm->needsTextFixup()); assert(!Asm->needsTextFixup());
return; return;
case IceType_f64: case IceType_f64:
if (llvm::isa<Variable>(Src0)) { if (const auto *Var = llvm::dyn_cast<Variable>(Src0)) {
Asm->vmovdd(Dest, Src0, getPredicate()); Asm->vmovdd(Dest, Var, getPredicate());
return; return;
} else if (const auto *FpImm = } else if (const auto *FpImm =
llvm::dyn_cast<OperandARM32FlexFpImm>(Src0)) { llvm::dyn_cast<OperandARM32FlexFpImm>(Src0)) {
......
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