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Commit afe5fe22 by Stefan Maksimovic Committed by Jim Stichnoth
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Subzero, MIPS32: Fix conditional mov instructions

This patch implements changes needed for conditional mov instructions to fix problem with failing crosstest and invalid register allocation. Problem is visible from icmp test examples, causing cross test for icmp to fail. Eg: Incorrect, before this change: 674: 00653026 xor a2,v1,a1 678: 00a3182b sltu v1,a1,v1 67c: 0082102b sltu v0,a0,v0 680: 0043180a movz v1,v0,v0 Correct, aftrer this change: 674: 00653026 xor a2,v1,a1 678: 00a3182b sltu v1,a1,v1 67c: 0082102b sltu v0,a0,v0 680: 0046180a movz v1,v0,a2 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2394773004 . Patch from Stefan Maksimovic <makdstefan@gmail.com>.
parent 033dda7e
Showing with 180 additions and 182 deletions
src/IceInstMIPS32.cpp
...@@ -971,7 +971,7 @@ template <> void InstMIPS32Mov_s::emitIAS(const Cfg *Func) const { ...@@ -971,7 +971,7 @@ template <> void InstMIPS32Mov_s::emitIAS(const Cfg *Func) const {
template <> void InstMIPS32Movf::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movf::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->movf(getDest(), getSrc(1), getSrc(2)); Asm->movf(getDest(), getSrc(0), getSrc(1));
} }
template <> void InstMIPS32Movn::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movn::emitIAS(const Cfg *Func) const {
...@@ -991,7 +991,7 @@ template <> void InstMIPS32Movn_s::emitIAS(const Cfg *Func) const { ...@@ -991,7 +991,7 @@ template <> void InstMIPS32Movn_s::emitIAS(const Cfg *Func) const {
template <> void InstMIPS32Movt::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movt::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->movt(getDest(), getSrc(1), getSrc(2)); Asm->movt(getDest(), getSrc(0), getSrc(1));
} }
template <> void InstMIPS32Movz::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movz::emitIAS(const Cfg *Func) const {
......
src/IceInstMIPS32.h
...@@ -1065,13 +1065,13 @@ public: ...@@ -1065,13 +1065,13 @@ public:
if (!BuildDefs::dump()) if (!BuildDefs::dump())
return; return;
Ostream &Str = Func->getContext()->getStrEmit(); Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 3); assert(getSrcSize() == 2);
Str << "\t" << Opcode << "\t"; Str << "\t" << Opcode << "\t";
getDest()->emit(Func); getDest()->emit(Func);
Str << ", "; Str << ", ";
getSrc(1)->emit(Func); getSrc(0)->emit(Func);
Str << ", "; Str << ", ";
getSrc(2)->emit(Func); getSrc(1)->emit(Func);
} }
void emitIAS(const Cfg *Func) const override { void emitIAS(const Cfg *Func) const override {
...@@ -1094,8 +1094,7 @@ public: ...@@ -1094,8 +1094,7 @@ public:
private: private:
InstMIPS32MovConditional(Cfg *Func, Variable *Dest, Variable *Src, InstMIPS32MovConditional(Cfg *Func, Variable *Dest, Variable *Src,
Operand *FCC) Operand *FCC)
: InstMIPS32(Func, K, 3, Dest) { : InstMIPS32(Func, K, 2, Dest) {
addSource(Dest);
addSource(Src); addSource(Src);
addSource(FCC); addSource(FCC);
} }
...@@ -1148,11 +1147,11 @@ using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>; ...@@ -1148,11 +1147,11 @@ using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>;
using InstMIPS32Mov_d = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_d>; using InstMIPS32Mov_d = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_d>;
using InstMIPS32Mov_s = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_s>; using InstMIPS32Mov_s = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_s>;
using InstMIPS32Movf = InstMIPS32MovConditional<InstMIPS32::Movf>; using InstMIPS32Movf = InstMIPS32MovConditional<InstMIPS32::Movf>;
using InstMIPS32Movn = InstMIPS32MovConditional<InstMIPS32::Movn>; using InstMIPS32Movn = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn>;
using InstMIPS32Movn_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_d>; using InstMIPS32Movn_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_d>;
using InstMIPS32Movn_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_s>; using InstMIPS32Movn_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movn_s>;
using InstMIPS32Movt = InstMIPS32MovConditional<InstMIPS32::Movt>; using InstMIPS32Movt = InstMIPS32MovConditional<InstMIPS32::Movt>;
using InstMIPS32Movz = InstMIPS32MovConditional<InstMIPS32::Movz>; using InstMIPS32Movz = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz>;
using InstMIPS32Movz_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz_d>; using InstMIPS32Movz_d = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz_d>;
using InstMIPS32Movz_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz_s>; using InstMIPS32Movz_s = InstMIPS32ThreeAddrGPR<InstMIPS32::Movz_s>;
using InstMIPS32Mtc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mtc1>; using InstMIPS32Mtc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mtc1>;
......
src/IceTargetLoweringMIPS32.h
...@@ -365,38 +365,36 @@ public: ...@@ -365,38 +365,36 @@ public:
Context.insert<InstMIPS32Mov_s>(Dest, Src); Context.insert<InstMIPS32Mov_s>(Dest, Src);
} }
void _movf(Variable *Src0, Variable *Src1, Operand *FCC) { void _movf(Variable *Dest, Variable *Src0, Operand *FCC) {
auto *Instr = Context.insert<InstMIPS32Movf>(Src0, Src1, FCC); Context.insert<InstMIPS32Movf>(Dest, Src0, FCC)->setDestRedefined();
Instr->setDestRedefined();
} }
void _movn(Variable *Dest, Variable *Src0, Variable *Src1) { void _movn(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Movn>(Dest, Src0, Src1); Context.insert<InstMIPS32Movn>(Dest, Src0, Src1)->setDestRedefined();
} }
void _movn_d(Variable *Dest, Variable *Src0, Variable *Src1) { void _movn_d(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Movn_d>(Dest, Src0, Src1); Context.insert<InstMIPS32Movn_d>(Dest, Src0, Src1)->setDestRedefined();
} }
void _movn_s(Variable *Dest, Variable *Src0, Variable *Src1) { void _movn_s(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Movn_s>(Dest, Src0, Src1); Context.insert<InstMIPS32Movn_s>(Dest, Src0, Src1)->setDestRedefined();
} }
void _movt(Variable *Src0, Variable *Src1, Operand *FCC) { void _movt(Variable *Dest, Variable *Src0, Operand *FCC) {
auto *Instr = Context.insert<InstMIPS32Movt>(Src0, Src1, FCC); Context.insert<InstMIPS32Movt>(Dest, Src0, FCC)->setDestRedefined();
Instr->setDestRedefined();
} }
void _movz(Variable *Dest, Variable *Src0, Variable *Src1) { void _movz(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Movz>(Dest, Src0, Src1); Context.insert<InstMIPS32Movz>(Dest, Src0, Src1)->setDestRedefined();
} }
void _movz_d(Variable *Dest, Variable *Src0, Variable *Src1) { void _movz_d(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Movz_d>(Dest, Src0, Src1); Context.insert<InstMIPS32Movz_d>(Dest, Src0, Src1)->setDestRedefined();
} }
void _movz_s(Variable *Dest, Variable *Src0, Variable *Src1) { void _movz_s(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Movz_s>(Dest, Src0, Src1); Context.insert<InstMIPS32Movz_s>(Dest, Src0, Src1)->setDestRedefined();
} }
void _mtc1(Variable *Dest, Variable *Src) { void _mtc1(Variable *Dest, Variable *Src) {
......
tests_lit/assembler/mips32/encoding_intrinsics.ll
...@@ -50,15 +50,15 @@ entry: ...@@ -50,15 +50,15 @@ entry:
; ASM-NEXT: andi $v0, $v0, 65535 ; ASM-NEXT: andi $v0, $v0, 65535
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap16>: ; DIS-LABEL: <encBswap16>:
; DIS-NEXT: {{.*}} 00041200 sll v0,a0,0x8 ; DIS-NEXT: 00041200 sll v0,a0,0x8
; DIS-NEXT: {{.*}} 3c0300ff lui v1,0xff ; DIS-NEXT: 3c0300ff lui v1,0xff
; DIS-NEXT: {{.*}} 00431024 and v0,v0,v1 ; DIS-NEXT: 00431024 and v0,v0,v1
; DIS-NEXT: {{.*}} 00042600 sll a0,a0,0x18 ; DIS-NEXT: 00042600 sll a0,a0,0x18
; DIS-NEXT: {{.*}} 00821025 or v0,a0,v0 ; DIS-NEXT: 00821025 or v0,a0,v0
; DIS-NEXT: {{.*}} 00021402 srl v0,v0,0x10 ; DIS-NEXT: 00021402 srl v0,v0,0x10
; DIS-NEXT: {{.*}} 3042ffff andi v0,v0,0xffff ; DIS-NEXT: 3042ffff andi v0,v0,0xffff
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encBswap16 ; IASM-LABEL: encBswap16
; IASM-NEXT: .LencBswap16$entry: ; IASM-NEXT: .LencBswap16$entry:
...@@ -116,19 +116,19 @@ entry: ...@@ -116,19 +116,19 @@ entry:
; ASM-NEXT: move $v0, $v1 ; ASM-NEXT: move $v0, $v1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap32>: ; DIS-LABEL: <encBswap32>:
; DIS-NEXT: {{.*}} 00041602 srl v0,a0,0x18 ; DIS-NEXT: 00041602 srl v0,a0,0x18
; DIS-NEXT: {{.*}} 00041a02 srl v1,a0,0x8 ; DIS-NEXT: 00041a02 srl v1,a0,0x8
; DIS-NEXT: {{.*}} 3063ff00 andi v1,v1,0xff00 ; DIS-NEXT: 3063ff00 andi v1,v1,0xff00
; DIS-NEXT: {{.*}} 00621025 or v0,v1,v0 ; DIS-NEXT: 00621025 or v0,v1,v0
; DIS-NEXT: {{.*}} 00041a00 sll v1,a0,0x8 ; DIS-NEXT: 00041a00 sll v1,a0,0x8
; DIS-NEXT: {{.*}} 3c0500ff lui a1,0xff ; DIS-NEXT: 3c0500ff lui a1,0xff
; DIS-NEXT: {{.*}} 00651824 and v1,v1,a1 ; DIS-NEXT: 00651824 and v1,v1,a1
; DIS-NEXT: {{.*}} 00042600 sll a0,a0,0x18 ; DIS-NEXT: 00042600 sll a0,a0,0x18
; DIS-NEXT: {{.*}} 00831825 or v1,a0,v1 ; DIS-NEXT: 00831825 or v1,a0,v1
; DIS-NEXT: {{.*}} 00621825 or v1,v1,v0 ; DIS-NEXT: 00621825 or v1,v1,v0
; DIS-NEXT: {{.*}} 00601021 move v0,v1 ; DIS-NEXT: 00601021 move v0,v1
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encBswap32 ; IASM-LABEL: encBswap32
; IASM-NEXT: .LencBswap32$entry: ; IASM-NEXT: .LencBswap32$entry:
...@@ -212,29 +212,29 @@ entry: ...@@ -212,29 +212,29 @@ entry:
; ASM-NEXT: move $v1, $a0 ; ASM-NEXT: move $v1, $a0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap64>: ; DIS-LABEL: <encBswap64>:
; DIS-NEXT: {{.*}} 00051200 sll v0,a1,0x8 ; DIS-NEXT: 00051200 sll v0,a1,0x8
; DIS-NEXT: {{.*}} 00051e02 srl v1,a1,0x18 ; DIS-NEXT: 00051e02 srl v1,a1,0x18
; DIS-NEXT: {{.*}} 00053202 srl a2,a1,0x8 ; DIS-NEXT: 00053202 srl a2,a1,0x8
; DIS-NEXT: {{.*}} 30c6ff00 andi a2,a2,0xff00 ; DIS-NEXT: 30c6ff00 andi a2,a2,0xff00
; DIS-NEXT: {{.*}} 3c0700ff lui a3,0xff ; DIS-NEXT: 3c0700ff lui a3,0xff
; DIS-NEXT: {{.*}} 00c33025 or a2,a2,v1 ; DIS-NEXT: 00c33025 or a2,a2,v1
; DIS-NEXT: {{.*}} 00471024 and v0,v0,a3 ; DIS-NEXT: 00471024 and v0,v0,a3
; DIS-NEXT: {{.*}} 00052e00 sll a1,a1,0x18 ; DIS-NEXT: 00052e00 sll a1,a1,0x18
; DIS-NEXT: {{.*}} 00a22825 or a1,a1,v0 ; DIS-NEXT: 00a22825 or a1,a1,v0
; DIS-NEXT: {{.*}} 00041602 srl v0,a0,0x18 ; DIS-NEXT: 00041602 srl v0,a0,0x18
; DIS-NEXT: {{.*}} 00041a02 srl v1,a0,0x8 ; DIS-NEXT: 00041a02 srl v1,a0,0x8
; DIS-NEXT: {{.*}} 3063ff00 andi v1,v1,0xff00 ; DIS-NEXT: 3063ff00 andi v1,v1,0xff00
; DIS-NEXT: {{.*}} 00a62825 or a1,a1,a2 ; DIS-NEXT: 00a62825 or a1,a1,a2
; DIS-NEXT: {{.*}} 00621825 or v1,v1,v0 ; DIS-NEXT: 00621825 or v1,v1,v0
; DIS-NEXT: {{.*}} 00041200 sll v0,a0,0x8 ; DIS-NEXT: 00041200 sll v0,a0,0x8
; DIS-NEXT: {{.*}} 00471024 and v0,v0,a3 ; DIS-NEXT: 00471024 and v0,v0,a3
; DIS-NEXT: {{.*}} 00042600 sll a0,a0,0x18 ; DIS-NEXT: 00042600 sll a0,a0,0x18
; DIS-NEXT: {{.*}} 00822025 or a0,a0,v0 ; DIS-NEXT: 00822025 or a0,a0,v0
; DIS-NEXT: {{.*}} 00832025 or a0,a0,v1 ; DIS-NEXT: 00832025 or a0,a0,v1
; DIS-NEXT: {{.*}} 00a01021 move v0,a1 ; DIS-NEXT: 00a01021 move v0,a1
; DIS-NEXT: {{.*}} 00801821 move v1,a0 ; DIS-NEXT: 00801821 move v1,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encBswap64 ; IASM-LABEL: encBswap64
...@@ -364,32 +364,32 @@ entry: ...@@ -364,32 +364,32 @@ entry:
; ASM-NEXT: move $v1, $a0 ; ASM-NEXT: move $v1, $a0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encBswap64Undef>: ; DIS-LABEL: <encBswap64Undef>:
; DIS-NEXT: {{.*}} 24020000 li v0,0 ; DIS-NEXT: 24020000 li v0,0
; DIS-NEXT: {{.*}} 24030000 li v1,0 ; DIS-NEXT: 24030000 li v1,0
; DIS-NEXT: {{.*}} 00032200 sll a0,v1,0x8 ; DIS-NEXT: 00032200 sll a0,v1,0x8
; DIS-NEXT: {{.*}} 00032e02 srl a1,v1,0x18 ; DIS-NEXT: 00032e02 srl a1,v1,0x18
; DIS-NEXT: {{.*}} 00033202 srl a2,v1,0x8 ; DIS-NEXT: 00033202 srl a2,v1,0x8
; DIS-NEXT: {{.*}} 30c6ff00 andi a2,a2,0xff00 ; DIS-NEXT: 30c6ff00 andi a2,a2,0xff00
; DIS-NEXT: {{.*}} 3c0700ff lui a3,0xff ; DIS-NEXT: 3c0700ff lui a3,0xff
; DIS-NEXT: {{.*}} 00c53025 or a2,a2,a1 ; DIS-NEXT: 00c53025 or a2,a2,a1
; DIS-NEXT: {{.*}} 00872024 and a0,a0,a3 ; DIS-NEXT: 00872024 and a0,a0,a3
; DIS-NEXT: {{.*}} 00031e00 sll v1,v1,0x18 ; DIS-NEXT: 00031e00 sll v1,v1,0x18
; DIS-NEXT: {{.*}} 00641825 or v1,v1,a0 ; DIS-NEXT: 00641825 or v1,v1,a0
; DIS-NEXT: {{.*}} 00022602 srl a0,v0,0x18 ; DIS-NEXT: 00022602 srl a0,v0,0x18
; DIS-NEXT: {{.*}} 00022a02 srl a1,v0,0x8 ; DIS-NEXT: 00022a02 srl a1,v0,0x8
; DIS-NEXT: {{.*}} 30a5ff00 andi a1,a1,0xff00 ; DIS-NEXT: 30a5ff00 andi a1,a1,0xff00
; DIS-NEXT: {{.*}} 00661825 or v1,v1,a2 ; DIS-NEXT: 00661825 or v1,v1,a2
; DIS-NEXT: {{.*}} 00a42825 or a1,a1,a0 ; DIS-NEXT: 00a42825 or a1,a1,a0
; DIS-NEXT: {{.*}} 00022200 sll a0,v0,0x8 ; DIS-NEXT: 00022200 sll a0,v0,0x8
; DIS-NEXT: {{.*}} 00872024 and a0,a0,a3 ; DIS-NEXT: 00872024 and a0,a0,a3
; DIS-NEXT: {{.*}} 00021600 sll v0,v0,0x18 ; DIS-NEXT: 00021600 sll v0,v0,0x18
; DIS-NEXT: {{.*}} 00441025 or v0,v0,a0 ; DIS-NEXT: 00441025 or v0,v0,a0
; DIS-NEXT: {{.*}} 00451025 or v0,v0,a1 ; DIS-NEXT: 00451025 or v0,v0,a1
; DIS-NEXT: {{.*}} 00402021 move a0,v0 ; DIS-NEXT: 00402021 move a0,v0
; DIS-NEXT: {{.*}} 00601021 move v0,v1 ; DIS-NEXT: 00601021 move v0,v1
; DIS-NEXT: {{.*}} 00801821 move v1,a0 ; DIS-NEXT: 00801821 move v1,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encBswap64Undef ; IASM-LABEL: encBswap64Undef
; IASM-NEXT: .LencBswap64Undef$entry: ; IASM-NEXT: .LencBswap64Undef$entry:
...@@ -506,10 +506,10 @@ entry: ...@@ -506,10 +506,10 @@ entry:
; ASM-NEXT: move $v0, $a0 ; ASM-NEXT: move $v0, $a0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCtlz32>: ; DIS-LABEL: <encCtlz32>:
; DIS-NEXT: {{.*}} 70842020 clz a0,a0 ; DIS-NEXT: 70842020 clz a0,a0
; DIS-NEXT: {{.*}} 00801021 move v0,a0 ; DIS-NEXT: 00801021 move v0,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCtlz32 ; IASM-LABEL: encCtlz32
; IASM-NEXT: .LencCtlz32$entry: ; IASM-NEXT: .LencCtlz32$entry:
...@@ -539,11 +539,11 @@ entry: ...@@ -539,11 +539,11 @@ entry:
; ASM-NEXT: clz $v0, $v0 ; ASM-NEXT: clz $v0, $v0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCtlz32Const>: ; DIS-LABEL: <encCtlz32Const>:
; DIS-NEXT: {{.*}} 3c020001 lui v0,0x1 ; DIS-NEXT: 3c020001 lui v0,0x1
; DIS-NEXT: {{.*}} 3442e240 ori v0,v0,0xe240 ; DIS-NEXT: 3442e240 ori v0,v0,0xe240
; DIS-NEXT: {{.*}} 70421020 clz v0,v0 ; DIS-NEXT: 70421020 clz v0,v0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCtlz32Const ; IASM-LABEL: encCtlz32Const
; IASM-NEXT: .LencCtlz32Const$entry: ; IASM-NEXT: .LencCtlz32Const$entry:
...@@ -581,15 +581,15 @@ entry: ...@@ -581,15 +581,15 @@ entry:
; ASM-NEXT: move $v0, $a0 ; ASM-NEXT: move $v0, $a0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCtlz64>: ; DIS-LABEL: <encCtlz64>:
; DIS-NEXT: {{.*}} 70a21020 clz v0,a1 ; DIS-NEXT: 70a21020 clz v0,a1
; DIS-NEXT: {{.*}} 70842020 clz a0,a0 ; DIS-NEXT: 70842020 clz a0,a0
; DIS-NEXT: {{.*}} 24840020 addiu a0,a0,32 ; DIS-NEXT: 24840020 addiu a0,a0,32
; DIS-NEXT: {{.*}} {{.*}}0b movn {{.*}} ; DIS-NEXT: 0045200b movn a0,v0,a1
; DIS-NEXT: {{.*}} 24020000 li v0,0 ; DIS-NEXT: 24020000 li v0,0
; DIS-NEXT: {{.*}} 00401821 move v1,v0 ; DIS-NEXT: 00401821 move v1,v0
; DIS-NEXT: {{.*}} 00801021 move v0,a0 ; DIS-NEXT: 00801021 move v0,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCtlz64 ; IASM-LABEL: encCtlz64
; IASM-NEXT: .LencCtlz64$entry: ; IASM-NEXT: .LencCtlz64$entry:
...@@ -607,7 +607,7 @@ entry: ...@@ -607,7 +607,7 @@ entry:
; IASM-NEXT: .byte 0x24 ; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0xb ; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0x20 ; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x82 ; IASM-NEXT: .byte 0x45
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -646,16 +646,16 @@ entry: ...@@ -646,16 +646,16 @@ entry:
; ASM-NEXT: move $v0, $v1 ; ASM-NEXT: move $v0, $v1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCtlz64Const>: ; DIS-LABEL: <encCtlz64Const>:
; DIS-NEXT: {{.*}} 2402001c li v0,28 ; DIS-NEXT: 2402001c li v0,28
; DIS-NEXT: {{.*}} 3c03be99 lui v1,0xbe99 ; DIS-NEXT: 3c03be99 lui v1,0xbe99
; DIS-NEXT: {{.*}} 34631a14 ori v1,v1,0x1a14 ; DIS-NEXT: 34631a14 ori v1,v1,0x1a14
; DIS-NEXT: {{.*}} 70442020 clz a0,v0 ; DIS-NEXT: 70442020 clz a0,v0
; DIS-NEXT: {{.*}} 70631820 clz v1,v1 ; DIS-NEXT: 70631820 clz v1,v1
; DIS-NEXT: {{.*}} 24630020 addiu v1,v1,32 ; DIS-NEXT: 24630020 addiu v1,v1,32
; DIS-NEXT: {{.*}} {{.*}}0b movn {{.*}} ; DIS-NEXT: 0082180b movn v1,a0,v0
; DIS-NEXT: {{.*}} 00601021 move v0,v1 ; DIS-NEXT: 00601021 move v0,v1
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCtlz64Const ; IASM-LABEL: encCtlz64Const
; IASM-NEXT: .LencCtlz64Const$entry: ; IASM-NEXT: .LencCtlz64Const$entry:
...@@ -685,7 +685,7 @@ entry: ...@@ -685,7 +685,7 @@ entry:
; IASM-NEXT: .byte 0x24 ; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0xb ; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0x18 ; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x64 ; IASM-NEXT: .byte 0x82
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x21 ; IASM-NEXT: .byte 0x21
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
...@@ -712,14 +712,14 @@ entry: ...@@ -712,14 +712,14 @@ entry:
; ASM-NEXT: subu $v0, $v0, $a0 ; ASM-NEXT: subu $v0, $v0, $a0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCttz32>: ; DIS-LABEL: <encCttz32>:
; DIS-NEXT: {{.*}} 2482ffff addiu v0,a0,-1 ; DIS-NEXT: 2482ffff addiu v0,a0,-1
; DIS-NEXT: {{.*}} 00802027 nor a0,a0,zero ; DIS-NEXT: 00802027 nor a0,a0,zero
; DIS-NEXT: {{.*}} 00822024 and a0,a0,v0 ; DIS-NEXT: 00822024 and a0,a0,v0
; DIS-NEXT: {{.*}} 70842020 clz a0,a0 ; DIS-NEXT: 70842020 clz a0,a0
; DIS-NEXT: {{.*}} 24020020 li v0,32 ; DIS-NEXT: 24020020 li v0,32
; DIS-NEXT: {{.*}} 00441023 subu v0,v0,a0 ; DIS-NEXT: 00441023 subu v0,v0,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCttz32 ; IASM-LABEL: encCttz32
; IASM-NEXT: .LencCttz32$entry: ; IASM-NEXT: .LencCttz32$entry:
...@@ -771,17 +771,17 @@ entry: ...@@ -771,17 +771,17 @@ entry:
; ASM-NEXT: move $v0, $v1 ; ASM-NEXT: move $v0, $v1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCttz32Const>: ; DIS-LABEL: <encCttz32Const>:
; DIS-NEXT: {{.*}} 3c020001 lui v0,0x1 ; DIS-NEXT: 3c020001 lui v0,0x1
; DIS-NEXT: {{.*}} ori v0,v0,0xe240 ; DIS-NEXT: 3442e240 ori v0,v0,0xe240
; DIS-NEXT: {{.*}} addiu v1,v0,-1 ; DIS-NEXT: 2443ffff addiu v1,v0,-1
; DIS-NEXT: {{.*}} nor v0,v0,zero ; DIS-NEXT: 00401027 nor v0,v0,zero
; DIS-NEXT: {{.*}} and v0,v0,v1 ; DIS-NEXT: 00431024 and v0,v0,v1
; DIS-NEXT: {{.*}} clz v0,v0 ; DIS-NEXT: 70421020 clz v0,v0
; DIS-NEXT: {{.*}} li v1,32 ; DIS-NEXT: 24030020 li v1,32
; DIS-NEXT: {{.*}} subu v1,v1,v0 ; DIS-NEXT: 00621823 subu v1,v1,v0
; DIS-NEXT: {{.*}} move v0,v1 ; DIS-NEXT: 00601021 move v0,v1
; DIS-NEXT: {{.*}} jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCttz32Const: ; IASM-LABEL: encCttz32Const:
; IASM-NEXT: .LencCttz32Const$entry: ; IASM-NEXT: .LencCttz32Const$entry:
...@@ -850,22 +850,23 @@ entry: ...@@ -850,22 +850,23 @@ entry:
; ASM-NEXT: addiu $v1, $zero, 0 ; ASM-NEXT: addiu $v1, $zero, 0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCttz64>: ; DIS-LABEL: <encCttz64>:
; DIS-NEXT: {{.*}} 24a2ffff addiu v0,a1,-1 ; DIS-NEXT: 24a2ffff addiu v0,a1,-1
; DIS-NEXT: {{.*}} 00a02827 nor a1,a1,zero ; DIS-NEXT: 00a02827 nor a1,a1,zero
; DIS-NEXT: {{.*}} 00a22824 and a1,a1,v0 ; DIS-NEXT: 00a22824 and a1,a1,v0
; DIS-NEXT: {{.*}} 70a52820 clz a1,a1 ; DIS-NEXT: 70a52820 clz a1,a1
; DIS-NEXT: {{.*}} 24020040 li v0,64 ; DIS-NEXT: 24020040 li v0,64
; DIS-NEXT: {{.*}} 00451023 subu v0,v0,a1 ; DIS-NEXT: 00451023 subu v0,v0,a1
; DIS-NEXT: {{.*}} 2483ffff addiu v1,a0,-1 ; DIS-NEXT: 2483ffff addiu v1,a0,-1
; DIS-NEXT: {{.*}} 00802827 nor a1,a0,zero ; DIS-NEXT: 00802827 nor a1,a0,zero
; DIS-NEXT: {{.*}} 00a32824 and a1,a1,v1 ; DIS-NEXT: 00a32824 and a1,a1,v1
; DIS-NEXT: {{.*}} 70a52820 clz a1,a1 ; DIS-NEXT: 70a52820 clz a1,a1
; DIS-NEXT: {{.*}} 24030020 li v1,32 ; DIS-NEXT: 24030020 li v1,32
; DIS-NEXT: {{.*}} 00651823 subu v1,v1,a1 ; DIS-NEXT: 00651823 subu v1,v1,a1
; DIS-NEXT: {{.*}} {{.*}}0b movn {{.*}} ; DIS-NEXT: 0064100b movn v0,v1,a0
; DIS-NEXT: {{.*}} 24030000 li v1,0 ; DIS-NEXT: 24030000 li v1,0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; DIS-NEXT: 00000000 nop
; IASM-LABEL: encCttz64: ; IASM-LABEL: encCttz64:
; IASM-NEXT: .LencCttz64$entry: ; IASM-NEXT: .LencCttz64$entry:
...@@ -919,7 +920,7 @@ entry: ...@@ -919,7 +920,7 @@ entry:
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xb ; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x43 ; IASM-NEXT: .byte 0x64
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -960,27 +961,27 @@ entry: ...@@ -960,27 +961,27 @@ entry:
; ASM-NEXT: move $v0, $a0 ; ASM-NEXT: move $v0, $a0
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: {{.*}} <encCttz64Const>: ; DIS-LABEL: <encCttz64Const>:
; DIS-NEXT: {{.*}} 2402001c li v0,28 ; DIS-NEXT: 2402001c li v0,28
; DIS-NEXT: {{.*}} 3c03be99 lui v1,0xbe99 ; DIS-NEXT: 3c03be99 lui v1,0xbe99
; DIS-NEXT: {{.*}} 34631a14 ori v1,v1,0x1a14 ; DIS-NEXT: 34631a14 ori v1,v1,0x1a14
; DIS-NEXT: {{.*}} 2444ffff addiu a0,v0,-1 ; DIS-NEXT: 2444ffff addiu a0,v0,-1
; DIS-NEXT: {{.*}} 00401027 nor v0,v0,zero ; DIS-NEXT: 00401027 nor v0,v0,zero
; DIS-NEXT: {{.*}} 00441024 and v0,v0,a0 ; DIS-NEXT: 00441024 and v0,v0,a0
; DIS-NEXT: {{.*}} 70421020 clz v0,v0 ; DIS-NEXT: 70421020 clz v0,v0
; DIS-NEXT: {{.*}} 24040040 li a0,64 ; DIS-NEXT: 24040040 li a0,64
; DIS-NEXT: {{.*}} 00822023 subu a0,a0,v0 ; DIS-NEXT: 00822023 subu a0,a0,v0
; DIS-NEXT: {{.*}} 2462ffff addiu v0,v1,-1 ; DIS-NEXT: 2462ffff addiu v0,v1,-1
; DIS-NEXT: {{.*}} 00602827 nor a1,v1,zero ; DIS-NEXT: 00602827 nor a1,v1,zero
; DIS-NEXT: {{.*}} 00a22824 and a1,a1,v0 ; DIS-NEXT: 00a22824 and a1,a1,v0
; DIS-NEXT: {{.*}} 70a52820 clz a1,a1 ; DIS-NEXT: 70a52820 clz a1,a1
; DIS-NEXT: {{.*}} 24020020 li v0,32 ; DIS-NEXT: 24020020 li v0,32
; DIS-NEXT: {{.*}} 00451023 subu v0,v0,a1 ; DIS-NEXT: 00451023 subu v0,v0,a1
; DIS-NEXT: {{.*}} {{.*}}0b movn {{.*}} ; DIS-NEXT: 0043200b movn a0,v0,v1
; DIS-NEXT: {{.*}} 24{{.*}} li {{.*}},0 ; DIS-NEXT: 24020000 li v0,0
; DIS-NEXT: {{.*}} {{.*}}21 move v1,{{.*}} ; DIS-NEXT: 00401821 move v1,v0
; DIS-NEXT: {{.*}} {{.*}}21 move v0,{{.*}} ; DIS-NEXT: 00801021 move v0,a0
; DIS-NEXT: {{.*}} 03e00008 jr ra ; DIS-NEXT: 03e00008 jr ra
; IASM-LABEL: encCttz64Const: ; IASM-LABEL: encCttz64Const:
; IASM-NEXT: .LencCttz64Const$entry: ; IASM-NEXT: .LencCttz64Const$entry:
...@@ -1046,7 +1047,7 @@ entry: ...@@ -1046,7 +1047,7 @@ entry:
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xb ; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0x20 ; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x82 ; IASM-NEXT: .byte 0x43
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -1073,8 +1074,8 @@ define internal void @encTrap() { ...@@ -1073,8 +1074,8 @@ define internal void @encTrap() {
; ASM-NEXT: .LencTrap$__0: ; ASM-NEXT: .LencTrap$__0:
; ASM-NEXT: teq $zero, $zero, 0 ; ASM-NEXT: teq $zero, $zero, 0
; DIS-LABEL: {{.*}} <encTrap>: ; DIS-LABEL: <encTrap>:
; DIS-NEXT: {{.*}} 00000034 teq zero,zero ; DIS-NEXT: 00000034 teq zero,zero
; IASM-LABEL: encTrap: ; IASM-LABEL: encTrap:
; IASM-NEXT: .LencTrap$__0: ; IASM-NEXT: .LencTrap$__0:
......
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