Skip to content

S
swiftshader
Commit d895447b by Jaydeep Patil Committed by Jim Stichnoth
Options

[SubZero] Fix floating-point comparison for MIPS

The patch fixes code generation and encoding of floating-point comparison. All floating-point comparison related test in test_fcmp cross test pass (after removing vector related tests): TotalTests=123904 Passes=123904 Failures=0 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2357143002 . Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.
parent 0465d026
Showing with 363 additions and 136 deletions
src/IceAssemblerMIPS32.cpp
...@@ -627,8 +627,8 @@ void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs, ...@@ -627,8 +627,8 @@ void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs,
void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs, void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs,
const Operand *OpCc) { const Operand *OpCc) {
IValueT Opcode = 0x00000001; IValueT Opcode = 0x00000001;
const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf"); const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt");
const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt");
OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0; OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0;
if (const auto *OpFCC = llvm::dyn_cast<OperandMIPS32FCC>(OpCc)) { if (const auto *OpFCC = llvm::dyn_cast<OperandMIPS32FCC>(OpCc)) {
Cc = OpFCC->getFCC(); Cc = OpFCC->getFCC();
......
src/IceInstMIPS32.cpp
...@@ -930,7 +930,7 @@ template <> void InstMIPS32Mov_s::emitIAS(const Cfg *Func) const { ...@@ -930,7 +930,7 @@ template <> void InstMIPS32Mov_s::emitIAS(const Cfg *Func) const {
template <> void InstMIPS32Movf::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movf::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->movf(getDest(), getSrc(0), getSrc(1)); Asm->movf(getDest(), getSrc(1), getSrc(2));
} }
template <> void InstMIPS32Movn_d::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movn_d::emitIAS(const Cfg *Func) const {
...@@ -945,7 +945,7 @@ template <> void InstMIPS32Movn_s::emitIAS(const Cfg *Func) const { ...@@ -945,7 +945,7 @@ template <> void InstMIPS32Movn_s::emitIAS(const Cfg *Func) const {
template <> void InstMIPS32Movt::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movt::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->movt(getDest(), getSrc(0), getSrc(1)); Asm->movt(getDest(), getSrc(1), getSrc(2));
} }
template <> void InstMIPS32Movz_d::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Movz_d::emitIAS(const Cfg *Func) const {
......
src/IceInstMIPS32.h
...@@ -95,8 +95,10 @@ public: ...@@ -95,8 +95,10 @@ public:
} }
void dump(const Cfg *Func, Ostream &Str) const override { void dump(const Cfg *Func, Ostream &Str) const override {
if (!BuildDefs::dump())
return;
(void)Func; (void)Func;
(void)Str; Str << "$fcc" << static_cast<uint16_t>(FpCondCode);
} }
private: private:
...@@ -1062,13 +1064,13 @@ public: ...@@ -1062,13 +1064,13 @@ public:
if (!BuildDefs::dump()) if (!BuildDefs::dump())
return; return;
Ostream &Str = Func->getContext()->getStrEmit(); Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 2); assert(getSrcSize() == 3);
Str << "\t" << Opcode << "\t"; Str << "\t" << Opcode << "\t";
getDest()->emit(Func); getDest()->emit(Func);
Str << ", "; Str << ", ";
getSrc(0)->emit(Func);
Str << ", ";
getSrc(1)->emit(Func); getSrc(1)->emit(Func);
Str << ", ";
getSrc(2)->emit(Func);
} }
void emitIAS(const Cfg *Func) const override { void emitIAS(const Cfg *Func) const override {
...@@ -1091,7 +1093,8 @@ public: ...@@ -1091,7 +1093,8 @@ public:
private: private:
InstMIPS32MovConditional(Cfg *Func, Variable *Dest, Variable *Src, InstMIPS32MovConditional(Cfg *Func, Variable *Dest, Variable *Src,
Operand *FCC) Operand *FCC)
: InstMIPS32(Func, K, 2, Dest) { : InstMIPS32(Func, K, 3, Dest) {
addSource(Dest);
addSource(Src); addSource(Src);
addSource(FCC); addSource(FCC);
} }
......
src/IceTargetLoweringMIPS32.cpp
...@@ -2468,7 +2468,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2468,7 +2468,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
auto *Zero = getZero(); auto *Zero = getZero();
InstFcmp::FCond Cond = Instr->getCondition(); InstFcmp::FCond Cond = Instr->getCondition();
auto *DestR = legalizeToReg(Dest); auto *DestR = makeReg(Dest->getType());
auto *Src0R = legalizeToReg(Src0); auto *Src0R = legalizeToReg(Src0);
auto *Src1R = legalizeToReg(Src1); auto *Src1R = legalizeToReg(Src1);
const Type Src0Ty = Src0->getType(); const Type Src0Ty = Src0->getType();
...@@ -2493,6 +2493,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2493,6 +2493,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_eq_d(Src0R, Src1R); _c_eq_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2503,6 +2504,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2503,6 +2504,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ule_d(Src0R, Src1R); _c_ule_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2513,6 +2515,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2513,6 +2515,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ult_d(Src0R, Src1R); _c_ult_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2523,6 +2526,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2523,6 +2526,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_olt_d(Src0R, Src1R); _c_olt_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2533,6 +2537,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2533,6 +2537,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ole_d(Src0R, Src1R); _c_ole_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2543,6 +2548,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2543,6 +2548,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ueq_d(Src0R, Src1R); _c_ueq_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2553,6 +2559,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2553,6 +2559,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_un_d(Src0R, Src1R); _c_un_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2563,6 +2570,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2563,6 +2570,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ueq_d(Src0R, Src1R); _c_ueq_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2573,6 +2581,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2573,6 +2581,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ole_d(Src0R, Src1R); _c_ole_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2583,6 +2592,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2583,6 +2592,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_olt_d(Src0R, Src1R); _c_olt_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2593,6 +2603,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2593,6 +2603,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ult_d(Src0R, Src1R); _c_ult_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2603,6 +2614,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2603,6 +2614,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_ule_d(Src0R, Src1R); _c_ule_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2613,6 +2625,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2613,6 +2625,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_eq_d(Src0R, Src1R); _c_eq_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movt(DestR, Zero, FCC0); _movt(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
...@@ -2623,6 +2636,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { ...@@ -2623,6 +2636,7 @@ void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
} else { } else {
_c_un_d(Src0R, Src1R); _c_un_d(Src0R, Src1R);
} }
_addiu(DestR, Zero, 1);
_movf(DestR, Zero, FCC0); _movf(DestR, Zero, FCC0);
_mov(Dest, DestR); _mov(Dest, DestR);
break; break;
......
src/IceTargetLoweringMIPS32.h
...@@ -357,7 +357,8 @@ public: ...@@ -357,7 +357,8 @@ public:
} }
void _movf(Variable *Src0, Variable *Src1, Operand *FCC) { void _movf(Variable *Src0, Variable *Src1, Operand *FCC) {
Context.insert<InstMIPS32Movf>(Src0, Src1, FCC); auto *Instr = Context.insert<InstMIPS32Movf>(Src0, Src1, FCC);
Instr->setDestRedefined();
} }
void _movn(Variable *Dest, Variable *Src0, Variable *Src1) { void _movn(Variable *Dest, Variable *Src0, Variable *Src1) {
...@@ -373,7 +374,8 @@ public: ...@@ -373,7 +374,8 @@ public:
} }
void _movt(Variable *Src0, Variable *Src1, Operand *FCC) { void _movt(Variable *Src0, Variable *Src1, Operand *FCC) {
Context.insert<InstMIPS32Movt>(Src0, Src1, FCC); auto *Instr = Context.insert<InstMIPS32Movt>(Src0, Src1, FCC);
Instr->setDestRedefined();
} }
void _movz(Variable *Dest, Variable *Src0, Variable *Src1) { void _movz(Variable *Dest, Variable *Src0, Variable *Src1) {
......
tests_lit/assembler/mips32/encoding_test_fcmp.ll
...@@ -98,15 +98,17 @@ entry: ...@@ -98,15 +98,17 @@ entry:
; ASM-LABEL: fcmpOeqFloat ; ASM-LABEL: fcmpOeqFloat
; ASM-NEXT: .LfcmpOeqFloat$entry: ; ASM-NEXT: .LfcmpOeqFloat$entry:
; ASM-NEXT: c.eq.s $f12, $f14 ; ASM-NEXT: c.eq.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000020 <fcmpOeqFloat>: ; DIS-LABEL: 00000020 <fcmpOeqFloat>:
; DIS-NEXT: 20: 460e6032 c.eq.s $f12,$f14 ; DIS-NEXT: 20: 460e6032 c.eq.s $f12,$f14
; DIS-NEXT: 24: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 24: 24020001 li v0,1
; DIS-NEXT: 28: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 28: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 2c: 03e00008 jr ra ; DIS-NEXT: 2c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 30: 03e00008 jr ra
; IASM-LABEL: fcmpOeqFloat: ; IASM-LABEL: fcmpOeqFloat:
; IASM-NEXT: .LfcmpOeqFloat$entry: ; IASM-NEXT: .LfcmpOeqFloat$entry:
...@@ -115,6 +117,10 @@ entry: ...@@ -115,6 +117,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -137,15 +143,17 @@ entry: ...@@ -137,15 +143,17 @@ entry:
; ASM-LABEL: fcmpOeqDouble ; ASM-LABEL: fcmpOeqDouble
; ASM-NEXT: .LfcmpOeqDouble$entry: ; ASM-NEXT: .LfcmpOeqDouble$entry:
; ASM-NEXT: c.eq.d $f12, $f14 ; ASM-NEXT: c.eq.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000040 <fcmpOeqDouble>: ; DIS-LABEL: 00000040 <fcmpOeqDouble>:
; DIS-NEXT: 40: 462e6032 c.eq.d $f12,$f14 ; DIS-NEXT: 40: 462e6032 c.eq.d $f12,$f14
; DIS-NEXT: 44: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 44: 24020001 li v0,1
; DIS-NEXT: 48: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 48: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 4c: 03e00008 jr ra ; DIS-NEXT: 4c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 50: 03e00008 jr ra
; IASM-LABEL: fcmpOeqDouble: ; IASM-LABEL: fcmpOeqDouble:
; IASM-NEXT: .LfcmpOeqDouble$entry: ; IASM-NEXT: .LfcmpOeqDouble$entry:
...@@ -154,6 +162,10 @@ entry: ...@@ -154,6 +162,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -176,15 +188,17 @@ entry: ...@@ -176,15 +188,17 @@ entry:
; ASM-LABEL: fcmpOgtFloat ; ASM-LABEL: fcmpOgtFloat
; ASM-NEXT: .LfcmpOgtFloat$entry: ; ASM-NEXT: .LfcmpOgtFloat$entry:
; ASM-NEXT: c.ule.s $f12, $f14 ; ASM-NEXT: c.ule.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000060 <fcmpOgtFloat>: ; DIS-LABEL: 00000060 <fcmpOgtFloat>:
; DIS-NEXT: 60: 460e6037 c.ule.s $f12,$f14 ; DIS-NEXT: 60: 460e6037 c.ule.s $f12,$f14
; DIS-NEXT: 64: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 64: 24020001 li v0,1
; DIS-NEXT: 68: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 68: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 6c: 03e00008 jr ra ; DIS-NEXT: 6c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 70: 03e00008 jr ra
; IASM-LABEL: fcmpOgtFloat: ; IASM-LABEL: fcmpOgtFloat:
; IASM-NEXT: .LfcmpOgtFloat$entry: ; IASM-NEXT: .LfcmpOgtFloat$entry:
...@@ -193,6 +207,10 @@ entry: ...@@ -193,6 +207,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -215,15 +233,17 @@ entry: ...@@ -215,15 +233,17 @@ entry:
; ASM-LABEL: fcmpOgtDouble ; ASM-LABEL: fcmpOgtDouble
; ASM-NEXT: .LfcmpOgtDouble$entry: ; ASM-NEXT: .LfcmpOgtDouble$entry:
; ASM-NEXT: c.ule.d $f12, $f14 ; ASM-NEXT: c.ule.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000080 <fcmpOgtDouble>: ; DIS-LABEL: 00000080 <fcmpOgtDouble>:
; DIS-NEXT: 80: 462e6037 c.ule.d $f12,$f14 ; DIS-NEXT: 80: 462e6037 c.ule.d $f12,$f14
; DIS-NEXT: 84: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 84: 24020001 li v0,1
; DIS-NEXT: 88: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 88: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 8c: 03e00008 jr ra ; DIS-NEXT: 8c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 90: 03e00008 jr ra
; IASM-LABEL: fcmpOgtDouble: ; IASM-LABEL: fcmpOgtDouble:
; IASM-NEXT: .LfcmpOgtDouble$entry: ; IASM-NEXT: .LfcmpOgtDouble$entry:
...@@ -232,6 +252,10 @@ entry: ...@@ -232,6 +252,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -254,15 +278,17 @@ entry: ...@@ -254,15 +278,17 @@ entry:
; ASM-LABEL: fcmpOgeFloat ; ASM-LABEL: fcmpOgeFloat
; ASM-NEXT: .LfcmpOgeFloat$entry: ; ASM-NEXT: .LfcmpOgeFloat$entry:
; ASM-NEXT: c.ult.s $f12, $f14 ; ASM-NEXT: c.ult.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000000a0 <fcmpOgeFloat>: ; DIS-LABEL: 000000a0 <fcmpOgeFloat>:
; DIS-NEXT: a0: 460e6035 c.ult.s $f12,$f14 ; DIS-NEXT: a0: 460e6035 c.ult.s $f12,$f14
; DIS-NEXT: a4: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: a4: 24020001 li v0,1
; DIS-NEXT: a8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: a8: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: ac: 03e00008 jr ra ; DIS-NEXT: ac: 30420001 andi v0,v0,0x1
; DIS-NEXT: b0: 03e00008 jr ra
; IASM-LABEL: fcmpOgeFloat: ; IASM-LABEL: fcmpOgeFloat:
; IASM-NEXT: .LfcmpOgeFloat$entry: ; IASM-NEXT: .LfcmpOgeFloat$entry:
...@@ -271,6 +297,10 @@ entry: ...@@ -271,6 +297,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -293,15 +323,17 @@ entry: ...@@ -293,15 +323,17 @@ entry:
; ASM-LABEL: fcmpOgeDouble ; ASM-LABEL: fcmpOgeDouble
; ASM-NEXT: .LfcmpOgeDouble$entry: ; ASM-NEXT: .LfcmpOgeDouble$entry:
; ASM-NEXT: c.ult.d $f12, $f14 ; ASM-NEXT: c.ult.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000000c0 <fcmpOgeDouble>: ; DIS-LABEL: 000000c0 <fcmpOgeDouble>:
; DIS-NEXT: c0: 462e6035 c.ult.d $f12,$f14 ; DIS-NEXT: c0: 462e6035 c.ult.d $f12,$f14
; DIS-NEXT: c4: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: c4: 24020001 li v0,1
; DIS-NEXT: c8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: c8: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: cc: 03e00008 jr ra ; DIS-NEXT: cc: 30420001 andi v0,v0,0x1
; DIS-NEXT: d0: 03e00008 jr ra
; IASM-LABEL: fcmpOgeDouble: ; IASM-LABEL: fcmpOgeDouble:
; IASM-NEXT: .LfcmpOgeDouble$entry: ; IASM-NEXT: .LfcmpOgeDouble$entry:
...@@ -310,6 +342,10 @@ entry: ...@@ -310,6 +342,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -332,15 +368,17 @@ entry: ...@@ -332,15 +368,17 @@ entry:
; ASM-LABEL: fcmpOltFloat ; ASM-LABEL: fcmpOltFloat
; ASM-NEXT: .LfcmpOltFloat$entry: ; ASM-NEXT: .LfcmpOltFloat$entry:
; ASM-NEXT: c.olt.s $f12, $f14 ; ASM-NEXT: c.olt.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000000e0 <fcmpOltFloat>: ; DIS-LABEL: 000000e0 <fcmpOltFloat>:
; DIS-NEXT: e0: 460e6034 c.olt.s $f12,$f14 ; DIS-NEXT: e0: 460e6034 c.olt.s $f12,$f14
; DIS-NEXT: e4: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: e4: 24020001 li v0,1
; DIS-NEXT: e8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: e8: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: ec: 03e00008 jr ra ; DIS-NEXT: ec: 30420001 andi v0,v0,0x1
; DIS-NEXT: f0: 03e00008 jr ra
; IASM-LABEL: fcmpOltFloat: ; IASM-LABEL: fcmpOltFloat:
; IASM-NEXT: .LfcmpOltFloat$entry: ; IASM-NEXT: .LfcmpOltFloat$entry:
...@@ -349,6 +387,10 @@ entry: ...@@ -349,6 +387,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -371,15 +413,17 @@ entry: ...@@ -371,15 +413,17 @@ entry:
; ASM-LABEL: fcmpOltDouble ; ASM-LABEL: fcmpOltDouble
; ASM-NEXT: .LfcmpOltDouble$entry: ; ASM-NEXT: .LfcmpOltDouble$entry:
; ASM-NEXT: c.olt.d $f12, $f14 ; ASM-NEXT: c.olt.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000100 <fcmpOltDouble>: ; DIS-LABEL: 00000100 <fcmpOltDouble>:
; DIS-NEXT: 100: 462e6034 c.olt.d $f12,$f14 ; DIS-NEXT: 100: 462e6034 c.olt.d $f12,$f14
; DIS-NEXT: 104: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 104: 24020001 li v0,1
; DIS-NEXT: 108: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 108: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 10c: 03e00008 jr ra ; DIS-NEXT: 10c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 110: 03e00008 jr ra
; IASM-LABEL: fcmpOltDouble: ; IASM-LABEL: fcmpOltDouble:
; IASM-NEXT: .LfcmpOltDouble$entry: ; IASM-NEXT: .LfcmpOltDouble$entry:
...@@ -388,6 +432,10 @@ entry: ...@@ -388,6 +432,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -410,15 +458,17 @@ entry: ...@@ -410,15 +458,17 @@ entry:
; ASM-LABEL: fcmpOleFloat ; ASM-LABEL: fcmpOleFloat
; ASM-NEXT: .LfcmpOleFloat$entry: ; ASM-NEXT: .LfcmpOleFloat$entry:
; ASM-NEXT: c.ole.s $f12, $f14 ; ASM-NEXT: c.ole.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000120 <fcmpOleFloat>: ; DIS-LABEL: 00000120 <fcmpOleFloat>:
; DIS-NEXT: 120: 460e6036 c.ole.s $f12,$f14 ; DIS-NEXT: 120: 460e6036 c.ole.s $f12,$f14
; DIS-NEXT: 124: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 124: 24020001 li v0,1
; DIS-NEXT: 128: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 128: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 12c: 03e00008 jr ra ; DIS-NEXT: 12c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 130: 03e00008 jr ra
; IASM-LABEL: fcmpOleFloat: ; IASM-LABEL: fcmpOleFloat:
; IASM-NEXT: .LfcmpOleFloat$entry: ; IASM-NEXT: .LfcmpOleFloat$entry:
...@@ -427,6 +477,10 @@ entry: ...@@ -427,6 +477,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -449,15 +503,17 @@ entry: ...@@ -449,15 +503,17 @@ entry:
; ASM-LABEL: fcmpOleDouble ; ASM-LABEL: fcmpOleDouble
; ASM-NEXT: .LfcmpOleDouble$entry: ; ASM-NEXT: .LfcmpOleDouble$entry:
; ASM-NEXT: c.ole.d $f12, $f14 ; ASM-NEXT: c.ole.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000140 <fcmpOleDouble>: ; DIS-LABEL: 00000140 <fcmpOleDouble>:
; DIS-NEXT: 140: 462e6036 c.ole.d $f12,$f14 ; DIS-NEXT: 140: 462e6036 c.ole.d $f12,$f14
; DIS-NEXT: 144: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 144: 24020001 li v0,1
; DIS-NEXT: 148: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 148: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 14c: 03e00008 jr ra ; DIS-NEXT: 14c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 150: 03e00008 jr ra
; IASM-LABEL: fcmpOleDouble: ; IASM-LABEL: fcmpOleDouble:
; IASM-NEXT: .LfcmpOleDouble$entry: ; IASM-NEXT: .LfcmpOleDouble$entry:
...@@ -466,6 +522,10 @@ entry: ...@@ -466,6 +522,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -488,15 +548,17 @@ entry: ...@@ -488,15 +548,17 @@ entry:
; ASM-LABEL: fcmpOneFloat ; ASM-LABEL: fcmpOneFloat
; ASM-NEXT: .LfcmpOneFloat$entry: ; ASM-NEXT: .LfcmpOneFloat$entry:
; ASM-NEXT: c.ueq.s $f12, $f14 ; ASM-NEXT: c.ueq.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000160 <fcmpOneFloat>: ; DIS-LABEL: 00000160 <fcmpOneFloat>:
; DIS-NEXT: 160: 460e6033 c.ueq.s $f12,$f14 ; DIS-NEXT: 160: 460e6033 c.ueq.s $f12,$f14
; DIS-NEXT: 164: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 164: 24020001 li v0,1
; DIS-NEXT: 168: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 168: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 16c: 03e00008 jr ra ; DIS-NEXT: 16c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 170: 03e00008 jr ra
; IASM-LABEL: fcmpOneFloat: ; IASM-LABEL: fcmpOneFloat:
; IASM-NEXT: .LfcmpOneFloat$entry: ; IASM-NEXT: .LfcmpOneFloat$entry:
...@@ -505,6 +567,10 @@ entry: ...@@ -505,6 +567,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -527,15 +593,17 @@ entry: ...@@ -527,15 +593,17 @@ entry:
; ASM-LABEL: fcmpOneDouble ; ASM-LABEL: fcmpOneDouble
; ASM-NEXT: .LfcmpOneDouble$entry: ; ASM-NEXT: .LfcmpOneDouble$entry:
; ASM-NEXT: c.ueq.d $f12, $f14 ; ASM-NEXT: c.ueq.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000180 <fcmpOneDouble>: ; DIS-LABEL: 00000180 <fcmpOneDouble>:
; DIS-NEXT: 180: 462e6033 c.ueq.d $f12,$f14 ; DIS-NEXT: 180: 462e6033 c.ueq.d $f12,$f14
; DIS-NEXT: 184: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 184: 24020001 li v0,1
; DIS-NEXT: 188: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 188: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 18c: 03e00008 jr ra ; DIS-NEXT: 18c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 190: 03e00008 jr ra
; IASM-LABEL: fcmpOneDouble: ; IASM-LABEL: fcmpOneDouble:
; IASM-NEXT: .LfcmpOneDouble$entry: ; IASM-NEXT: .LfcmpOneDouble$entry:
...@@ -544,6 +612,10 @@ entry: ...@@ -544,6 +612,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -566,15 +638,17 @@ entry: ...@@ -566,15 +638,17 @@ entry:
; ASM-LABEL: fcmpOrdFloat: ; ASM-LABEL: fcmpOrdFloat:
; ASM-NEXT: .LfcmpOrdFloat$entry: ; ASM-NEXT: .LfcmpOrdFloat$entry:
; ASM-NEXT: c.un.s $f12, $f14 ; ASM-NEXT: c.un.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000001a0 <fcmpOrdFloat>: ; DIS-LABEL: 000001a0 <fcmpOrdFloat>:
; DIS-NEXT: 1a0: 460e6031 c.un.s $f12,$f14 ; DIS-NEXT: 1a0: 460e6031 c.un.s $f12,$f14
; DIS-NEXT: 1a4: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 1a4: 24020001 li v0,1
; DIS-NEXT: 1a8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 1a8: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 1ac: 03e00008 jr ra ; DIS-NEXT: 1ac: 30420001 andi v0,v0,0x1
; DIS-NEXT: 1b0: 03e00008 jr ra
; IASM-LABEL: fcmpOrdFloat: ; IASM-LABEL: fcmpOrdFloat:
; IASM-NEXT: .LfcmpOrdFloat$entry: ; IASM-NEXT: .LfcmpOrdFloat$entry:
...@@ -583,6 +657,10 @@ entry: ...@@ -583,6 +657,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -605,15 +683,17 @@ entry: ...@@ -605,15 +683,17 @@ entry:
; ASM-LABEL: fcmpOrdDouble: ; ASM-LABEL: fcmpOrdDouble:
; ASM-NEXT: .LfcmpOrdDouble$entry: ; ASM-NEXT: .LfcmpOrdDouble$entry:
; ASM-NEXT: c.un.d $f12, $f14 ; ASM-NEXT: c.un.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000001c0 <fcmpOrdDouble>: ; DIS-LABEL: 000001c0 <fcmpOrdDouble>:
; DIS-NEXT: 1c0: 462e6031 c.un.d $f12,$f14 ; DIS-NEXT: 1c0: 462e6031 c.un.d $f12,$f14
; DIS-NEXT: 1c4: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 1c4: 24020001 li v0,1
; DIS-NEXT: 1c8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 1c8: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 1cc: 03e00008 jr ra ; DIS-NEXT: 1cc: 30420001 andi v0,v0,0x1
; DIS-NEXT: 1d0: 03e00008 jr ra
; IASM-LABEL: fcmpOrdDouble: ; IASM-LABEL: fcmpOrdDouble:
; IASM-NEXT: .LfcmpOrdDouble$entry: ; IASM-NEXT: .LfcmpOrdDouble$entry:
...@@ -622,6 +702,10 @@ entry: ...@@ -622,6 +702,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -644,15 +728,17 @@ entry: ...@@ -644,15 +728,17 @@ entry:
; ASM-LABEL: fcmpUeqFloat ; ASM-LABEL: fcmpUeqFloat
; ASM-NEXT: .LfcmpUeqFloat$entry: ; ASM-NEXT: .LfcmpUeqFloat$entry:
; ASM-NEXT: c.ueq.s $f12, $f14 ; ASM-NEXT: c.ueq.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000001e0 <fcmpUeqFloat>: ; DIS-LABEL: 000001e0 <fcmpUeqFloat>:
; DIS-NEXT: 1e0: 460e6033 c.ueq.s $f12,$f14 ; DIS-NEXT: 1e0: 460e6033 c.ueq.s $f12,$f14
; DIS-NEXT: 1e4: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 1e4: 24020001 li v0,1
; DIS-NEXT: 1e8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 1e8: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 1ec: 03e00008 jr ra ; DIS-NEXT: 1ec: 30420001 andi v0,v0,0x1
; DIS-NEXT: 1f0: 03e00008 jr ra
; IASM-LABEL: fcmpUeqFloat: ; IASM-LABEL: fcmpUeqFloat:
; IASM-NEXT: .LfcmpUeqFloat$entry: ; IASM-NEXT: .LfcmpUeqFloat$entry:
...@@ -661,6 +747,10 @@ entry: ...@@ -661,6 +747,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -683,15 +773,17 @@ entry: ...@@ -683,15 +773,17 @@ entry:
; ASM-LABEL: fcmpUeqDouble ; ASM-LABEL: fcmpUeqDouble
; ASM-NEXT: .LfcmpUeqDouble$entry: ; ASM-NEXT: .LfcmpUeqDouble$entry:
; ASM-NEXT: c.ueq.d $f12, $f14 ; ASM-NEXT: c.ueq.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000200 <fcmpUeqDouble>: ; DIS-LABEL: 00000200 <fcmpUeqDouble>:
; DIS-NEXT: 200: 462e6033 c.ueq.d $f12,$f14 ; DIS-NEXT: 200: 462e6033 c.ueq.d $f12,$f14
; DIS-NEXT: 204: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 204: 24020001 li v0,1
; DIS-NEXT: 208: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 208: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 20c: 03e00008 jr ra ; DIS-NEXT: 20c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 210: 03e00008 jr ra
; IASM-LABEL: fcmpUeqDouble: ; IASM-LABEL: fcmpUeqDouble:
; IASM-NEXT: .LfcmpUeqDouble$entry: ; IASM-NEXT: .LfcmpUeqDouble$entry:
...@@ -700,6 +792,10 @@ entry: ...@@ -700,6 +792,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -722,15 +818,17 @@ entry: ...@@ -722,15 +818,17 @@ entry:
; ASM-LABEL: fcmpUgtFloat ; ASM-LABEL: fcmpUgtFloat
; ASM-NEXT: .LfcmpUgtFloat$entry: ; ASM-NEXT: .LfcmpUgtFloat$entry:
; ASM-NEXT: c.ole.s $f12, $f14 ; ASM-NEXT: c.ole.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000220 <fcmpUgtFloat>: ; DIS-LABEL: 00000220 <fcmpUgtFloat>:
; DIS-NEXT: 220: 460e6036 c.ole.s $f12,$f14 ; DIS-NEXT: 220: 460e6036 c.ole.s $f12,$f14
; DIS-NEXT: 224: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 224: 24020001 li v0,1
; DIS-NEXT: 228: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 228: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 22c: 03e00008 jr ra ; DIS-NEXT: 22c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 230: 03e00008 jr ra
; IASM-LABEL: fcmpUgtFloat: ; IASM-LABEL: fcmpUgtFloat:
; IASM-NEXT: .LfcmpUgtFloat$entry: ; IASM-NEXT: .LfcmpUgtFloat$entry:
...@@ -739,6 +837,10 @@ entry: ...@@ -739,6 +837,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -761,15 +863,17 @@ entry: ...@@ -761,15 +863,17 @@ entry:
; ASM-LABEL: fcmpUgtDouble ; ASM-LABEL: fcmpUgtDouble
; ASM-NEXT: .LfcmpUgtDouble$entry: ; ASM-NEXT: .LfcmpUgtDouble$entry:
; ASM-NEXT: c.ole.d $f12, $f14 ; ASM-NEXT: c.ole.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000240 <fcmpUgtDouble>: ; DIS-LABEL: 00000240 <fcmpUgtDouble>:
; DIS-NEXT: 240: 462e6036 c.ole.d $f12,$f14 ; DIS-NEXT: 240: 462e6036 c.ole.d $f12,$f14
; DIS-NEXT: 244: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 244: 24020001 li v0,1
; DIS-NEXT: 248: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 248: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 24c: 03e00008 jr ra ; DIS-NEXT: 24c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 250: 03e00008 jr ra
; IASM-LABEL: fcmpUgtDouble: ; IASM-LABEL: fcmpUgtDouble:
; IASM-NEXT: .LfcmpUgtDouble$entry: ; IASM-NEXT: .LfcmpUgtDouble$entry:
...@@ -778,6 +882,10 @@ entry: ...@@ -778,6 +882,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -800,15 +908,17 @@ entry: ...@@ -800,15 +908,17 @@ entry:
; ASM-LABEL: fcmpUgeFloat ; ASM-LABEL: fcmpUgeFloat
; ASM-NEXT: .LfcmpUgeFloat$entry: ; ASM-NEXT: .LfcmpUgeFloat$entry:
; ASM-NEXT: c.olt.s $f12, $f14 ; ASM-NEXT: c.olt.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000260 <fcmpUgeFloat>: ; DIS-LABEL: 00000260 <fcmpUgeFloat>:
; DIS-NEXT: 260: 460e6034 c.olt.s $f12,$f14 ; DIS-NEXT: 260: 460e6034 c.olt.s $f12,$f14
; DIS-NEXT: 264: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 264: 24020001 li v0,1
; DIS-NEXT: 268: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 268: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 26c: 03e00008 jr ra ; DIS-NEXT: 26c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 270: 03e00008 jr ra
; IASM-LABEL: fcmpUgeFloat: ; IASM-LABEL: fcmpUgeFloat:
; IASM-NEXT: .LfcmpUgeFloat$entry: ; IASM-NEXT: .LfcmpUgeFloat$entry:
...@@ -817,6 +927,10 @@ entry: ...@@ -817,6 +927,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -839,15 +953,17 @@ entry: ...@@ -839,15 +953,17 @@ entry:
; ASM-LABEL: fcmpUgeDouble ; ASM-LABEL: fcmpUgeDouble
; ASM-NEXT: .LfcmpUgeDouble$entry: ; ASM-NEXT: .LfcmpUgeDouble$entry:
; ASM-NEXT: c.olt.d $f12, $f14 ; ASM-NEXT: c.olt.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000280 <fcmpUgeDouble>: ; DIS-LABEL: 00000280 <fcmpUgeDouble>:
; DIS-NEXT: 280: 462e6034 c.olt.d $f12,$f14 ; DIS-NEXT: 280: 462e6034 c.olt.d $f12,$f14
; DIS-NEXT: 284: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 284: 24020001 li v0,1
; DIS-NEXT: 288: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 288: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 28c: 03e00008 jr ra ; DIS-NEXT: 28c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 290: 03e00008 jr ra
; IASM-LABEL: fcmpUgeDouble: ; IASM-LABEL: fcmpUgeDouble:
; IASM-NEXT: .LfcmpUgeDouble$entry: ; IASM-NEXT: .LfcmpUgeDouble$entry:
...@@ -856,6 +972,10 @@ entry: ...@@ -856,6 +972,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -878,15 +998,17 @@ entry: ...@@ -878,15 +998,17 @@ entry:
; ASM-LABEL: fcmpUltFloat ; ASM-LABEL: fcmpUltFloat
; ASM-NEXT: .LfcmpUltFloat$entry: ; ASM-NEXT: .LfcmpUltFloat$entry:
; ASM-NEXT: c.ult.s $f12, $f14 ; ASM-NEXT: c.ult.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000002a0 <fcmpUltFloat>: ; DIS-LABEL: 000002a0 <fcmpUltFloat>:
; DIS-NEXT: 2a0: 460e6035 c.ult.s $f12,$f14 ; DIS-NEXT: 2a0: 460e6035 c.ult.s $f12,$f14
; DIS-NEXT: 2a4: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 2a4: 24020001 li v0,1
; DIS-NEXT: 2a8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 2a8: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 2ac: 03e00008 jr ra ; DIS-NEXT: 2ac: 30420001 andi v0,v0,0x1
; DIS-NEXT: 2b0: 03e00008 jr ra
; IASM-LABEL: fcmpUltFloat: ; IASM-LABEL: fcmpUltFloat:
; IASM-NEXT: .LfcmpUltFloat$entry: ; IASM-NEXT: .LfcmpUltFloat$entry:
...@@ -895,6 +1017,10 @@ entry: ...@@ -895,6 +1017,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -917,15 +1043,17 @@ entry: ...@@ -917,15 +1043,17 @@ entry:
; ASM-LABEL: fcmpUltDouble ; ASM-LABEL: fcmpUltDouble
; ASM-NEXT: .LfcmpUltDouble$entry: ; ASM-NEXT: .LfcmpUltDouble$entry:
; ASM-NEXT: c.ult.d $f12, $f14 ; ASM-NEXT: c.ult.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000002c0 <fcmpUltDouble>: ; DIS-LABEL: 000002c0 <fcmpUltDouble>:
; DIS-NEXT: 2c0: 462e6035 c.ult.d $f12,$f14 ; DIS-NEXT: 2c0: 462e6035 c.ult.d $f12,$f14
; DIS-NEXT: 2c4: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 2c4: 24020001 li v0,1
; DIS-NEXT: 2c8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 2c8: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 2cc: 03e00008 jr ra ; DIS-NEXT: 2cc: 30420001 andi v0,v0,0x1
; DIS-NEXT: 2d0: 03e00008 jr ra
; IASM-LABEL: fcmpUltDouble: ; IASM-LABEL: fcmpUltDouble:
; IASM-NEXT: .LfcmpUltDouble$entry: ; IASM-NEXT: .LfcmpUltDouble$entry:
...@@ -934,6 +1062,10 @@ entry: ...@@ -934,6 +1062,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -956,15 +1088,17 @@ entry: ...@@ -956,15 +1088,17 @@ entry:
; ASM-LABEL: fcmpUleFloat ; ASM-LABEL: fcmpUleFloat
; ASM-NEXT: .LfcmpUleFloat$entry: ; ASM-NEXT: .LfcmpUleFloat$entry:
; ASM-NEXT: c.ule.s $f12, $f14 ; ASM-NEXT: c.ule.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 000002e0 <fcmpUleFloat>: ; DIS-LABEL: 000002e0 <fcmpUleFloat>:
; DIS-NEXT: 2e0: 460e6037 c.ule.s $f12,$f14 ; DIS-NEXT: 2e0: 460e6037 c.ule.s $f12,$f14
; DIS-NEXT: 2e4: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 2e4: 24020001 li v0,1
; DIS-NEXT: 2e8: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 2e8: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 2ec: 03e00008 jr ra ; DIS-NEXT: 2ec: 30420001 andi v0,v0,0x1
; DIS-NEXT: 2f0: 03e00008 jr ra
; IASM-LABEL: fcmpUleFloat: ; IASM-LABEL: fcmpUleFloat:
; IASM-NEXT: .LfcmpUleFloat$entry: ; IASM-NEXT: .LfcmpUleFloat$entry:
...@@ -973,6 +1107,10 @@ entry: ...@@ -973,6 +1107,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -995,15 +1133,17 @@ entry: ...@@ -995,15 +1133,17 @@ entry:
; ASM-LABEL: fcmpUleDouble ; ASM-LABEL: fcmpUleDouble
; ASM-NEXT: .LfcmpUleDouble$entry: ; ASM-NEXT: .LfcmpUleDouble$entry:
; ASM-NEXT: c.ule.d $f12, $f14 ; ASM-NEXT: c.ule.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000300 <fcmpUleDouble>: ; DIS-LABEL: 00000300 <fcmpUleDouble>:
; DIS-NEXT: 300: 462e6037 c.ule.d $f12,$f14 ; DIS-NEXT: 300: 462e6037 c.ule.d $f12,$f14
; DIS-NEXT: 304: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 304: 24020001 li v0,1
; DIS-NEXT: 308: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 308: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 30c: 03e00008 jr ra ; DIS-NEXT: 30c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 310: 03e00008 jr ra
; IASM-LABEL: fcmpUleDouble: ; IASM-LABEL: fcmpUleDouble:
; IASM-NEXT: .LfcmpUleDouble$entry: ; IASM-NEXT: .LfcmpUleDouble$entry:
...@@ -1012,6 +1152,10 @@ entry: ...@@ -1012,6 +1152,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -1034,15 +1178,17 @@ entry: ...@@ -1034,15 +1178,17 @@ entry:
; ASM-LABEL: fcmpUneFloat ; ASM-LABEL: fcmpUneFloat
; ASM-NEXT: .LfcmpUneFloat$entry: ; ASM-NEXT: .LfcmpUneFloat$entry:
; ASM-NEXT: c.eq.s $f12, $f14 ; ASM-NEXT: c.eq.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000320 <fcmpUneFloat>: ; DIS-LABEL: 00000320 <fcmpUneFloat>:
; DIS-NEXT: 320: 460e6032 c.eq.s $f12,$f14 ; DIS-NEXT: 320: 460e6032 c.eq.s $f12,$f14
; DIS-NEXT: 324: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 324: 24020001 li v0,1
; DIS-NEXT: 328: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 328: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 32c: 03e00008 jr ra ; DIS-NEXT: 32c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 330: 03e00008 jr ra
; IASM-LABEL: fcmpUneFloat: ; IASM-LABEL: fcmpUneFloat:
; IASM-NEXT: .LfcmpUneFloat$entry: ; IASM-NEXT: .LfcmpUneFloat$entry:
...@@ -1051,6 +1197,10 @@ entry: ...@@ -1051,6 +1197,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -1073,15 +1223,17 @@ entry: ...@@ -1073,15 +1223,17 @@ entry:
; ASM-LABEL: fcmpUneDouble ; ASM-LABEL: fcmpUneDouble
; ASM-NEXT: .LfcmpUneDouble$entry: ; ASM-NEXT: .LfcmpUneDouble$entry:
; ASM-NEXT: c.eq.d $f12, $f14 ; ASM-NEXT: c.eq.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movt $v0, $zero, $fcc0 ; ASM-NEXT: movt $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000340 <fcmpUneDouble>: ; DIS-LABEL: 00000340 <fcmpUneDouble>:
; DIS-NEXT: 340: 462e6032 c.eq.d $f12,$f14 ; DIS-NEXT: 340: 462e6032 c.eq.d $f12,$f14
; DIS-NEXT: 344: 00011001 movt v0,zero,$fcc0 ; DIS-NEXT: 344: 24020001 li v0,1
; DIS-NEXT: 348: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 348: 00011001 movt v0,zero,$fcc0
; DIS-NEXT: 34c: 03e00008 jr ra ; DIS-NEXT: 34c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 350: 03e00008 jr ra
; IASM-LABEL: fcmpUneDouble: ; IASM-LABEL: fcmpUneDouble:
; IASM-NEXT: .LfcmpUneDouble$entry: ; IASM-NEXT: .LfcmpUneDouble$entry:
...@@ -1090,6 +1242,10 @@ entry: ...@@ -1090,6 +1242,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -1112,15 +1268,17 @@ entry: ...@@ -1112,15 +1268,17 @@ entry:
; ASM-LABEL: fcmpUnoFloat ; ASM-LABEL: fcmpUnoFloat
; ASM-NEXT: .LfcmpUnoFloat$entry: ; ASM-NEXT: .LfcmpUnoFloat$entry:
; ASM-NEXT: c.un.s $f12, $f14 ; ASM-NEXT: c.un.s $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000360 <fcmpUnoFloat>: ; DIS-LABEL: 00000360 <fcmpUnoFloat>:
; DIS-NEXT: 360: 460e6031 c.un.s $f12,$f14 ; DIS-NEXT: 360: 460e6031 c.un.s $f12,$f14
; DIS-NEXT: 364: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 364: 24020001 li v0,1
; DIS-NEXT: 368: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 368: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 36c: 03e00008 jr ra ; DIS-NEXT: 36c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 370: 03e00008 jr ra
; IASM-LABEL: fcmpUnoFloat: ; IASM-LABEL: fcmpUnoFloat:
; IASM-NEXT: .LfcmpUnoFloat$entry: ; IASM-NEXT: .LfcmpUnoFloat$entry:
...@@ -1129,6 +1287,10 @@ entry: ...@@ -1129,6 +1287,10 @@ entry:
; IASM-NEXT: .byte 0xe ; IASM-NEXT: .byte 0xe
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
...@@ -1151,15 +1313,17 @@ entry: ...@@ -1151,15 +1313,17 @@ entry:
; ASM-LABEL: fcmpUnoDouble ; ASM-LABEL: fcmpUnoDouble
; ASM-NEXT: .LfcmpUnoDouble$entry: ; ASM-NEXT: .LfcmpUnoDouble$entry:
; ASM-NEXT: c.un.d $f12, $f14 ; ASM-NEXT: c.un.d $f12, $f14
; ASM-NEXT: addiu $v0, $zero, 1
; ASM-NEXT: movf $v0, $zero, $fcc0 ; ASM-NEXT: movf $v0, $zero, $fcc0
; ASM-NEXT: andi $v0, $v0, 1 ; ASM-NEXT: andi $v0, $v0, 1
; ASM-NEXT: jr $ra ; ASM-NEXT: jr $ra
; DIS-LABEL: 00000380 <fcmpUnoDouble>: ; DIS-LABEL: 00000380 <fcmpUnoDouble>:
; DIS-NEXT: 380: 462e6031 c.un.d $f12,$f14 ; DIS-NEXT: 380: 462e6031 c.un.d $f12,$f14
; DIS-NEXT: 384: 00001001 movf v0,zero,$fcc0 ; DIS-NEXT: 384: 24020001 li v0,1
; DIS-NEXT: 388: 30420001 andi v0,v0,0x1 ; DIS-NEXT: 388: 00001001 movf v0,zero,$fcc0
; DIS-NEXT: 38c: 03e00008 jr ra ; DIS-NEXT: 38c: 30420001 andi v0,v0,0x1
; DIS-NEXT: 390: 03e00008 jr ra
; IASM-LABEL: fcmpUnoDouble: ; IASM-LABEL: fcmpUnoDouble:
; IASM-NEXT: .LfcmpUnoDouble$entry: ; IASM-NEXT: .LfcmpUnoDouble$entry:
...@@ -1168,6 +1332,10 @@ entry: ...@@ -1168,6 +1332,10 @@ entry:
; IASM-NEXT: .byte 0x2e ; IASM-NEXT: .byte 0x2e
; IASM-NEXT: .byte 0x46 ; IASM-NEXT: .byte 0x46
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x24
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x0
......
tests_lit/llvm2ice_tests/fp.cmp.ll
...@@ -76,10 +76,12 @@ if.end3: ; preds = %if.then2, %if.end ...@@ -76,10 +76,12 @@ if.end3: ; preds = %if.then2, %if.end
; MIPS32-LABEL: fcmpEq ; MIPS32-LABEL: fcmpEq
; MIPS32-LABEL: .LfcmpEq$entry ; MIPS32-LABEL: .LfcmpEq$entry
; MIPS32: c.eq.s ; MIPS32: c.eq.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
; MIPS32-LABEL: .LfcmpEq$if.end ; MIPS32-LABEL: .LfcmpEq$if.end
; MIPS32: c.eq.d ; MIPS32: c.eq.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
declare void @func() declare void @func()
...@@ -139,10 +141,12 @@ if.end3: ; preds = %if.then2, %if.end ...@@ -139,10 +141,12 @@ if.end3: ; preds = %if.then2, %if.end
; MIPS32-LABEL: fcmpNe ; MIPS32-LABEL: fcmpNe
; MIPS32-LABEL: .LfcmpNe$entry ; MIPS32-LABEL: .LfcmpNe$entry
; MIPS32: c.eq.s ; MIPS32: c.eq.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
; MIPS32-LABEL: .LfcmpNe$if.end ; MIPS32-LABEL: .LfcmpNe$if.end
; MIPS32: c.eq.d ; MIPS32: c.eq.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal void @fcmpGt(float %a, float %b, double %c, double %d) { define internal void @fcmpGt(float %a, float %b, double %c, double %d) {
entry: entry:
...@@ -192,10 +196,12 @@ if.end3: ; preds = %if.then2, %if.end ...@@ -192,10 +196,12 @@ if.end3: ; preds = %if.then2, %if.end
; MIPS32-LABEL: fcmpGt ; MIPS32-LABEL: fcmpGt
; MIPS32-LABEL: .LfcmpGt$entry ; MIPS32-LABEL: .LfcmpGt$entry
; MIPS32: c.ule.s ; MIPS32: c.ule.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
; MIPS32-LABEL: .LfcmpGt$if.end ; MIPS32-LABEL: .LfcmpGt$if.end
; MIPS32: c.ule.d ; MIPS32: c.ule.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal void @fcmpGe(float %a, float %b, double %c, double %d) { define internal void @fcmpGe(float %a, float %b, double %c, double %d) {
entry: entry:
...@@ -245,10 +251,12 @@ if.end3: ; preds = %if.end, %if.then2 ...@@ -245,10 +251,12 @@ if.end3: ; preds = %if.end, %if.then2
; MIPS32-LABEL: fcmpGe ; MIPS32-LABEL: fcmpGe
; MIPS32-LABEL: .LfcmpGe$entry ; MIPS32-LABEL: .LfcmpGe$entry
; MIPS32: c.ult.s ; MIPS32: c.ult.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
; MIPS32-LABEL: .LfcmpGe$if.end ; MIPS32-LABEL: .LfcmpGe$if.end
; MIPS32: c.ult.d ; MIPS32: c.ult.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal void @fcmpLt(float %a, float %b, double %c, double %d) { define internal void @fcmpLt(float %a, float %b, double %c, double %d) {
entry: entry:
...@@ -298,10 +306,12 @@ if.end3: ; preds = %if.then2, %if.end ...@@ -298,10 +306,12 @@ if.end3: ; preds = %if.then2, %if.end
; MIPS32-LABEL: fcmpLt ; MIPS32-LABEL: fcmpLt
; MIPS32-LABEL: .LfcmpLt$entry ; MIPS32-LABEL: .LfcmpLt$entry
; MIPS32: c.olt.s ; MIPS32: c.olt.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
; MIPS32-LABEL: .LfcmpLt$if.end ; MIPS32-LABEL: .LfcmpLt$if.end
; MIPS32: c.olt.d ; MIPS32: c.olt.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal void @fcmpLe(float %a, float %b, double %c, double %d) { define internal void @fcmpLe(float %a, float %b, double %c, double %d) {
entry: entry:
...@@ -351,10 +361,12 @@ if.end3: ; preds = %if.end, %if.then2 ...@@ -351,10 +361,12 @@ if.end3: ; preds = %if.end, %if.then2
; MIPS32-LABEL: fcmpLe ; MIPS32-LABEL: fcmpLe
; MIPS32-LABEL: .LfcmpLe$entry ; MIPS32-LABEL: .LfcmpLe$entry
; MIPS32: c.ole.s ; MIPS32: c.ole.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
; MIPS32-LABEL: .LfcmpLe$if.end ; MIPS32-LABEL: .LfcmpLe$if.end
; MIPS32: c.ole.d ; MIPS32: c.ole.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpFalseFloat(float %a, float %b) { define internal i32 @fcmpFalseFloat(float %a, float %b) {
entry: entry:
...@@ -402,7 +414,8 @@ entry: ...@@ -402,7 +414,8 @@ entry:
; ARM32: moveq [[R]], #1 ; ARM32: moveq [[R]], #1
; MIPS32-LABEL: fcmpOeqFloat ; MIPS32-LABEL: fcmpOeqFloat
; MIPS32: c.eq.s ; MIPS32: c.eq.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpOeqDouble(double %a, double %b) { define internal i32 @fcmpOeqDouble(double %a, double %b) {
entry: entry:
...@@ -422,7 +435,8 @@ entry: ...@@ -422,7 +435,8 @@ entry:
; ARM32: moveq [[R]], #1 ; ARM32: moveq [[R]], #1
; MIPS32-LABEL: fcmpOeqDouble ; MIPS32-LABEL: fcmpOeqDouble
; MIPS32: c.eq.d ; MIPS32: c.eq.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpOgtFloat(float %a, float %b) { define internal i32 @fcmpOgtFloat(float %a, float %b) {
entry: entry:
...@@ -441,7 +455,8 @@ entry: ...@@ -441,7 +455,8 @@ entry:
; ARM32: movgt [[R]], #1 ; ARM32: movgt [[R]], #1
; MIPS32-LABEL: fcmpOgtFloat ; MIPS32-LABEL: fcmpOgtFloat
; MIPS32: c.ule.s ; MIPS32: c.ule.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOgtDouble(double %a, double %b) { define internal i32 @fcmpOgtDouble(double %a, double %b) {
entry: entry:
...@@ -460,7 +475,8 @@ entry: ...@@ -460,7 +475,8 @@ entry:
; ARM32: movgt [[R]], #1 ; ARM32: movgt [[R]], #1
; MIPS32-LABEL: fcmpOgtDouble ; MIPS32-LABEL: fcmpOgtDouble
; MIPS32: c.ule.d ; MIPS32: c.ule.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOgeFloat(float %a, float %b) { define internal i32 @fcmpOgeFloat(float %a, float %b) {
entry: entry:
...@@ -479,7 +495,8 @@ entry: ...@@ -479,7 +495,8 @@ entry:
; ARM32: movge [[R]], #1 ; ARM32: movge [[R]], #1
; MIPS32-LABEL: fcmpOgeFloat ; MIPS32-LABEL: fcmpOgeFloat
; MIPS32: c.ult.s ; MIPS32: c.ult.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOgeDouble(double %a, double %b) { define internal i32 @fcmpOgeDouble(double %a, double %b) {
entry: entry:
...@@ -498,7 +515,8 @@ entry: ...@@ -498,7 +515,8 @@ entry:
; ARM32: movge [[R]], #1 ; ARM32: movge [[R]], #1
; MIPS32-LABEL: fcmpOgeDouble ; MIPS32-LABEL: fcmpOgeDouble
; MIPS32: c.ult.d ; MIPS32: c.ult.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOltFloat(float %a, float %b) { define internal i32 @fcmpOltFloat(float %a, float %b) {
entry: entry:
...@@ -517,7 +535,8 @@ entry: ...@@ -517,7 +535,8 @@ entry:
; ARM32: movmi [[R]], #1 ; ARM32: movmi [[R]], #1
; MIPS32-LABEL: fcmpOltFloat ; MIPS32-LABEL: fcmpOltFloat
; MIPS32: c.olt.s ; MIPS32: c.olt.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpOltDouble(double %a, double %b) { define internal i32 @fcmpOltDouble(double %a, double %b) {
entry: entry:
...@@ -536,7 +555,8 @@ entry: ...@@ -536,7 +555,8 @@ entry:
; ARM32: movmi [[R]], #1 ; ARM32: movmi [[R]], #1
; MIPS32-LABEL: fcmpOltDouble ; MIPS32-LABEL: fcmpOltDouble
; MIPS32: c.olt.d ; MIPS32: c.olt.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpOleFloat(float %a, float %b) { define internal i32 @fcmpOleFloat(float %a, float %b) {
entry: entry:
...@@ -555,7 +575,8 @@ entry: ...@@ -555,7 +575,8 @@ entry:
; ARM32: movls [[R]], #1 ; ARM32: movls [[R]], #1
; MIPS32-LABEL: fcmpOleFloat ; MIPS32-LABEL: fcmpOleFloat
; MIPS32: c.ole.s ; MIPS32: c.ole.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpOleDouble(double %a, double %b) { define internal i32 @fcmpOleDouble(double %a, double %b) {
entry: entry:
...@@ -574,7 +595,8 @@ entry: ...@@ -574,7 +595,8 @@ entry:
; ARM32: movls [[R]], #1 ; ARM32: movls [[R]], #1
; MIPS32-LABEL: fcmpOleDouble ; MIPS32-LABEL: fcmpOleDouble
; MIPS32: c.ole.d ; MIPS32: c.ole.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpOneFloat(float %a, float %b) { define internal i32 @fcmpOneFloat(float %a, float %b) {
entry: entry:
...@@ -594,7 +616,8 @@ entry: ...@@ -594,7 +616,8 @@ entry:
; ARM32: movgt [[R]], #1 ; ARM32: movgt [[R]], #1
; MIPS32-LABEL: fcmpOneFloat ; MIPS32-LABEL: fcmpOneFloat
; MIPS32: c.ueq.s ; MIPS32: c.ueq.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOneDouble(double %a, double %b) { define internal i32 @fcmpOneDouble(double %a, double %b) {
entry: entry:
...@@ -614,7 +637,8 @@ entry: ...@@ -614,7 +637,8 @@ entry:
; ARM32: movgt [[R]], #1 ; ARM32: movgt [[R]], #1
; MIPS32-LABEL: fcmpOneDouble ; MIPS32-LABEL: fcmpOneDouble
; MIPS32: c.ueq.d ; MIPS32: c.ueq.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOrdFloat(float %a, float %b) { define internal i32 @fcmpOrdFloat(float %a, float %b) {
entry: entry:
...@@ -633,7 +657,8 @@ entry: ...@@ -633,7 +657,8 @@ entry:
; ARM32: movvc [[R]], #1 ; ARM32: movvc [[R]], #1
; MIPS32-LABEL: fcmpOrdFloat ; MIPS32-LABEL: fcmpOrdFloat
; MIPS32: c.un.s ; MIPS32: c.un.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpOrdDouble(double %a, double %b) { define internal i32 @fcmpOrdDouble(double %a, double %b) {
entry: entry:
...@@ -652,7 +677,8 @@ entry: ...@@ -652,7 +677,8 @@ entry:
; ARM32: movvc [[R]], #1 ; ARM32: movvc [[R]], #1
; MIPS32-LABEL: fcmpOrdDouble ; MIPS32-LABEL: fcmpOrdDouble
; MIPS32: c.un.d ; MIPS32: c.un.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUeqFloat(float %a, float %b) { define internal i32 @fcmpUeqFloat(float %a, float %b) {
entry: entry:
...@@ -672,7 +698,8 @@ entry: ...@@ -672,7 +698,8 @@ entry:
; ARM32: movvs [[R]], #1 ; ARM32: movvs [[R]], #1
; MIPS32-LABEL: fcmpUeqFloat ; MIPS32-LABEL: fcmpUeqFloat
; MIPS32: c.ueq.s ; MIPS32: c.ueq.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUeqDouble(double %a, double %b) { define internal i32 @fcmpUeqDouble(double %a, double %b) {
entry: entry:
...@@ -692,7 +719,8 @@ entry: ...@@ -692,7 +719,8 @@ entry:
; ARM32: movvs [[R]], #1 ; ARM32: movvs [[R]], #1
; MIPS32-LABEL: fcmpUeqDouble ; MIPS32-LABEL: fcmpUeqDouble
; MIPS32: c.ueq.d ; MIPS32: c.ueq.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUgtFloat(float %a, float %b) { define internal i32 @fcmpUgtFloat(float %a, float %b) {
entry: entry:
...@@ -711,7 +739,8 @@ entry: ...@@ -711,7 +739,8 @@ entry:
; ARM32: movhi [[R]], #1 ; ARM32: movhi [[R]], #1
; MIPS32-LABEL: fcmpUgtFloat ; MIPS32-LABEL: fcmpUgtFloat
; MIPS32: c.ole.s ; MIPS32: c.ole.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUgtDouble(double %a, double %b) { define internal i32 @fcmpUgtDouble(double %a, double %b) {
entry: entry:
...@@ -730,7 +759,8 @@ entry: ...@@ -730,7 +759,8 @@ entry:
; ARM32: movhi [[R]], #1 ; ARM32: movhi [[R]], #1
; MIPS32-LABEL: fcmpUgtDouble ; MIPS32-LABEL: fcmpUgtDouble
; MIPS32: c.ole.d ; MIPS32: c.ole.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUgeFloat(float %a, float %b) { define internal i32 @fcmpUgeFloat(float %a, float %b) {
entry: entry:
...@@ -749,7 +779,8 @@ entry: ...@@ -749,7 +779,8 @@ entry:
; ARM32: movpl [[R]], #1 ; ARM32: movpl [[R]], #1
; MIPS32-LABEL: fcmpUgeFloat ; MIPS32-LABEL: fcmpUgeFloat
; MIPS32: c.olt.s ; MIPS32: c.olt.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUgeDouble(double %a, double %b) { define internal i32 @fcmpUgeDouble(double %a, double %b) {
entry: entry:
...@@ -768,7 +799,8 @@ entry: ...@@ -768,7 +799,8 @@ entry:
; ARM32: movpl [[R]], #1 ; ARM32: movpl [[R]], #1
; MIPS32-LABEL: fcmpUgeDouble ; MIPS32-LABEL: fcmpUgeDouble
; MIPS32: c.olt.d ; MIPS32: c.olt.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUltFloat(float %a, float %b) { define internal i32 @fcmpUltFloat(float %a, float %b) {
entry: entry:
...@@ -787,7 +819,8 @@ entry: ...@@ -787,7 +819,8 @@ entry:
; ARM32: movlt [[R]], #1 ; ARM32: movlt [[R]], #1
; MIPS32-LABEL: fcmpUltFloat ; MIPS32-LABEL: fcmpUltFloat
; MIPS32: c.ult.s ; MIPS32: c.ult.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUltDouble(double %a, double %b) { define internal i32 @fcmpUltDouble(double %a, double %b) {
entry: entry:
...@@ -806,7 +839,8 @@ entry: ...@@ -806,7 +839,8 @@ entry:
; ARM32: movlt [[R]], #1 ; ARM32: movlt [[R]], #1
; MIPS32-LABEL: fcmpUltDouble ; MIPS32-LABEL: fcmpUltDouble
; MIPS32: c.ult.d ; MIPS32: c.ult.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUleFloat(float %a, float %b) { define internal i32 @fcmpUleFloat(float %a, float %b) {
entry: entry:
...@@ -825,7 +859,8 @@ entry: ...@@ -825,7 +859,8 @@ entry:
; ARM32: movle [[R]], #1 ; ARM32: movle [[R]], #1
; MIPS32-LABEL: fcmpUleFloat ; MIPS32-LABEL: fcmpUleFloat
; MIPS32: c.ule.s ; MIPS32: c.ule.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUleDouble(double %a, double %b) { define internal i32 @fcmpUleDouble(double %a, double %b) {
entry: entry:
...@@ -844,7 +879,8 @@ entry: ...@@ -844,7 +879,8 @@ entry:
; ARM32: movle [[R]], #1 ; ARM32: movle [[R]], #1
; MIPS32-LABEL: fcmpUleDouble ; MIPS32-LABEL: fcmpUleDouble
; MIPS32: c.ule.d ; MIPS32: c.ule.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUneFloat(float %a, float %b) { define internal i32 @fcmpUneFloat(float %a, float %b) {
entry: entry:
...@@ -864,7 +900,8 @@ entry: ...@@ -864,7 +900,8 @@ entry:
; ARM32: movne [[R]], #1 ; ARM32: movne [[R]], #1
; MIPS32-LABEL: fcmpUneFloat ; MIPS32-LABEL: fcmpUneFloat
; MIPS32: c.eq.s ; MIPS32: c.eq.s
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUneDouble(double %a, double %b) { define internal i32 @fcmpUneDouble(double %a, double %b) {
entry: entry:
...@@ -884,7 +921,8 @@ entry: ...@@ -884,7 +921,8 @@ entry:
; ARM32: movne [[R]], #1 ; ARM32: movne [[R]], #1
; MIPS32-LABEL: fcmpUneDouble ; MIPS32-LABEL: fcmpUneDouble
; MIPS32: c.eq.d ; MIPS32: c.eq.d
; MIPS32: movt ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movt [[REG]], $zero, {{.*}}
define internal i32 @fcmpUnoFloat(float %a, float %b) { define internal i32 @fcmpUnoFloat(float %a, float %b) {
entry: entry:
...@@ -903,7 +941,8 @@ entry: ...@@ -903,7 +941,8 @@ entry:
; ARM32: movvs [[R]], #1 ; ARM32: movvs [[R]], #1
; MIPS32-LABEL: fcmpUnoFloat ; MIPS32-LABEL: fcmpUnoFloat
; MIPS32: c.un.s ; MIPS32: c.un.s
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpUnoDouble(double %a, double %b) { define internal i32 @fcmpUnoDouble(double %a, double %b) {
entry: entry:
...@@ -922,7 +961,8 @@ entry: ...@@ -922,7 +961,8 @@ entry:
; ARM32: movvs [[R]], #1 ; ARM32: movvs [[R]], #1
; MIPS32-LABEL: fcmpUnoDouble ; MIPS32-LABEL: fcmpUnoDouble
; MIPS32: c.un.d ; MIPS32: c.un.d
; MIPS32: movf ; MIPS32: addiu [[REG:.*]], $zero, 1
; MIPS32: movf [[REG]], $zero, {{.*}}
define internal i32 @fcmpTrueFloat(float %a, float %b) { define internal i32 @fcmpTrueFloat(float %a, float %b) {
entry: entry:
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment