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Commit d91cbbfa by Karl Schimpf
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Change ARM calls into indirect calls.

This is done by putting far pointers (for calls) into a register and then do an indirect call. This was done to guarantee that we aren't putting a size limit on ARM32 executables. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=jpp@chromium.org Review URL: https://codereview.chromium.org/1687553002 .
parent f084a571
Showing with 374 additions and 260 deletions
src/IceTargetLoweringARM32.cpp
...@@ -3354,7 +3354,10 @@ void TargetARM32::lowerBr(const InstBr *Instr) { ...@@ -3354,7 +3354,10 @@ void TargetARM32::lowerBr(const InstBr *Instr) {
} }
void TargetARM32::lowerCall(const InstCall *Instr) { void TargetARM32::lowerCall(const InstCall *Instr) {
Operand *CallTarget = Instr->getCallTarget(); // Note: Keep original call target. This allows us to call the correct
// postamble helper, even if the CallTarget gets modified during lowering.
Operand *OrigCallTarget = Instr->getCallTarget();
Operand *CallTarget = OrigCallTarget;
if (Instr->isTargetHelperCall()) { if (Instr->isTargetHelperCall()) {
auto TargetHelperPreamble = ARM32HelpersPreamble.find(CallTarget); auto TargetHelperPreamble = ARM32HelpersPreamble.find(CallTarget);
if (TargetHelperPreamble != ARM32HelpersPreamble.end()) { if (TargetHelperPreamble != ARM32HelpersPreamble.end()) {
...@@ -3479,12 +3482,9 @@ void TargetARM32::lowerCall(const InstCall *Instr) { ...@@ -3479,12 +3482,9 @@ void TargetARM32::lowerCall(const InstCall *Instr) {
} }
} }
// Allow ConstantRelocatable to be left alone as a direct call, but force // Note: To allow far calls, even for constant relocatables, we force
// other constants like ConstantInteger32 to be in a register and make it an // the call target into a register, and make an indirect call.
// indirect call. CallTarget = legalizeToReg(CallTarget);
if (!llvm::isa<ConstantRelocatable>(CallTarget)) {
CallTarget = legalize(CallTarget, Legal_Reg);
}
// Copy arguments to be passed in registers to the appropriate registers. // Copy arguments to be passed in registers to the appropriate registers.
for (auto &FPArg : FPArgs) { for (auto &FPArg : FPArgs) {
...@@ -3535,7 +3535,7 @@ void TargetARM32::lowerCall(const InstCall *Instr) { ...@@ -3535,7 +3535,7 @@ void TargetARM32::lowerCall(const InstCall *Instr) {
} }
if (Instr->isTargetHelperCall()) { if (Instr->isTargetHelperCall()) {
auto TargetHelpersPostamble = ARM32HelpersPostamble.find(CallTarget); auto TargetHelpersPostamble = ARM32HelpersPostamble.find(OrigCallTarget);
if (TargetHelpersPostamble != ARM32HelpersPostamble.end()) { if (TargetHelpersPostamble != ARM32HelpersPostamble.end()) {
(this->*TargetHelpersPostamble->second)(Instr); (this->*TargetHelpersPostamble->second)(Instr);
} }
......
tests_lit/assembler/arm32/call.ll 0 → 100644
; Show that we convert direct calls, into indirect calls (to handle far
; branches).
; NOTE: We use -O2 to get rid of memory stores.
; REQUIRES: allow_dump
; Compile using standalone assembler.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -allow-extern \
; RUN: -reg-use r5 | FileCheck %s --check-prefix=ASM
; Show bytes in assembled standalone code.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 -allow-extern -reg-use r5 | FileCheck %s --check-prefix=DIS
; Compile using integrated assembler.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
; RUN: -allow-extern -reg-use r5 | FileCheck %s --check-prefix=IASM
; Show bytes in assembled integrated code.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 -allow-extern -reg-use r5 | FileCheck %s --check-prefix=DIS
declare external void @doSomething()
define internal void @callSomething() {
; ASM-LABEL:callSomething:
; DIS-LABEL:{{.+}} <callSomething>:
; IASM-LABEL:callSomething:
call void @doSomething();
; ASM: movw r5, #:lower16:doSomething
; DIS: {{.+}}: e3005000
; ASM-NOT: movw
; ASM-NEXT: movt r5, #:upper16:doSomething
; DIS-NEXT: {{.+}}: e3405000
; ASM-NOT: movt
; ASM-NEXT: blx r5
; DIS-NEXT: {{.+}}: e12fff35
; ASM-NOT: blx
ret void
}
tests_lit/assembler/arm32/popmult.ll
...@@ -40,9 +40,9 @@ define internal float @test2SPops(float %p1, float %p2) { ...@@ -40,9 +40,9 @@ define internal float @test2SPops(float %p1, float %p2) {
; ASM-NEXT: vpush {s22, s23} ; ASM-NEXT: vpush {s22, s23}
; ASM-NEXT: push {lr} ; ASM-NEXT: push {lr}
; DIS: 0: ed2daa01 ; DIS: {{.+}}: ed2daa01
; DIS-NEXT: 4: ed2dba02 ; DIS-NEXT: {{.+}}: ed2dba02
; DIS-NEXT: 8: e52de004 ; DIS-NEXT: {{.+}}: e52de004
; IASM-NOT: vpush ; IASM-NOT: vpush
; IASM-NOT: push ; IASM-NOT: push
...@@ -59,9 +59,9 @@ define internal float @test2SPops(float %p1, float %p2) { ...@@ -59,9 +59,9 @@ define internal float @test2SPops(float %p1, float %p2) {
; ASM-NEXT: vpop {s22, s23} ; ASM-NEXT: vpop {s22, s23}
; ASM-NEXT: vpop {s20} ; ASM-NEXT: vpop {s20}
; DIS: 40: e49de004 ; DIS: {{.+}}: e49de004
; DIS-NEXT: 44: ecbdba02 ; DIS-NEXT: {{.+}}: ecbdba02
; DIS-NEXT: 48: ecbdaa01 ; DIS-NEXT: {{.+}}: ecbdaa01
; IASM-NOT: pop ; IASM-NOT: pop
; IASM-NOT: vpop ; IASM-NOT: vpop
......
tests_lit/assembler/arm32/push-pop.ll
...@@ -7,71 +7,42 @@ ...@@ -7,71 +7,42 @@
; Compile using standalone assembler. ; Compile using standalone assembler.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -allow-extern \ ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -allow-extern \
; RUN: | FileCheck %s --check-prefix=ASM ; RUN: -reg-use r0,r1,r2,r3,r4,r5 | FileCheck %s --check-prefix=ASM
; Show bytes in assembled standalone code. ; Show bytes in assembled standalone code.
; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 -allow-extern | FileCheck %s --check-prefix=DIS ; RUN: --args -O2 -allow-extern -reg-use r0,r1,r2,r3,r4,r5 \
; RUN: | FileCheck %s --check-prefix=DIS
; Compile using integrated assembler. ; Compile using integrated assembler.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
; RUN: -allow-extern | FileCheck %s --check-prefix=IASM ; RUN: -allow-extern -reg-use r0,r1,r2,r3,r4,r5 \
; RUN: | FileCheck %s --check-prefix=IASM
; Show bytes in assembled integrated code. ; Show bytes in assembled integrated code.
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 -allow-extern | FileCheck %s --check-prefix=DIS ; RUN: --args -O2 -allow-extern -reg-use r0,r1,r2,r3,r4,r5 \
; RUN: | FileCheck %s --check-prefix=DIS
declare external void @DoSomething() declare external void @DoSomething()
define internal void @SinglePushPop() { define internal void @SinglePushPop() {
; ASM-LABEL:SinglePushPop:
; DIS-LABEL:{{.+}} <SinglePushPop>:
; IASM-LABEL:SinglePushPop:
; ASM: push {lr}
; DIS: {{.+}} e52de004
; IASM-NOT: push
call void @DoSomething(); call void @DoSomething();
ret void ret void
}
; ASM-LABEL:SinglePushPop: ; ASM: pop {lr}
; ASM-NEXT:.LSinglePushPop$__0: ; DIS: {{.+}} e49de004
; ASM-NEXT: push {lr} ; IASM-NOT: pop
; ASM-NEXT: sub sp, sp, #12
; ASM-NEXT: bl DoSomething
; ASM-NEXT: add sp, sp, #12
; ASM-NEXT: pop {lr}
; ASM-NEXT: # lr = def.pseudo
; ASM-NEXT: bx lr
; DIS-LABEL:00000000 <SinglePushPop>:
; DIS-NEXT: 0: e52de004
; DIS-NEXT: 4: e24dd00c
; DIS-NEXT: 8: ebfffffe
; DIS-NEXT: c: e28dd00c
; DIS-NEXT: 10: e49de004
; DIS-NEXT: 14: e12fff1e
; IASM-LABEL:SinglePushPop: }
; IASM-NEXT:.LSinglePushPop$__0:
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x2d
; IASM-NEXT: .byte 0xe5
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0xd0
; IASM-NEXT: .byte 0x4d
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: bl DoSomething @ .word ebfffffe
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0xd0
; IASM-NEXT: .byte 0x8d
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x9d
; IASM-NEXT: .byte 0xe4
; IASM: .byte 0x1e
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x2f
; IASM-NEXT: .byte 0xe1
; This test is based on taking advantage of the over-eager -O2 ; This test is based on taking advantage of the over-eager -O2
; register allocator that puts V1 and V2 into callee-save registers, ; register allocator that puts V1 and V2 into callee-save registers,
...@@ -79,83 +50,21 @@ define internal void @SinglePushPop() { ...@@ -79,83 +50,21 @@ define internal void @SinglePushPop() {
; requires the callee-save registers to be pushed/popped in the ; requires the callee-save registers to be pushed/popped in the
; prolog/epilog. ; prolog/epilog.
define internal i32 @MultPushPop(i32 %v1, i32 %v2) { define internal i32 @MultPushPop(i32 %v1, i32 %v2) {
; ASM-LABEL:MultPushPop:
; DIS_LABEL: {{.+}} <MultPushPop>:
; IASM-LABEL:MultPushPop:
; ASM: push {r4, r5, lr}
; DIS: {{.+}}: e92d4030
; IASM-NOT: push
call void @DoSomething(); call void @DoSomething();
%v3 = add i32 %v1, %v2 %v3 = add i32 %v1, %v2
ret i32 %v3 ret i32 %v3
}
; ASM-LABEL:MultPushPop: ; ASM: pop {r4, r5, lr}
; ASM-NEXT:.LMultPushPop$__0: ; DIS: {{.+}} e8bd4030
; ASM-NEXT: push {r4, r5, lr} ; IASM-NOT: pop
; ASM-NEXT: sub sp, sp, #4
; ASM-NEXT: mov r4, r0
; ASM-NEXT: mov r5, r1
; ASM-NEXT: bl DoSomething
; ASM-NEXT: add r4, r4, r5
; ASM-NEXT: mov r0, r4
; ASM-NEXT: add sp, sp, #4
; ASM-NEXT: pop {r4, r5, lr}
; ASM-NEXT: # r4 = def.pseudo
; ASM-NEXT: # r5 = def.pseudo
; ASM-NEXT: # lr = def.pseudo
; ASM-NEXT: bx lr
; DIS-LABEL:00000020 <MultPushPop>:
; DIS-NEXT: 20: e92d4030
; DIS-NEXT: 24: e24dd004
; DIS-NEXT: 28: e1a04000
; DIS-NEXT: 2c: e1a05001
; DIS-NEXT: 30: ebfffffe
; DIS-NEXT: 34: e0844005
; DIS-NEXT: 38: e1a00004
; DIS-NEXT: 3c: e28dd004
; DIS-NEXT: 40: e8bd4030
; DIS-NEXT: 44: e12fff1e
; IASM-LABEL:MultPushPop: }
; IASM-NEXT:.LMultPushPop$__0:
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0x2d
; IASM-NEXT: .byte 0xe9
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0xd0
; IASM-NEXT: .byte 0x4d
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xe1
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x50
; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xe1
; IASM-NEXT: bl DoSomething @ .word ebfffffe
; IASM-NEXT: .byte 0x5
; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0x84
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xe1
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0xd0
; IASM-NEXT: .byte 0x8d
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0xbd
; IASM-NEXT: .byte 0xe8
; IASM: .byte 0x1e
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x2f
; IASM-NEXT: .byte 0xe1
tests_lit/assembler/arm32/vpush.ll
...@@ -26,10 +26,10 @@ ...@@ -26,10 +26,10 @@
define internal double @testVpushVpop(double %v1, double %v2) { define internal double @testVpushVpop(double %v1, double %v2) {
; ASM-LABEL: testVpushVpop: ; ASM-LABEL: testVpushVpop:
; DIS-LABEL: 00000000 <testVpushVpop>: ; DIS-LABEL: {{.+}} <testVpushVpop>:
; ASM: vpush {s18, s19, s20, s21} ; ASM: vpush {s18, s19, s20, s21}
; DIS: 0: ed2d9a04 ; DIS: {{.+}}: ed2d9a04
; IASM-NOT: vpush ; IASM-NOT: vpush
call void @foo() call void @foo()
...@@ -37,7 +37,7 @@ define internal double @testVpushVpop(double %v1, double %v2) { ...@@ -37,7 +37,7 @@ define internal double @testVpushVpop(double %v1, double %v2) {
ret double %res ret double %res
; ASM: vpop {s18, s19, s20, s21} ; ASM: vpop {s18, s19, s20, s21}
; DIS: 28: ecbd9a04 ; DIS: {{.+}}: ecbd9a04
; IASM-NOT: vpopd ; IASM-NOT: vpopd
} }
......
tests_lit/llvm2ice_tests/64bit.pnacl.ll
...@@ -10,18 +10,15 @@ ...@@ -10,18 +10,15 @@
; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s ; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
; once enough infrastructure is in. Also, switch to --filetype=obj
; when possible.
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=obj --assemble \
; RUN: --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \ ; RUN: --disassemble --target arm32 -i %s --args -O2 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s ; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ ; RUN: --command %p2i --filetype=obj --assemble --disassemble --target arm32 \
; RUN: -i %s --args -Om1 --skip-unimplemented \ ; RUN: -i %s --args -Om1 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s ; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
...@@ -102,18 +99,24 @@ entry: ...@@ -102,18 +99,24 @@ entry:
; ARM32-LABEL: pass64BitArg ; ARM32-LABEL: pass64BitArg
; ARM32: str {{.*}}, [sp] ; ARM32: str {{.*}}, [sp]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: mov r2, #123 ; ARM32: mov r2, #123
; ARM32: bl {{.*}} ignore64BitArgNoInline ; ARM32: blx [[CALL]]
; ARM32: str {{.*}}, [sp] ; ARM32: str {{.*}}, [sp]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: {{mov|ldr}} r0 ; ARM32: {{mov|ldr}} r0
; ARM32: {{mov|ldr}} r1 ; ARM32: {{mov|ldr}} r1
; ARM32: mov r2, #123 ; ARM32: mov r2, #123
; ARM32: bl {{.*}} ignore64BitArgNoInline ; ARM32: blx [[CALL]]
; ARM32: str {{.*}}, [sp] ; ARM32: str {{.*}}, [sp]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: {{mov|ldr}} r0 ; ARM32: {{mov|ldr}} r0
; ARM32: {{mov|ldr}} r1 ; ARM32: {{mov|ldr}} r1
; ARM32: mov r2, #123 ; ARM32: mov r2, #123
; ARM32: bl {{.*}} ignore64BitArgNoInline ; ARM32: blx [[CALL]]
; MIPS32-LABEL: pass64BitArg ; MIPS32-LABEL: pass64BitArg
...@@ -155,10 +158,13 @@ entry: ...@@ -155,10 +158,13 @@ entry:
; ARM32: movt [[REG2]], {{.*}} ; 0x1234 ; ARM32: movt [[REG2]], {{.*}} ; 0x1234
; ARM32: str [[REG1]], [sp, #4] ; ARM32: str [[REG1]], [sp, #4]
; ARM32: str [[REG2]], [sp] ; ARM32: str [[REG2]], [sp]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: {{mov|ldr}} r0 ; ARM32: {{mov|ldr}} r0
; ARM32: {{mov|ldr}} r1 ; ARM32: {{mov|ldr}} r1
; ARM32: mov r2, #123 ; ARM32: mov r2, #123
; ARM32: bl {{.*}} ignore64BitArgNoInline ; ARM32: blx [[CALL]]
define internal i32 @pass64BitUndefArg() { define internal i32 @pass64BitUndefArg() {
entry: entry:
...@@ -179,8 +185,10 @@ entry: ...@@ -179,8 +185,10 @@ entry:
; ARM32: sub sp ; ARM32: sub sp
; ARM32: mov {{.*}}, #0 ; ARM32: mov {{.*}}, #0
; ARM32: str ; ARM32: str
; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: mov {{.*}}, #123 ; ARM32: mov {{.*}}, #123
; ARM32: bl {{.*}} ignore64BitArgNoInline ; ARM32: blx [[CALL]]
; MIPS32-LABEL: pass64BitUndefArg ; MIPS32-LABEL: pass64BitUndefArg
; MIPS32: jr ra ; MIPS32: jr ra
...@@ -388,7 +396,9 @@ entry: ...@@ -388,7 +396,9 @@ entry:
; ARM32-LABEL: div64BitSigned ; ARM32-LABEL: div64BitSigned
; ARM32: orrs {{r.*}}, {{r.*}} ; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __divdi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divdi3
; ARM32: movt [[CALL]], {{.+}} __divdi3
; ARM32: blx [[CALL]]
define internal i64 @div64BitSignedConst(i64 %a) { define internal i64 @div64BitSignedConst(i64 %a) {
entry: entry:
...@@ -408,10 +418,12 @@ entry: ...@@ -408,10 +418,12 @@ entry:
; ARM32-LABEL: div64BitSignedConst ; ARM32-LABEL: div64BitSignedConst
; For a constant, we should be able to optimize-out the divide by zero check. ; For a constant, we should be able to optimize-out the divide by zero check.
; ARM32-NOT: orrs ; ARM32-NOT: orrs
; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divdi3
; ARM32: movt [[CALL]], {{.+}} __divdi3
; ARM32: movw {{.*}} ; 0x2ff2 ; ARM32: movw {{.*}} ; 0x2ff2
; ARM32: movt {{.*}} ; 0x73ce ; ARM32: movt {{.*}} ; 0x73ce
; ARM32: movw {{.*}} ; 0xb3a ; ARM32: movw {{.*}} ; 0xb3a
; ARM32: bl {{.*}} __divdi3 ; ARM32: blx [[CALL]]
define internal i64 @div64BitUnsigned(i64 %a, i64 %b) { define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
entry: entry:
...@@ -427,7 +439,9 @@ entry: ...@@ -427,7 +439,9 @@ entry:
; ARM32-LABEL: div64BitUnsigned ; ARM32-LABEL: div64BitUnsigned
; ARM32: orrs {{r.*}}, {{r.*}} ; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __udivdi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __udivdi3
; ARM32: movt [[CALL]], {{.+}} __udivdi3
; ARM32: blx [[CALL]]
define internal i64 @rem64BitSigned(i64 %a, i64 %b) { define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
entry: entry:
...@@ -443,7 +457,9 @@ entry: ...@@ -443,7 +457,9 @@ entry:
; ARM32-LABEL: rem64BitSigned ; ARM32-LABEL: rem64BitSigned
; ARM32: orrs {{r.*}}, {{r.*}} ; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __moddi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __moddi3
; ARM32: movt [[CALL]], {{.+}} __moddi3
; ARM32: blx [[CALL]]
define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) { define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
entry: entry:
...@@ -459,7 +475,9 @@ entry: ...@@ -459,7 +475,9 @@ entry:
; ARM32-LABEL: rem64BitUnsigned ; ARM32-LABEL: rem64BitUnsigned
; ARM32: orrs {{r.*}}, {{r.*}} ; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __umoddi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __umoddi3
; ARM32: movt [[CALL]], {{.+}} __umoddi3
; ARM32: blx [[CALL]]
define internal i64 @shl64BitSigned(i64 %a, i64 %b) { define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
entry: entry:
...@@ -1122,12 +1140,16 @@ if.end3: ; preds = %if.then2, %if.end ...@@ -1122,12 +1140,16 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32-OM1: tst ; ARM32-OM1: tst
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} <func> ; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
; ARM32: movt [[CALL]], {{.+}} func
; ARM32: blx [[CALL]]
; ARM32: cmp ; ARM32: cmp
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32-OM1: tst ; ARM32-OM1: tst
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} <func> ; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
; ARM32: movt [[CALL]], {{.+}} func
; ARM32: blx [[CALL]]
; ARM32: bx ; ARM32: bx
declare void @func() declare void @func()
...@@ -1192,7 +1214,9 @@ if.end3: ; preds = %if.end, %if.then2 ...@@ -1192,7 +1214,9 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-OM1: tst ; ARM32-OM1: tst
; ARM32-OM1: bne ; ARM32-OM1: bne
; ARM32-O2: beq ; ARM32-O2: beq
; ARM32: bl {{.*}} <func> ; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
; ARM32: movt [[CALL]], {{.+}} func
; ARM32: blx [[CALL]]
; ARM32: cmp ; ARM32: cmp
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32-OM1: tst ; ARM32-OM1: tst
......
tests_lit/llvm2ice_tests/alloc.ll
...@@ -9,19 +9,16 @@ ...@@ -9,19 +9,16 @@
; RUN: | %if --need=target_X8632 --command FileCheck \ ; RUN: | %if --need=target_X8632 --command FileCheck \
; RUN: --check-prefix CHECK-OPTM1 %s ; RUN: --check-prefix CHECK-OPTM1 %s
; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
; once enough infrastructure is in. Also, switch to --filetype=obj
; when possible.
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=obj --assemble \
; RUN: --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \ ; RUN: --disassemble --target arm32 -i %s --args -O2 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPT2 %s ; RUN: --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPT2 %s
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=obj --assemble \
; RUN: --disassemble --target arm32 -i %s --args -Om1 --skip-unimplemented \ ; RUN: --disassemble --target arm32 -i %s --args -Om1 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPTM1 %s ; RUN: --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPTM1 %s
...@@ -48,7 +45,9 @@ entry: ...@@ -48,7 +45,9 @@ entry:
; ARM32-LABEL: fixed_416_align_16 ; ARM32-LABEL: fixed_416_align_16
; ARM32-OPT2: sub sp, sp, #428 ; ARM32-OPT2: sub sp, sp, #428
; ARM32-OPTM1: sub sp, sp, #416 ; ARM32-OPTM1: sub sp, sp, #416
; ARM32: bl {{.*}} R_{{.*}} f1 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} f1
; ARM32: movt [[CALL]], {{.+}} f1
; ARM32: blx [[CALL]]
define internal void @fixed_416_align_32(i32 %n) { define internal void @fixed_416_align_32(i32 %n) {
entry: entry:
...@@ -70,7 +69,9 @@ entry: ...@@ -70,7 +69,9 @@ entry:
; ARM32-OPT2: sub sp, sp, #424 ; ARM32-OPT2: sub sp, sp, #424
; ARM32-OPTM1: sub sp, sp, #416 ; ARM32-OPTM1: sub sp, sp, #416
; ARM32: bic sp, sp, #31 ; ARM32: bic sp, sp, #31
; ARM32: bl {{.*}} R_{{.*}} f1 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} f1
; ARM32: movt [[CALL]], {{.+}} f1
; ARM32: blx [[CALL]]
; Show that the amount to allocate will be rounded up. ; Show that the amount to allocate will be rounded up.
define internal void @fixed_351_align_16(i32 %n) { define internal void @fixed_351_align_16(i32 %n) {
...@@ -95,7 +96,9 @@ entry: ...@@ -95,7 +96,9 @@ entry:
; ARM32-LABEL: fixed_351_align_16 ; ARM32-LABEL: fixed_351_align_16
; ARM32-OPT2: sub sp, sp, #364 ; ARM32-OPT2: sub sp, sp, #364
; ARM32-OPTM1: sub sp, sp, #352 ; ARM32-OPTM1: sub sp, sp, #352
; ARM32: bl {{.*}} R_{{.*}} f1 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} f1
; ARM32: movt [[CALL]], {{.+}} f1
; ARM32: blx [[CALL]]
define internal void @fixed_351_align_32(i32 %n) { define internal void @fixed_351_align_32(i32 %n) {
entry: entry:
...@@ -117,7 +120,9 @@ entry: ...@@ -117,7 +120,9 @@ entry:
; ARM32-OPT2: sub sp, sp, #360 ; ARM32-OPT2: sub sp, sp, #360
; ARM32-OPTM1: sub sp, sp, #352 ; ARM32-OPTM1: sub sp, sp, #352
; ARM32: bic sp, sp, #31 ; ARM32: bic sp, sp, #31
; ARM32: bl {{.*}} R_{{.*}} f1 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} f1
; ARM32: movt [[CALL]], {{.+}} f1
; ARM32: blx [[CALL]]
declare void @f1(i32 %ignored) declare void @f1(i32 %ignored)
...@@ -144,7 +149,9 @@ entry: ...@@ -144,7 +149,9 @@ entry:
; ARM32: add r0, r0, #15 ; ARM32: add r0, r0, #15
; ARM32: bic r0, r0, #15 ; ARM32: bic r0, r0, #15
; ARM32: sub sp, sp, r0 ; ARM32: sub sp, sp, r0
; ARM32: bl {{.*}} R_{{.*}} f2 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} f2
; ARM32: movt [[CALL]], {{.+}} f2
; ARM32: blx [[CALL]]
define internal void @variable_n_align_32(i32 %n) { define internal void @variable_n_align_32(i32 %n) {
entry: entry:
...@@ -176,7 +183,9 @@ entry: ...@@ -176,7 +183,9 @@ entry:
; ARM32: add r0, r0, #31 ; ARM32: add r0, r0, #31
; ARM32: bic r0, r0, #31 ; ARM32: bic r0, r0, #31
; ARM32: sub sp, sp, r0 ; ARM32: sub sp, sp, r0
; ARM32: bl {{.*}} R_{{.*}} f2 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} f2
; ARM32: movt [[CALL]], {{.+}} f2
; ARM32: blx [[CALL]]
; ARM32: mov sp, fp ; ARM32: mov sp, fp
; ARM32: pop {fp, lr} ; ARM32: pop {fp, lr}
......
tests_lit/llvm2ice_tests/arith.ll
...@@ -4,28 +4,28 @@ ...@@ -4,28 +4,28 @@
; RUN: --target x8632 -i %s --args -O2 \ ; RUN: --target x8632 -i %s --args -O2 \
; RUN: | %if --need=target_X8632 --command FileCheck %s ; RUN: | %if --need=target_X8632 --command FileCheck %s
; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
; once enough infrastructure is in. Also, switch to --filetype=obj
; when possible.
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ ; RUN: --command %p2i --filetype=obj --assemble --disassemble --target arm32 \
; RUN: -i %s --args -O2 --skip-unimplemented \ ; RUN: -i %s --args -O2 \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM-OPT2 %s ; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM-OPT2 %s
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ ; RUN: --command %p2i --filetype=obj --assemble --disassemble --target arm32 \
; RUN: -i %s --args -O2 --mattr=hwdiv-arm --skip-unimplemented \ ; RUN: -i %s --args -O2 --mattr=hwdiv-arm \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32HWDIV %s ; RUN: --command FileCheck --check-prefix ARM32HWDIV %s
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ ; RUN: --command %p2i --filetype=obj --assemble --disassemble --target arm32 \
; RUN: -i %s --args -Om1 --skip-unimplemented \ ; RUN: -i %s --args -Om1 \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OPTM1 %s ; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OPTM1 %s
; ;
; TODO(kschimpf): Stop skipping unimplemented parts (via --skip-unimplemented)
; once enough infrastructure is in. Also, switch to --filetype=obj
; when possible.
; RUN: %if --need=target_MIPS32 --need=allow_dump \ ; RUN: %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
; RUN: -i %s --args -O2 --skip-unimplemented \ ; RUN: -i %s --args -O2 -skip-unimplemented \
; RUN: | %if --need=target_MIPS32 --need=allow_dump \ ; RUN: | %if --need=target_MIPS32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix MIPS32 %s ; RUN: --command FileCheck --check-prefix MIPS32 %s
...@@ -162,8 +162,11 @@ entry: ...@@ -162,8 +162,11 @@ entry:
; ARM32-LABEL: Sdiv ; ARM32-LABEL: Sdiv
; ARM32: tst [[DENOM:r.*]], [[DENOM]] ; ARM32: tst [[DENOM:r.*]], [[DENOM]]
; ARM32: bne ; ARM32: bne
; ARM32: .word 0xe7fedef0 ; AARM32: .word 0xe7fedef0
; ARM32: {{.*}} bl {{.*}} __divsi3 ; ARM32: udf #60896 ; 0xede0
; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divsi3
; ARM32: movt [[CALL]], {{.+}} __divsi3
; ARM32: blx [[CALL]]
; ARM32HWDIV-LABEL: Sdiv ; ARM32HWDIV-LABEL: Sdiv
; ARM32HWDIV: tst ; ARM32HWDIV: tst
; ARM32HWDIV: bne ; ARM32HWDIV: bne
...@@ -182,7 +185,9 @@ entry: ...@@ -182,7 +185,9 @@ entry:
; ;
; ARM32-LABEL: SdivConst ; ARM32-LABEL: SdivConst
; ARM32-NOT: tst ; ARM32-NOT: tst
; ARM32: bl {{.*}} __divsi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divsi3
; ARM32: movt [[CALL]], {{.+}} __divsi3
; ARM32: blx [[CALL]]
; ARM32HWDIV-LABEL: SdivConst ; ARM32HWDIV-LABEL: SdivConst
; ARM32HWDIV-NOT: tst ; ARM32HWDIV-NOT: tst
; ARM32HWDIV: sdiv ; ARM32HWDIV: sdiv
...@@ -201,7 +206,9 @@ entry: ...@@ -201,7 +206,9 @@ entry:
; ARM32-LABEL: Srem ; ARM32-LABEL: Srem
; ARM32: tst [[DENOM:r.*]], [[DENOM]] ; ARM32: tst [[DENOM:r.*]], [[DENOM]]
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __modsi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __modsi3
; ARM32: movt [[CALL]], {{.+}} __modsi3
; ARM32: blx [[CALL]]
; ARM32HWDIV-LABEL: Srem ; ARM32HWDIV-LABEL: Srem
; ARM32HWDIV: tst ; ARM32HWDIV: tst
; ARM32HWDIV: bne ; ARM32HWDIV: bne
...@@ -221,7 +228,9 @@ entry: ...@@ -221,7 +228,9 @@ entry:
; ARM32-LABEL: Udiv ; ARM32-LABEL: Udiv
; ARM32: tst [[DENOM:r.*]], [[DENOM]] ; ARM32: tst [[DENOM:r.*]], [[DENOM]]
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __udivsi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __udivsi3
; ARM32: movt [[CALL]], {{.+}} __udivsi3
; ARM32: blx [[CALL]]
; ARM32HWDIV-LABEL: Udiv ; ARM32HWDIV-LABEL: Udiv
; ARM32HWDIV: tst ; ARM32HWDIV: tst
; ARM32HWDIV: bne ; ARM32HWDIV: bne
...@@ -240,7 +249,9 @@ entry: ...@@ -240,7 +249,9 @@ entry:
; ARM32-LABEL: Urem ; ARM32-LABEL: Urem
; ARM32: tst [[DENOM:r.*]], [[DENOM]] ; ARM32: tst [[DENOM:r.*]], [[DENOM]]
; ARM32: bne ; ARM32: bne
; ARM32: bl {{.*}} __umodsi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __umodsi3
; ARM32: movt [[CALL]], {{.+}} __umodsi3
; ARM32: blx [[CALL]]
; ARM32HWDIV-LABEL: Urem ; ARM32HWDIV-LABEL: Urem
; ARM32HWDIV: tst ; ARM32HWDIV: tst
; ARM32HWDIV: bne ; ARM32HWDIV: bne
......
tests_lit/llvm2ice_tests/bool-folding.ll
...@@ -55,7 +55,9 @@ branch2: ...@@ -55,7 +55,9 @@ branch2:
; CHECK: jge ; CHECK: jge
; ARM32-LABEL: fold_cmp_br_intervening_insts ; ARM32-LABEL: fold_cmp_br_intervening_insts
; ARM32: push {{[{].*[}]}} ; ARM32: push {{[{].*[}]}}
; ARM32: bl use_value ; ARM32: movw [[CALL:r[0-9]]], #:lower16:use_value
; ARM32: movt [[CALL]], #:upper16:use_value
; ARM32: blx [[CALL]]
; ARM32: cmp {{r[0-9]+}}, {{r[0-9]+}} ; ARM32: cmp {{r[0-9]+}}, {{r[0-9]+}}
; ARM32: bge ; ARM32: bge
; ARM32: mov r0, #1 ; ARM32: mov r0, #1
...@@ -190,7 +192,9 @@ entry: ...@@ -190,7 +192,9 @@ entry:
; CHECK: cmp ; CHECK: cmp
; CHECK: cmovl ; CHECK: cmovl
; ARM32-LABEL: fold_cmp_select_intervening_insts ; ARM32-LABEL: fold_cmp_select_intervening_insts
; ARM32: bl use_value ; ARM32: movw [[CALL:r[0-9]]], #:lower16:use_value
; ARM32: movt [[CALL]], #:upper16:use_value
; ARM32: blx [[CALL]]
; ARM32: cmp r{{[0-9]+}}, r{{[0-9]+}} ; ARM32: cmp r{{[0-9]+}}, r{{[0-9]+}}
; ARM32: movlt ; ARM32: movlt
; ARM32: bx lr ; ARM32: bx lr
......
tests_lit/llvm2ice_tests/branch-opt.ll
...@@ -9,18 +9,15 @@ ...@@ -9,18 +9,15 @@
; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OM1 %s ; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OM1 %s
; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
; once enough infrastructure is in. Also, switch to --filetype=obj
; when possible.
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=obj --assemble \
; RUN: --disassemble --target arm32 -i %s --args -O2 \ ; RUN: --disassemble --target arm32 -i %s --args -O2 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32O2 %s ; RUN: --command FileCheck --check-prefix ARM32O2 %s
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=obj --assemble \
; RUN: --disassemble --target arm32 -i %s --args -Om1 \ ; RUN: --disassemble --target arm32 -i %s --args -Om1 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
...@@ -51,13 +48,22 @@ next: ...@@ -51,13 +48,22 @@ next:
; OM1: call ; OM1: call
; ARM32O2-LABEL: testUncondToNextBlock ; ARM32O2-LABEL: testUncondToNextBlock
; ARM32O2: bl {{.*}} dummy ; ARM32O2: movw {{.+}} dummy
; ARM32O2-NEXT: bl {{.*}} dummy ; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32O2-NEXT: movw {{.+}} dummy
; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32OM1-LABEL: testUncondToNextBlock ; ARM32OM1-LABEL: testUncondToNextBlock
; ARM32OM1: bl {{.*}} dummy ; ARM32OM1: movw {{.+}} dummy
; ARM32OM1-NEXT: movt
; ARM32OM1-NEXT: blx
; ARM32OM1-NEXT: b ; ARM32OM1-NEXT: b
; ARM32OM1-NEXT: bl {{.*}} dummy ; ARM32OM1-NEXT: movw {{.+}} dummy
; ARM32OM1-NEXT: movt
; ARM32OM1-NEXT: blx
; For a conditional branch with a fallthrough to the next block, the ; For a conditional branch with a fallthrough to the next block, the
; fallthrough branch should be removed. ; fallthrough branch should be removed.
...@@ -95,9 +101,13 @@ target: ...@@ -95,9 +101,13 @@ target:
; ARM32O2-LABEL: testCondFallthroughToNextBlock ; ARM32O2-LABEL: testCondFallthroughToNextBlock
; ARM32O2: cmp {{.*}}, #123 ; ARM32O2: cmp {{.*}}, #123
; ARM32O2-NEXT: bge ; ARM32O2-NEXT: bge
; ARM32O2-NEXT: bl ; ARM32O2-NEXT: movw {{.+}} dummy
; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32O2: bx lr ; ARM32O2: bx lr
; ARM32O2: bl ; ARM32O2-NEXT: movw {{.+}} dummy
; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32O2: bx lr ; ARM32O2: bx lr
; ARM32OM1-LABEL: testCondFallthroughToNextBlock ; ARM32OM1-LABEL: testCondFallthroughToNextBlock
...@@ -107,9 +117,13 @@ target: ...@@ -107,9 +117,13 @@ target:
; ARM32OM1: tst {{.*}}, #1 ; ARM32OM1: tst {{.*}}, #1
; ARM32OM1: bne ; ARM32OM1: bne
; ARM32OM1: b ; ARM32OM1: b
; ARM32OM1: bl ; ARM32OM1: movw
; ARM32OM1: movt
; ARM32OM1: blx
; ARM32OM1: bx lr ; ARM32OM1: bx lr
; ARM32OM1: bl ; ARM32OM1: movw
; ARM32OM1: movt
; ARM32OM1: blx
; ARM32OM1: bx lr ; ARM32OM1: bx lr
; For a conditional branch with the next block as the target and a ; For a conditional branch with the next block as the target and a
...@@ -152,9 +166,13 @@ target: ...@@ -152,9 +166,13 @@ target:
; ARM32O2-LABEL: testCondTargetNextBlock ; ARM32O2-LABEL: testCondTargetNextBlock
; ARM32O2: cmp {{.*}}, #123 ; ARM32O2: cmp {{.*}}, #123
; ARM32O2-NEXT: blt ; ARM32O2-NEXT: blt
; ARM32O2-NEXT: bl ; ARM32O2-NEXT: movw
; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32O2: bx lr ; ARM32O2: bx lr
; ARM32O2: bl ; ARM32O2-NEXT: movw
; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32O2: bx lr ; ARM32O2: bx lr
; ARM32OM1-LABEL: testCondTargetNextBlock ; ARM32OM1-LABEL: testCondTargetNextBlock
...@@ -163,9 +181,9 @@ target: ...@@ -163,9 +181,9 @@ target:
; ARM32OM1: tst {{.*}}, #1 ; ARM32OM1: tst {{.*}}, #1
; ARM32OM1: bne ; ARM32OM1: bne
; ARM32OM1: b ; ARM32OM1: b
; ARM32OM1: bl ; ARM32OM1: blx
; ARM32OM1: bx lr ; ARM32OM1: bx lr
; ARM32OM1: bl ; ARM32OM1: blx
; ARM32OM1: bx lr ; ARM32OM1: bx lr
; Unconditional branches to the block after a contracted block should be ; Unconditional branches to the block after a contracted block should be
...@@ -194,10 +212,18 @@ target: ...@@ -194,10 +212,18 @@ target:
; OM1: call ; OM1: call
; ARM32O2-LABEL: testUncondToBlockAfterContract ; ARM32O2-LABEL: testUncondToBlockAfterContract
; ARM32O2: bl {{.*}} dummy ; ARM32O2: movw {{.+}} dummy
; ARM32O2-NEXT: bl {{.*}} dummy ; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32O2-NEXT: movw {{.+}} dummy
; ARM32O2-NEXT: movt
; ARM32O2-NEXT: blx
; ARM32OM1-LABEL: testUncondToBlockAfterContract ; ARM32OM1-LABEL: testUncondToBlockAfterContract
; ARM32OM1: bl {{.*}} dummy ; ARM32OM1: movw {{.+}} dummy
; ARM32OM1-NEXT: movt
; ARM32OM1-NEXT: blx
; ARM32OM1-NEXT: b ; ARM32OM1-NEXT: b
; ARM32OM1-NEXT: bl {{.*}} dummy ; ARM32OM1-NEXT: movw {{.+}} dummy
; ARM32OM1-NEXT: movt
; ARM32OM1-NEXT: blx
tests_lit/llvm2ice_tests/fp.arith.ll
...@@ -117,7 +117,9 @@ entry: ...@@ -117,7 +117,9 @@ entry:
; CHECK-LABEL: remFloat ; CHECK-LABEL: remFloat
; CHECK: call {{.*}} R_{{.*}} fmodf ; CHECK: call {{.*}} R_{{.*}} fmodf
; ARM32-LABEL: remFloat ; ARM32-LABEL: remFloat
; ARM32: bl {{.*}} fmodf ; ARM32: movw {{.+}} fmodf
; ARM32: movt
; ARM32: blx
define internal double @remDouble(double %a, double %b) { define internal double @remDouble(double %a, double %b) {
entry: entry:
...@@ -127,4 +129,6 @@ entry: ...@@ -127,4 +129,6 @@ entry:
; CHECK-LABEL: remDouble ; CHECK-LABEL: remDouble
; CHECK: call {{.*}} R_{{.*}} fmod ; CHECK: call {{.*}} R_{{.*}} fmod
; ARM32-LABEL: remDouble ; ARM32-LABEL: remDouble
; ARM32: bl {{.*}} fmod ; ARM32: movw {{.+}} fmod
; ARM32: movt
; ARM32: blx
tests_lit/llvm2ice_tests/fp.cmp.ll
...@@ -61,7 +61,9 @@ if.end3: ; preds = %if.then2, %if.end ...@@ -61,7 +61,9 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32-OM1: mov [[R0:r[0-9]+]], #0 ; ARM32-OM1: mov [[R0:r[0-9]+]], #0
; ARM32-OM1: moveq [[R0]], #1 ; ARM32-OM1: moveq [[R0]], #1
; ARM32-O2: bne ; ARM32-O2: bne
; ARM32: bl func ; ARM32: movw [[CALL:r[0-9]]], #:lower16:func
; ARM32: movt [[CALL:r[0-9]]], #:upper16:func
; ARM32: blx [[CALL]]
; ARM32: vcmp.f64 ; ARM32: vcmp.f64
; ARM32: vmrs ; ARM32: vmrs
; ARM32-OM1: mov [[R1:r[0-9]+]], #0 ; ARM32-OM1: mov [[R1:r[0-9]+]], #0
......
tests_lit/llvm2ice_tests/large_stack_offs.ll
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
; RUN: -i %s --args -Om1 --skip-unimplemented --test-stack-extra 4096 \ ; RUN: -i %s --args -Om1 --test-stack-extra 4096 \
; RUN: -allow-externally-defined-symbols \ ; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 %s ; RUN: --command FileCheck --check-prefix ARM32 %s
...@@ -63,12 +63,16 @@ end: ...@@ -63,12 +63,16 @@ end:
; Now skip ahead to where the call in br_1 begins, to check how %t2 is used. ; Now skip ahead to where the call in br_1 begins, to check how %t2 is used.
; ARM32: movw ip, #4232 ; ARM32: movw ip, #4232
; ARM32-NEXT: add ip, sp, ip ; ARM32-NEXT: add ip, sp, ip
; ARM32: movw [[CALL:r[0-9]]], {{.+}} dummy
; ARM32: movt [[CALL]]
; ARM32: ldr r2, [ip, #-4] ; ARM32: ldr r2, [ip, #-4]
; ARM32: bl {{.*}} dummy ; ARM32: blx [[CALL]]
; The call clobbers ip, so we need to re-create the base register. ; The call clobbers ip, so we need to re-create the base register.
; ARM32: movw ip, #4{{.*}} ; ARM32: movw ip, #4{{.*}}
; ARM32: b {{[a-f0-9]+}} ; ARM32: b {{[a-f0-9]+}}
; ARM32: bl {{.*}} dummy ; ARM32: movw [[CALL:r[0-9]]], {{.+}} dummy
; ARM32: movt [[CALL]]
; ARM32: blx [[CALL]]
; Similar, but test a function that uses FP as the base register (originally). ; Similar, but test a function that uses FP as the base register (originally).
define internal i64 @usesFrameReg(i32 %a, i32 %b, i32 %c, i32 %d) { define internal i64 @usesFrameReg(i32 %a, i32 %b, i32 %c, i32 %d) {
...@@ -118,9 +122,13 @@ end: ...@@ -118,9 +122,13 @@ end:
; Now skip ahead to where the call in br_1 begins, to check how %t2 is used. ; Now skip ahead to where the call in br_1 begins, to check how %t2 is used.
; ARM32: movw ip, #4120 ; ARM32: movw ip, #4120
; ARM32-NEXT: sub ip, fp, ip ; ARM32-NEXT: sub ip, fp, ip
; ARM32: movw [[CALL:r[0-9]]], {{.+}} dummy
; ARM32: movt [[CALL]]
; ARM32: ldr r2, [ip, #-4] ; ARM32: ldr r2, [ip, #-4]
; ARM32: bl {{.*}} dummy ; ARM32: blx [[CALL]]
; The call clobbers ip, so we need to re-create the base register. ; The call clobbers ip, so we need to re-create the base register.
; ARM32: movw ip, #4{{.*}} ; ARM32: movw ip, #4{{.*}}
; ARM32: b {{[a-f0-9]+}} ; ARM32: b {{[a-f0-9]+}}
; ARM32: bl {{.*}} dummy ; ARM32: movw [[CALL:r[0-9]]], {{.+}} dummy
; ARM32: movt [[CALL]]
; ARM32: blx [[CALL]]
tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
...@@ -129,8 +129,12 @@ NonZero: ...@@ -129,8 +129,12 @@ NonZero:
; CHECKO2REM: call {{.*}} R_{{.*}} setjmp ; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
; CHECKO2REM: call {{.*}} R_{{.*}} longjmp ; CHECKO2REM: call {{.*}} R_{{.*}} longjmp
; ARM32-LABEL: test_setjmplongjmp ; ARM32-LABEL: test_setjmplongjmp
; ARM32: bl {{.*}} setjmp ; ARM32: movw [[CALL:r[0-9]]], {{.+}} setjmp
; ARM32: bl {{.*}} longjmp ; ARM32: movt [[CALL]]
; ARM32: blx [[CALL]]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} longjmp
; ARM32: movt [[CALL]]
; ARM32: blx [[CALL]]
define internal i32 @test_setjmp_unused(i32 %iptr_env, i32 %i_other) { define internal i32 @test_setjmp_unused(i32 %iptr_env, i32 %i_other) {
entry: entry:
...@@ -471,7 +475,9 @@ entry: ...@@ -471,7 +475,9 @@ entry:
; CHECK-LABEL: test_popcount_32 ; CHECK-LABEL: test_popcount_32
; CHECK: call {{.*}} R_{{.*}} __popcountsi2 ; CHECK: call {{.*}} R_{{.*}} __popcountsi2
; ARM32-LABEL: test_popcount_32 ; ARM32-LABEL: test_popcount_32
; ARM32: bl {{.*}} __popcountsi2 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __popcountsi2
; ARM32: movt [[CALL]]
; ARM32: blx [[CALL]]
define internal i64 @test_popcount_64(i64 %x) { define internal i64 @test_popcount_64(i64 %x) {
entry: entry:
...@@ -484,7 +490,9 @@ entry: ...@@ -484,7 +490,9 @@ entry:
; the return value just in case. ; the return value just in case.
; CHECK: mov {{.*}},0x0 ; CHECK: mov {{.*}},0x0
; ARM32-LABEL: test_popcount_64 ; ARM32-LABEL: test_popcount_64
; ARM32: bl {{.*}} __popcountdi2 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __popcountdi2
; ARM32: movt [[CALL]]
; ARM32: blx [[CALL]]
; ARM32: mov {{.*}}, #0 ; ARM32: mov {{.*}}, #0
define internal i32 @test_popcount_64_ret_i32(i64 %x) { define internal i32 @test_popcount_64_ret_i32(i64 %x) {
......
tests_lit/llvm2ice_tests/select-opt.ll
...@@ -51,15 +51,23 @@ declare void @useInt(i32 %x) ...@@ -51,15 +51,23 @@ declare void @useInt(i32 %x)
; CHECK: ret ; CHECK: ret
; ARM32-LABEL: testSelect ; ARM32-LABEL: testSelect
; ARM32: cmp ; ARM32: cmp
; ARM32: bl {{.*}} useInt ; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt
; ARM32: movt [[CALL]]
; ARM32; blx [[CALL]]
; ARM32-Om1: mov {{.*}}, #20 ; ARM32-Om1: mov {{.*}}, #20
; ARM32-O2: mov [[REG:r[0-9]+]], #20 ; ARM32-O2: mov [[REG:r[0-9]+]], #20
; ARM32: tst ; ARM32: tst
; ARM32-Om1: movne {{.*}}, #10 ; ARM32-Om1: movne {{.*}}, #10
; ARM32-O2: movne [[REG]], #10 ; ARM32-O2: movne [[REG]], #10
; ARM32: bl {{.*}} useInt ; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt
; ARM32: bl {{.*}} useInt ; ARM32: movt [[CALL]]
; ARM32: bl {{.*}} useInt ; ARM32; blx [[CALL]]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt
; ARM32: movt [[CALL]]
; ARM32; blx [[CALL]]
; ARM32: movw [[CALL:r[0-9]]], {{.+}} useInt
; ARM32: movt [[CALL]]
; ARM32; blx [[CALL]]
; ARM32: bx lr ; ARM32: bx lr
; Check for valid addressing mode in the cmp instruction when the ; Check for valid addressing mode in the cmp instruction when the
......
tests_lit/llvm2ice_tests/unreachable.ll
...@@ -9,12 +9,12 @@ ...@@ -9,12 +9,12 @@
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=asm --assemble \
; RUN: --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \ ; RUN: --disassemble --target arm32 -i %s --args -O2 \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 %s ; RUN: --command FileCheck --check-prefix ARM32 %s
; RUN: %if --need=target_ARM32 --need=allow_dump \ ; RUN: %if --need=target_ARM32 --need=allow_dump \
; RUN: --command %p2i --filetype=asm --assemble \ ; RUN: --command %p2i --filetype=asm --assemble \
; RUN: --disassemble --target arm32 -i %s --args -Om1 --skip-unimplemented \ ; RUN: --disassemble --target arm32 -i %s --args -Om1 \
; RUN: | %if --need=target_ARM32 --need=allow_dump \ ; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 %s ; RUN: --command FileCheck --check-prefix ARM32 %s
...@@ -41,5 +41,7 @@ return: ; preds = %entry ...@@ -41,5 +41,7 @@ return: ; preds = %entry
; ARM32-LABEL: divide ; ARM32-LABEL: divide
; ARM32: tst ; ARM32: tst
; ARM32: .word 0xe7fedef0 ; ARM32: .word 0xe7fedef0
; ARM32: bl {{.*}} __divsi3 ; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divsi3
; ARM32: movt [[CALL]]
; ARM32; blx [[CALL]]
; ARM32: bx lr ; ARM32: bx lr
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