Commit e339d6c0 by Ben Clayton

Revert "SprivShader: Replace hand-rolled bitcount with LLVM intrinsic"

This reverts commit 0179e5eb. Reason for revert: Breaks LLVM 3 reactor backend. Change-Id: I0cdeac496c25b8b8994339e0b4b5a002d2e597f5 Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/29129Reviewed-by: 's avatarBen Clayton <bclayton@google.com> Tested-by: 's avatarBen Clayton <bclayton@google.com>
parent 0179e5eb
...@@ -2771,11 +2771,25 @@ namespace sw ...@@ -2771,11 +2771,25 @@ namespace sw
break; break;
} }
case spv::OpBitReverse: case spv::OpBitReverse:
{
dst.move(i, BitReverse(src.UInt(i))); dst.move(i, BitReverse(src.UInt(i)));
break; break;
}
case spv::OpBitCount: case spv::OpBitCount:
dst.move(i, BitCount(src.UInt(i))); {
// TODO: Add an intrinsic to reactor. Even if there isn't a
// single vector instruction, there may be target-dependent
// ways to make this faster.
// https://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
auto v = src.UInt(i);
SIMD::UInt c = v - ((v >> 1) & SIMD::UInt(0x55555555));
c = ((c >> 2) & SIMD::UInt(0x33333333)) + (c & SIMD::UInt(0x33333333));
c = ((c >> 4) + c) & SIMD::UInt(0x0F0F0F0F);
c = ((c >> 8) + c) & SIMD::UInt(0x00FF00FF);
c = ((c >> 16) + c) & SIMD::UInt(0x0000FFFF);
dst.move(i, c);
break; break;
}
case spv::OpSNegate: case spv::OpSNegate:
dst.move(i, -src.Int(i)); dst.move(i, -src.Int(i));
break; break;
......
...@@ -3220,12 +3220,6 @@ namespace rr ...@@ -3220,12 +3220,6 @@ namespace rr
return RValue<UInt4>(V(::builder->CreateCall(func, { V(v.value) }))); return RValue<UInt4>(V(::builder->CreateCall(func, { V(v.value) })));
} }
RValue<UInt4> BitCount(RValue<UInt4> v)
{
auto func = llvm::Intrinsic::getDeclaration(::module, llvm::Intrinsic::ctpop, { T(UInt4::getType()) } );
return RValue<UInt4>(V(::builder->CreateCall(func, { V(v.value) })));
}
RValue<UInt4> Ctlz(RValue<UInt4> v, bool isZeroUndef) RValue<UInt4> Ctlz(RValue<UInt4> v, bool isZeroUndef)
{ {
#if REACTOR_LLVM_VERSION < 7 #if REACTOR_LLVM_VERSION < 7
......
...@@ -2233,7 +2233,6 @@ namespace rr ...@@ -2233,7 +2233,6 @@ namespace rr
// Bit Manipulation functions. // Bit Manipulation functions.
// TODO: Currentlhy unimplemented for Subzero. // TODO: Currentlhy unimplemented for Subzero.
RValue<UInt4> BitReverse(RValue<UInt4> x); RValue<UInt4> BitReverse(RValue<UInt4> x);
RValue<UInt4> BitCount(RValue<UInt4> x);
// Count leading zeros. // Count leading zeros.
// Returns 32 when: isZeroUndef && x == 0. // Returns 32 when: isZeroUndef && x == 0.
......
...@@ -3371,17 +3371,6 @@ namespace rr ...@@ -3371,17 +3371,6 @@ namespace rr
return v; return v;
} }
RValue<UInt4> BitCount(RValue<UInt4> x)
{
// https://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
UInt4 v = x - ((x >> 1) & UInt4(0x55555555));
v = ((v >> 2) & UInt4(0x33333333)) + (v & UInt4(0x33333333));
v = ((v >> 4) + v) & UInt4(0x0F0F0F0F);
v = ((v >> 8) + v) & UInt4(0x00FF00FF);
v = ((v >> 16) + v) & UInt4(0x0000FFFF);
return v;
}
Type *Float4::getType() Type *Float4::getType()
{ {
return T(Ice::IceType_v4f32); return T(Ice::IceType_v4f32);
......
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