Add missing `volatile`s to 32-bit ARM cycleclock assembler. (#253)

Without these, clang reorders these instructions as if they were regular loads/stores which causes SIGILL from the kernel because it performs all the loads before it starts testing the values.

Add missing `volatile`s to 32-bit ARM cycleclock assembler. (#253)
b805b7c6 · Elliott Hughes · Dominic Hamon · 7e40ff9e · b805b7c6
Commit b805b7c6 authored Jul 12, 2016 by Elliott Hughes Committed by Dominic Hamon Jul 12, 2016
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cycleclock.h src/cycleclock.h +3 -3

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--- a/src/cycleclock.h
+++ b/src/cycleclock.h
@@ -113,11 +113,11 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
  uint32_t pmuseren;
  uint32_t pmcntenset;
  // Read the user mode perf monitor counter access permissions.
-  asm("mrc p15, 0, %0, c9, c14, 0" : "=r"(pmuseren));
+  asm volatile("mrc p15, 0, %0, c9, c14, 0" : "=r"(pmuseren));
  if (pmuseren & 1) {  // Allows reading perfmon counters for user mode code.
-    asm("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcntenset));
+    asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcntenset));
    if (pmcntenset & 0x80000000ul) {  // Is it counting?
-      asm("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr));
+      asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr));
      // The counter is set up to count every 64th cycle
      return static_cast<int64_t>(pmccntr) * 64;  // Should optimize to << 6
    }