The x86 lowering sequences for sdiv/udiv/srem/urem all have a problem, in that they don't reflect the fact that two registers are affected by the instruction.

For example, the urem instruction:
  dest = src0 urem src1
lowers to something like this:
  t1:eax = src0
  t2:edx = 0
  t2:edx = (t1:eax and t2:edx) div src1
  dest = t2:edx

The problem is that there is no indication that the div instruction smashes eax.  As such, it's possible that the register allocator could erroneously assume that src0 is still available in eax after the div instruction.

To fix this, we make use of the FakeDef instruction.  In this example, we change the div instruction to "officially" produce eax as its result, then fakedef edx in terms of eax.  This means that as long as the urem result is actually used, the definitions of eax and edx will be preserved, but if the urem result is unused, then the whole sequence can be dead-code eliminated.

  t1:eax = src0
  t2:edx = 0
  t1:eax = (t1:eax and t2:edx) div src1  # dest var changed to t1:eax
  t2:edx = fakedef t1:eax                # fakedef instruction added
  dest = t2:edx

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/2158213002 .