Specifically: sub, and, or, xor; for all integer types.

Turns out that RMW is not possible for fadd/fsub/fmul/fdiv as well as operations on vector types, because the corresponding x86 instructions require the result to be in a physical register.

Refactors the assembler's implementations of add/or/adc/sbb/and/sub/xor/cmp to avoid repetition.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4095
R=jvoung@chromium.org

Review URL: https://codereview.chromium.org/1186713010