add RBIT instruction to the ARM integrated assembler.

src/DartARM32/assembler_arm.h

@@ -1321,6 +1321,7 @@ class Assembler : public ValueObject {
   // Added the following missing operations:
   //
   // ARM32::AssemblerARM::uxt() (uxtb and uxth).
+  // ARM32::AssemblerARM:rbit().
 #endif
 
   DISALLOW_ALLOCATION();

src/IceAssemblerARM32.cpp

@@ -1797,21 +1797,39 @@ void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
             MulName);
 }
 
-void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpSrc,
+void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode,
+                              const Operand *OpRd, const Operand *OpRm,
+                              const char *InstName) {
+  IValueT Rd = encodeRegister(OpRd, "Rd", InstName);
+  IValueT Rm = encodeRegister(OpRm, "Rm", InstName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding =
+      (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::rbit(const Operand *OpRd, const Operand *OpRm,
+                          CondARM32::Cond Cond) {
+  // RBIT - ARM section A8.8.144, encoding A1:
+  //   rbit<c> <Rd>, <Rm>
+  //
+  // cccc011011111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
+  constexpr const char *RbitName = "rev";
+  constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 |
+                                 B17 | B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  emitRdRm(Cond, RbitOpcode, OpRd, OpRm, RbitName);
+}
+
+void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpRm,
                          CondARM32::Cond Cond) {
   // REV - ARM section A8.8.145, encoding A1:
-  //   rev <Rd>, <Rm>
+  //   rev<c> <Rd>, <Rm>
   //
   // cccc011010111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
   constexpr const char *RevName = "rev";
-  IValueT Rd = encodeRegister(OpRd, "Rd", RevName);
-  IValueT Rm = encodeRegister(OpSrc, "Rm", RevName);
-  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
-  constexpr IValueT Opcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
-                             B16 | B11 | B10 | B9 | B8 | B5 | B4;
-  IValueT Encoding =
-      (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
-  emitInst(Encoding);
+  constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
+                                B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  emitRdRm(Cond, RevOpcode, OpRd, OpRm, RevName);
 }
 
 void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn,

src/IceAssemblerARM32.h

@@ -265,7 +265,9 @@ public:
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void pushList(const IValueT Registers, CondARM32::Cond Cond);
 
-  void rev(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+  void rbit(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
+
+  void rev(const Operand *OpRd, const Operand *OpRm, CondARM32::Cond Cond);
 
   void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
@@ -384,6 +386,11 @@ private:
                  bool IsByte, IValueT Rt, IValueT Address,
                  const char *InstName);
 
+  // Emit ccccxxxxxxxxxxxxddddxxxxxxxxmmmm where cccc=Cond,
+  // xxxxxxxxxxxx0000xxxxxxxx0000=Opcode, dddd=Rd, and mmmm=Rm.
+  void emitRdRm(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRd,
+                const Operand *OpRm, const char *InstName);
+
   // Emit ldr/ldrb/str/strb instruction with given address.
   void emitMemOp(CondARM32::Cond Cond, bool IsLoad, bool IsByte, IValueT Rt,
                  const Operand *OpAddress, const TargetInfo &TInfo,

src/IceInstARM32.cpp

@@ -1210,6 +1210,14 @@ void InstARM32UnaryopGPR<K, Nws>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32Rbit::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  Asm->rbit(getDest(), getSrc(0), getPredicate());
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Rev::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();

tests_lit/assembler/arm32/rbit.ll

+; Show that we know how to translate rbit.
+
+; NOTE: We use -O2 to get rid of memory stores.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+declare i32 @llvm.cttz.i32(i32, i1)
+
+define internal i32 @testRbit(i32 %a) {
+; ASM-LABEL: testRbit:
+; DIS-LABEL: 00000000 <testRbit>:
+; IASM-LABEL: testRbit:
+
+entry:
+; ASM-NEXT: .LtestRbit$entry:
+; IASM-NEXT: .LtestRbit$entry:
+
+  %x = call i32 @llvm.cttz.i32(i32 %a, i1 0)
+
+; ASM-NEXT:     rbit    r0, r0
+; DIS-NEXT:    0:       e6ff0f30
+; IASM-NEXT:    .byte 0x30
+; IASM-NEXT:    .byte 0xf
+; IASM-NEXT:    .byte 0xff
+; IASM-NEXT:    .byte 0xe6
+
+  ret i32 %x
+}