Skip to content

S
swiftshader
Commit 2187c84a by John Porto
Options

Subzero. ARM32. Introduces explicit register parameter attribute.

The ARM32 backend used to rely on a specific register declaration order for calling convention register assignment. This CL introduces a new field in the ARM32 register tables for explicitly setting which register holds which parameter. BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1508423003 .
parent 6106df80
Showing with 159 additions and 35 deletions
Makefile.standalone
......@@ -323,6 +323,9 @@ $(SB_OBJDIR)/pnacl-sz.x86-32.nexe: $(SB_OBJS)
$(SB_TRANSLATE) -arch x86-32 $(PNACL_SZ_BASE).nonfinal.pexe -o $@ \
--allow-llvm-bitcode-input
src/IceRegistersARM32.def: pydir/gen_arm32_reg_tables.py
python $< > $@
# TODO(stichnot): Be more precise than "*.h" here and elsewhere.
$(OBJS): $(OBJDIR)/%.o: src/%.cpp src/*.h src/*.def
$(CXX) -c $(CXXFLAGS) $< -o $@
......
src/IceRegList.h
......@@ -27,10 +27,10 @@
{ ns::Reg_##r0, ns::Reg_##r1, ns::Reg_##r2 }
#define REGLIST4(ns, r0, r1, r2, r3) \
{ ns::Reg_##r0, ns::Reg_##r1, ns::Reg_##r2, ns::Reg_##r3 }
#define REGLIST6(ns, r0, r1, r2, r3, r4, r5) \
#define REGLIST7(ns, r0, r1, r2, r3, r4, r5, r6) \
{ \
ns::Reg_##r0, ns::Reg_##r1, ns::Reg_##r2, ns::Reg_##r3, ns::Reg_##r4, \
ns::Reg_##r5 \
ns::Reg_##r5, ns::Reg_##r6 \
}
#endif // SUBZERO_SRC_ICEINSTREGLIST_H
src/IceRegistersARM32.def 0 → 100644
// This file was auto generated by the gen_arm32_reg_tables.py script.
// Do not modify it: modify the script instead.
#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF
#define SUBZERO_SRC_ICEREGISTERSARM32_DEF
#define REGARM32_GPR_TABLE \
X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \
X(Reg_r1, 1, "r1", 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r1, r0r1)) \
X(Reg_r2, 2, "r2", 3, 1, 0, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r2, r2r3)) \
X(Reg_r3, 3, "r3", 4, 1, 0, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r3, r2r3)) \
X(Reg_r4, 4, "r4", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r4, r4r5)) \
X(Reg_r5, 5, "r5", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r5, r4r5)) \
X(Reg_r6, 6, "r6", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r6, r6r7)) \
X(Reg_r7, 7, "r7", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r7, r6r7)) \
X(Reg_r8, 8, "r8", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r8, r8r9)) \
X(Reg_r9, 9, "r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, REGLIST2(RegARM32, r9, r8r9)) \
X(Reg_r10, 10, "r10", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r10, r10fp)) \
X(Reg_fp, 11, "fp", 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, fp, r10fp)) \
X(Reg_ip, 12, "ip", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST1(RegARM32, ip)) \
X(Reg_sp, 13, "sp", 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, REGLIST1(RegARM32, sp)) \
X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \
X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc))
#define REGARM32_I64PAIR_TABLE \
X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \
X(Reg_r2r3, 2, "r2, r3", 2, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r2r3, r2, r3)) \
X(Reg_r4r5, 4, "r4, r5", 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r4r5, r4, r5)) \
X(Reg_r6r7, 6, "r6, r7", 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r6r7, r6, r7)) \
X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \
X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
#define REGARM32_FP32_TABLE \
X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \
X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s1, d0, q0)) \
X(Reg_s2, 2, "s2", 3, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s2, d1, q0)) \
X(Reg_s3, 3, "s3", 4, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s3, d1, q0)) \
X(Reg_s4, 4, "s4", 5, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s4, d2, q1)) \
X(Reg_s5, 5, "s5", 6, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s5, d2, q1)) \
X(Reg_s6, 6, "s6", 7, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s6, d3, q1)) \
X(Reg_s7, 7, "s7", 8, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s7, d3, q1)) \
X(Reg_s8, 8, "s8", 9, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s8, d4, q2)) \
X(Reg_s9, 9, "s9", 10, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s9, d4, q2)) \
X(Reg_s10, 10, "s10", 11, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s10, d5, q2)) \
X(Reg_s11, 11, "s11", 12, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s11, d5, q2)) \
X(Reg_s12, 12, "s12", 13, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s12, d6, q3)) \
X(Reg_s13, 13, "s13", 14, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s13, d6, q3)) \
X(Reg_s14, 14, "s14", 15, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s14, d7, q3)) \
X(Reg_s15, 15, "s15", 16, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s15, d7, q3)) \
X(Reg_s16, 16, "s16", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s16, d8, q4)) \
X(Reg_s17, 17, "s17", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s17, d8, q4)) \
X(Reg_s18, 18, "s18", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s18, d9, q4)) \
X(Reg_s19, 19, "s19", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s19, d9, q4)) \
X(Reg_s20, 20, "s20", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s20, d10, q5)) \
X(Reg_s21, 21, "s21", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s21, d10, q5)) \
X(Reg_s22, 22, "s22", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s22, d11, q5)) \
X(Reg_s23, 23, "s23", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s23, d11, q5)) \
X(Reg_s24, 24, "s24", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s24, d12, q6)) \
X(Reg_s25, 25, "s25", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s25, d12, q6)) \
X(Reg_s26, 26, "s26", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s26, d13, q6)) \
X(Reg_s27, 27, "s27", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s27, d13, q6)) \
X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \
X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s29, d14, q7)) \
X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \
X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d14, q7))
#define REGARM32_FP64_TABLE \
X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15)) \
X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \
X(Reg_d29, 29, "d29", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d29, q14)) \
X(Reg_d28, 28, "d28", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d28, q14)) \
X(Reg_d27, 27, "d27", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d27, q13)) \
X(Reg_d26, 26, "d26", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d26, q13)) \
X(Reg_d25, 25, "d25", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d25, q12)) \
X(Reg_d24, 24, "d24", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d24, q12)) \
X(Reg_d23, 23, "d23", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d23, q11)) \
X(Reg_d22, 22, "d22", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d22, q11)) \
X(Reg_d21, 21, "d21", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d21, q10)) \
X(Reg_d20, 20, "d20", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d20, q10)) \
X(Reg_d19, 19, "d19", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d19, q9)) \
X(Reg_d18, 18, "d18", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d18, q9)) \
X(Reg_d17, 17, "d17", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d17, q8)) \
X(Reg_d16, 16, "d16", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d16, q8)) \
X(Reg_d15, 15, "d15", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d15, q7, s30, s31)) \
X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s28)) \
X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d13, q6, s26, s27)) \
X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d12, q6, s24, s25)) \
X(Reg_d11, 11, "d11", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d11, q5, s22, s24)) \
X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d10, q5, s20, s21)) \
X(Reg_d9, 9, "d9", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d9, q4, s18, s19)) \
X(Reg_d8, 8, "d8", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d8, q4, s16, s17)) \
X(Reg_d7, 7, "d7", 8, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d7, q3, s14, s15)) \
X(Reg_d6, 6, "d6", 7, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d6, q3, s12, s13)) \
X(Reg_d5, 5, "d5", 6, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d5, q2, s10, s11)) \
X(Reg_d4, 4, "d4", 5, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d4, q2, s8, s9)) \
X(Reg_d3, 3, "d3", 4, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d3, q1, s6, s7)) \
X(Reg_d2, 2, "d2", 3, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d2, q1, s4, s5)) \
X(Reg_d1, 1, "d1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d1, q0, s2, s3)) \
X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d0, q0, s0, s1))
#define REGARM32_VEC128_TABLE \
X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q15, d30, d31)) \
X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q14, d28, d29)) \
X(Reg_q13, 13, "q13", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q13, d26, d27)) \
X(Reg_q12, 12, "q12", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q12, d24, d25)) \
X(Reg_q11, 11, "q11", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q11, d22, d23)) \
X(Reg_q10, 10, "q10", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q10, d20, d21)) \
X(Reg_q9, 9, "q9", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q9, d18, d19)) \
X(Reg_q8, 8, "q8", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q8, d16, d17)) \
X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30, s31)) \
X(Reg_q6, 6, "q6", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q6, d12, d13, s24, s25, s26, s27)) \
X(Reg_q5, 5, "q5", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q5, d10, d11, s20, s21, s22, s23)) \
X(Reg_q4, 4, "q4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q4, d8, d9, s16, s17, s18, s19)) \
X(Reg_q3, 3, "q3", 4, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q3, d6, d7, s12, s13, s14, s15)) \
X(Reg_q2, 2, "q2", 3, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q2, d4, d5, s8, s9, s10, s11)) \
X(Reg_q1, 1, "q1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q1, d2, d3, s4, s5, s6, s7)) \
X(Reg_q0, 0, "q0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q0, d0, d1, s0, s1, s2, s3))
#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF
src/IceRegistersARM32.h
......@@ -27,8 +27,8 @@ public:
/// An enum of every register. The enum value may not match the encoding used
/// to binary encode register operands in instructions.
enum AllRegisters {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
val,
REGARM32_TABLE
#undef X
......@@ -41,8 +41,8 @@ public:
/// An enum of GPR Registers. The enum value does match the encoding used to
/// binary encode register operands in instructions.
enum GPRRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_GPR_TABLE
#undef X
......@@ -52,8 +52,8 @@ public:
/// An enum of FP32 S-Registers. The enum value does match the encoding used
/// to binary encode register operands in instructions.
enum SRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_FP32_TABLE
#undef X
......@@ -63,8 +63,8 @@ public:
/// An enum of FP64 D-Registers. The enum value does match the encoding used
/// to binary encode register operands in instructions.
enum DRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_FP64_TABLE
#undef X
......@@ -74,8 +74,8 @@ public:
/// An enum of 128-bit Q-Registers. The enum value does match the encoding
/// used to binary encode register operands in instructions.
enum QRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_VEC128_TABLE
#undef X
......@@ -94,6 +94,12 @@ public:
return GPRRegister(2 * (RegNum - Reg_I64PAIR_First + Reg_GPR_First));
}
static inline GPRRegister getI64PairSecondGPRNum(int32_t RegNum) {
assert(Reg_I64PAIR_First <= RegNum);
assert(RegNum <= Reg_I64PAIR_Last);
return GPRRegister(2 * (RegNum - Reg_I64PAIR_First + Reg_GPR_First) + 1);
}
static inline bool isI64RegisterPair(int32_t RegNum) {
return Reg_I64PAIR_First <= RegNum && RegNum <= Reg_I64PAIR_Last;
}
......
src/IceTargetLoweringARM32.h
......@@ -1046,34 +1046,30 @@ protected:
CallingConv &operator=(const CallingConv &) = delete;
public:
CallingConv()
: VFPRegsFree(ARM32_MAX_FP_REG_UNITS, true),
ValidF64Regs(ARM32_MAX_FP_REG_UNITS),
ValidV128Regs(ARM32_MAX_FP_REG_UNITS) {
for (uint32_t i = 0; i < ARM32_MAX_FP_REG_UNITS; ++i) {
if ((i % 2) == 0) {
ValidF64Regs[i] = true;
}
if ((i % 4) == 0) {
ValidV128Regs[i] = true;
}
}
}
CallingConv();
~CallingConv() = default;
bool I64InRegs(std::pair<int32_t, int32_t> *Regs);
bool I32InReg(int32_t *Reg);
bool FPInReg(Type Ty, int32_t *Reg);
/// argInGPR returns true if there is a GPR available for the requested
/// type, and false otherwise. If it returns true, Reg is set to the
/// appropriate register number. Note that, when Ty == IceType_i64, Reg will
/// be an I64 register pair.
bool argInGPR(Type Ty, int32_t *Reg);
static constexpr uint32_t ARM32_MAX_GPR_ARG = 4;
// TODO(jpp): comment.
static constexpr uint32_t ARM32_MAX_FP_REG_UNITS = 16;
/// argInVFP is to floating-point/vector types what argInGPR is for integer
/// types.
bool argInVFP(Type Ty, int32_t *Reg);
private:
uint32_t NumGPRRegsUsed = 0;
llvm::SmallBitVector VFPRegsFree;
llvm::SmallBitVector ValidF64Regs;
llvm::SmallBitVector ValidV128Regs;
void discardUnavailableGPRsAndTheirAliases(CfgVector<SizeT> *Regs);
llvm::SmallBitVector GPRegsUsed;
CfgVector<SizeT> GPRArgs;
CfgVector<SizeT> I64Args;
void discardUnavailableVFPRegs(CfgVector<SizeT> *Regs);
llvm::SmallBitVector VFPRegsUsed;
CfgVector<SizeT> FP32Args;
CfgVector<SizeT> FP64Args;
CfgVector<SizeT> Vec128Args;
};
private:
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment