[SubZero] Utilize instructions with immediate operands

This patch optimizes code generation of instructions with 16-bit immediate operands R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2478113003 . Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.

[SubZero] Utilize instructions with immediate operands
21f78bb1 · Jaydeep Patil · Jim Stichnoth · 3da9f657 · 21f78bb1 · 21f78bb1
Commit 21f78bb1 authored Nov 06, 2016 by Jaydeep Patil Committed by Jim Stichnoth Nov 06, 2016
9 changed files
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -2553,30 +2553,75 @@ void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) {

  Variable *T = makeReg(Dest->getType());
  Variable *Src0R = legalizeToReg(Src0);
-  Variable *Src1R = legalizeToReg(Src1);
+  Variable *Src1R = nullptr;
+  uint32_t Value = 0;
+  bool IsSrc1Imm16 = false;
+
+  switch (Instr->getOp()) {
+  case InstArithmetic::Add:
+  case InstArithmetic::And:
+  case InstArithmetic::Or:
+  case InstArithmetic::Xor:
+  case InstArithmetic::Sub:
+  case InstArithmetic::Shl:
+  case InstArithmetic::Lshr:
+  case InstArithmetic::Ashr: {
+    auto *Const32 = llvm::dyn_cast<ConstantInteger32>(Src1);
+    if (Const32 != nullptr && isInt<16>(int32_t(Const32->getValue()))) {
+      IsSrc1Imm16 = true;
+      Value = Const32->getValue();
+    } else {
+      Src1R = legalizeToReg(Src1);
+    }
+    break;
+  }
+  default:
+    Src1R = legalizeToReg(Src1);
+    break;
+  }
  constexpr uint32_t DivideByZeroTrapCode = 7;

  switch (Instr->getOp()) {
  case InstArithmetic::_num:
    break;
  case InstArithmetic::Add:
-    _addu(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _addiu(T, Src0R, Value);
+    } else {
+      _addu(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  case InstArithmetic::And:
-    _and(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _andi(T, Src0R, Value);
+    } else {
+      _and(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  case InstArithmetic::Or:
-    _or(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _ori(T, Src0R, Value);
+    } else {
+      _or(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  case InstArithmetic::Xor:
-    _xor(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _xori(T, Src0R, Value);
+    } else {
+      _xor(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  case InstArithmetic::Sub:
-    _subu(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _addiu(T, Src0R, -Value);
+    } else {
+      _subu(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  case InstArithmetic::Mul: {
@@ -2585,7 +2630,11 @@ void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) {
    return;
  }
  case InstArithmetic::Shl: {
-    _sllv(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _sll(T, Src0R, Value);
+    } else {
+      _sllv(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  }
@@ -2595,15 +2644,25 @@ void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) {
    if (Dest->getType() != IceType_i32) {
      T0R = makeReg(IceType_i32);
      lowerCast(InstCast::create(Func, InstCast::Zext, T0R, Src0R));
-      T1R = makeReg(IceType_i32);
-      lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
+      if (!IsSrc1Imm16) {
+        T1R = makeReg(IceType_i32);
+        lowerCast(InstCast::create(Func, InstCast::Zext, T1R, Src1R));
+      }
+    }
+    if (IsSrc1Imm16) {
+      _srl(T, T0R, Value);
+    } else {
+      _srlv(T, T0R, T1R);
    }
-    _srlv(T, T0R, T1R);
    _mov(Dest, T);
    return;
  }
  case InstArithmetic::Ashr: {
-    _srav(T, Src0R, Src1R);
+    if (IsSrc1Imm16) {
+      _sra(T, Src0R, Value);
+    } else {
+      _srav(T, Src0R, Src1R);
+    }
    _mov(Dest, T);
    return;
  }

--- a/tests_lit/assembler/mips32/encoding_test_arith.ll
+++ b/tests_lit/assembler/mips32/encoding_test_arith.ll
@@ -32,68 +32,40 @@ define internal i32 @test_01(i32 %a) {

 ; ASM-LABEL: test_01:
 ; ASM-NEXT: .Ltest_01$__0:
-; ASM-NEXT:	# $zero = def.pseudo
-; ASM-NEXT:	addiu	$v0, $zero, 1
-; ASM-NEXT:	addu	$a0, $a0, $v0
-; ASM-NEXT:	# $zero = def.pseudo
-; ASM-NEXT:	addiu	$v0, $zero, 1
-; ASM-NEXT:	and	$a0, $a0, $v0
-; ASM-NEXT:	# $zero = def.pseudo
-; ASM-NEXT:	addiu	$v0, $zero, 1
-; ASM-NEXT:	or	$a0, $a0, $v0
-; ASM-NEXT:	# $zero = def.pseudo
-; ASM-NEXT:	addiu	$v0, $zero, 1
-; ASM-NEXT:	xor	$a0, $a0, $v0
+; ASM-NEXT:	addiu	$a0, $a0, 1
+; ASM-NEXT:	andi	$a0, $a0, 1
+; ASM-NEXT:	ori	$a0, $a0, 1
+; ASM-NEXT:	xori	$a0, $a0, 1
 ; ASM-NEXT:	move	$v0, $a0
 ; ASM-NEXT:	jr	$ra

 ; DIS-LABEL:00000000 <test_01>:
-; DIS-NEXT:   0:   24020001	li	v0,1
-; DIS-NEXT:   4:   00822021	addu	a0,a0,v0
-; DIS-NEXT:   8:   24020001	li	v0,1
-; DIS-NEXT:   c:   00822024	and	a0,a0,v0
-; DIS-NEXT:  10:   24020001	li	v0,1
-; DIS-NEXT:  14:   00822025	or	a0,a0,v0
-; DIS-NEXT:  18:   24020001	li	v0,1
-; DIS-NEXT:  1c:   00822026	xor	a0,a0,v0
-; DIS-NEXT:  20:   00801021	move	v0,a0
-; DIS-NEXT:  24:   03e00008	jr	ra
-; DIS-NEXT:  28:   00000000	nop
+; DIS-NEXT:   0:	24840001 	addiu	a0,a0,1
+; DIS-NEXT:   4:	30840001 	andi	a0,a0,0x1
+; DIS-NEXT:   8:	34840001 	ori	a0,a0,0x1
+; DIS-NEXT:   c:	38840001 	xori	a0,a0,0x1
+; DIS-NEXT:  10:	00801021 	move	v0,a0
+; DIS-NEXT:  14:	03e00008 	jr	ra
+; DIS-NEXT:  18:	00000000 	nop

 ; IASM-LABEL: test_01:
 ; IASM-LABEL: .Ltest_01$__0:
 ; IASM-NEXT:	.byte 0x1
 ; IASM-NEXT:	.byte 0x0
-; IASM-NEXT:	.byte 0x2
+; IASM-NEXT:	.byte 0x84
 ; IASM-NEXT:	.byte 0x24
-; IASM-NEXT:	.byte 0x21
-; IASM-NEXT:	.byte 0x20
-; IASM-NEXT:	.byte 0x82
-; IASM-NEXT:	.byte 0x0
 ; IASM-NEXT:	.byte 0x1
 ; IASM-NEXT:	.byte 0x0
-; IASM-NEXT:	.byte 0x2
-; IASM-NEXT:	.byte 0x24
-; IASM-NEXT:	.byte 0x24
-; IASM-NEXT:	.byte 0x20
-; IASM-NEXT:	.byte 0x82
-; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x84
+; IASM-NEXT:	.byte 0x30
 ; IASM-NEXT:	.byte 0x1
 ; IASM-NEXT:	.byte 0x0
-; IASM-NEXT:	.byte 0x2
-; IASM-NEXT:	.byte 0x24
-; IASM-NEXT:	.byte 0x25
-; IASM-NEXT:	.byte 0x20
-; IASM-NEXT:	.byte 0x82
-; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x84
+; IASM-NEXT:	.byte 0x34
 ; IASM-NEXT:	.byte 0x1
 ; IASM-NEXT:	.byte 0x0
-; IASM-NEXT:	.byte 0x2
-; IASM-NEXT:	.byte 0x24
-; IASM-NEXT:	.byte 0x26
-; IASM-NEXT:	.byte 0x20
-; IASM-NEXT:	.byte 0x82
-; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x84
+; IASM-NEXT:	.byte 0x38
 ; IASM-NEXT:	.byte 0x21
 ; IASM-NEXT:	.byte 0x10
 ; IASM-NEXT:	.byte 0x80
@@ -123,14 +95,14 @@ define internal i32 @test_02(i32 %a) {
 ; ASM-NEXT:	move	$v0, $a0
 ; ASM-NEXT:	jr	$ra

-; DIS-LABEL:00000030 <test_02>:
-; DIS-NEXT:  30:   24020009	li	v0,9
-; DIS-NEXT:  34:   00822026	xor	a0,a0,v0
-; DIS-NEXT:  38:   2c840001	sltiu	a0,a0,1
-; DIS-NEXT:  3c:   30840001	andi	a0,a0,0x1
-; DIS-NEXT:  40:   00801021	move	v0,a0
-; DIS-NEXT:  44:   03e00008	jr	ra
-; DIS-NEXT:  48:   00000000	nop
+; DIS-LABEL:00000020 <test_02>:
+; DIS-NEXT:   20:	24020009 	li	v0,9
+; DIS-NEXT:   24:	00822026 	xor	a0,a0,v0
+; DIS-NEXT:   28:	2c840001 	sltiu	a0,a0,1
+; DIS-NEXT:   2c:	30840001 	andi	a0,a0,0x1
+; DIS-NEXT:   30:	00801021 	move	v0,a0
+; DIS-NEXT:   34:	03e00008 	jr	ra
+; DIS-NEXT:   38:	00000000 	nop

 ; IASM-LABEL: test_02:
 ; IASM-LABEL: .Ltest_02$__0:
@@ -182,15 +154,19 @@ entry:

 ; IASM-LABEL: ashrImm:
 ; IASM-NEXT: .LashrImm$entry:
-; IASM-NEXT: 	.byte 0x7
-; IASM-NEXT: 	.byte 0x20
-; IASM-NEXT: 	.byte 0xa4
-; IASM-NEXT: 	.byte 0x0
-; IASM-NEXT: 	.byte 0x21
-; IASM-NEXT: 	.byte 0x10
-; IASM-NEXT: 	.byte 0x80
-; IASM-NEXT: 	.byte 0x0
-; IASM-NEXT: 	.byte 0x8
-; IASM-NEXT: 	.byte 0x0
-; IASM-NEXT: 	.byte 0xe0
-; IASM-NEXT: 	.byte 0x3
+; IASM-NEXT:	.byte 0x7
+; IASM-NEXT:	.byte 0x20
+; IASM-NEXT:	.byte 0xa4
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x21
+; IASM-NEXT:	.byte 0x10
+; IASM-NEXT:	.byte 0x80
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x8
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0xe0
+; IASM-NEXT:	.byte 0x3
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x0
--- a/tests_lit/llvm2ice_tests/8bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/8bit.pnacl.ll
@@ -49,8 +49,7 @@ entry:
 ; CHECK-LABEL: add8BitConst
 ; CHECK: add {{[abcd]l}}
 ; MIPS32-LABEL: add8BitConst
-; MIPS32: 	li
-; MIPS32: 	addu
+; MIPS32: 	addiu
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	move
 ; MIPS32: 	jr
@@ -83,8 +82,7 @@ entry:
 ; CHECK-LABEL: sub8BitConst
 ; CHECK: sub {{[abcd]l}}
 ; MIPS32-LABEL: sub8BitConst
-; MIPS32: 	li
-; MIPS32: 	subu
+; MIPS32: 	addiu   {{.*}},-123
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	move
 ; MIPS32: 	jr
@@ -306,8 +304,7 @@ entry:
 ; CHECK-LABEL: shl8BitConst
 ; CHECK: shl {{[abcd]l|BYTE PTR}},0x6
 ; MIPS32-LABEL: shl8BitConst
-; MIPS32: 	li
-; MIPS32: 	sllv
+; MIPS32: 	sll
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	move
 ; MIPS32: 	jr
@@ -340,8 +337,7 @@ entry:
 ; CHECK-LABEL: lshr8BitConst
 ; CHECK: shr {{[abcd]l|BYTE PTR}},0x6
 ; MIPS32-LABEL: lshr8BitConst
-; MIPS32: 	li
-; MIPS32: 	srlv
+; MIPS32: 	srl
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	move
 ; MIPS32: 	jr
@@ -374,8 +370,7 @@ entry:
 ; CHECK-LABEL: ashr8BitConst
 ; CHECK: sar {{[abcd]l|BYTE PTR}},0x6
 ; MIPS32-LABEL: ashr8BitConst
-; MIPS32: 	li
-; MIPS32: 	srav
+; MIPS32: 	sra
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	move
 ; MIPS32: 	jr
@@ -577,8 +572,7 @@ entry:
 ; CHECK: mov {{[a-d]l}},BYTE PTR
 ; MIPS32-LABEL: load_i8
 ; MIPS32: 	lb
-; MIPS32: 	li
-; MIPS32: 	subu
+; MIPS32: 	addiu	{{.*}},0
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	move
 ; MIPS32: 	jr
@@ -598,8 +592,7 @@ entry:
 ; MIPS32: 	lui
 ; MIPS32: 	addiu
 ; MIPS32: 	lb
-; MIPS32: 	li
-; MIPS32: 	subu
+; MIPS32: 	addiu	{{.*}},0
 ; MIPS32: 	andi	{{.*}},0xff
 ; MIPS32: 	jr
 ; MIPS32: 	nop

--- a/tests_lit/llvm2ice_tests/adv-switch-opt.ll
+++ b/tests_lit/llvm2ice_tests/adv-switch-opt.ll
@@ -55,19 +55,19 @@ sw.epilog:
 ; MIPS32: 	beq	[[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
 ; MIPS32: 	nop
 ; MIPS32: 	li	[[REG2:.*]],92
-; MIPS32: 	beq	[[REG1]],[[REG2]],7c <.LtestJumpTable$sw.bb1>
+; MIPS32: 	beq	[[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
 ; MIPS32: 	nop
 ; MIPS32: 	li	[[REG2:.*]],93
 ; MIPS32: 	beq	[[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
 ; MIPS32: 	nop
 ; MIPS32: 	li	[[REG2:.*]],99
-; MIPS32: 	beq	[[REG1]],[[REG2]],7c <.LtestJumpTable$sw.bb1>
+; MIPS32: 	beq	[[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
 ; MIPS32: 	nop
 ; MIPS32: 	li	[[REG2:.*]],98
 ; MIPS32: 	beq	[[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
 ; MIPS32: 	nop
 ; MIPS32: 	li	[[REG2:.*]],96
-; MIPS32: 	beq	[[REG1]],[[REG2]],7c <.LtestJumpTable$sw.bb1>
+; MIPS32: 	beq	[[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
 ; MIPS32: 	nop
 ; MIPS32: 	li	[[REG2:.*]],97
 ; MIPS32: 	beq	[[REG1]],[[REG2]],60 <.LtestJumpTable$split_entry_sw.epilog_0>

--- a/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
+++ b/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
@@ -32,47 +32,36 @@ entry:
 ; MIPS32P50N1: nop
 ; MIPS32P50N1: sw {{.*}}
 ; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: addiu {{.*}},1
 ; MIPS32P50N1: nop
-; MIPS32P50N1: addu {{.*}}
 ; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
 ; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: nop
-; MIPS32P50N1: li {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: addiu {{.*}},2
 ; MIPS32P50N1: nop
 ; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: nop
-; MIPS32P50N1: li {{.*}}
-; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: nop
+; MIPS32P50N1: addiu {{.*}},3
 ; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: nop
-; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: addiu {{.*}},-1
 ; MIPS32P50N1: nop
-; MIPS32P50N1: subu {{.*}}
 ; MIPS32P50N1: sw {{.*}}
 ; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: li {{.*}}
-; MIPS32P50N1: subu {{.*}}
-; MIPS32P50N1: sw {{.*}}
 ; MIPS32P50N1: nop
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: li {{.*}}
-; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: addiu {{.*}},-2
 ; MIPS32P50N1: nop
 ; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
 ; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
+; MIPS32P50N1: addiu {{.*}},-3
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: nop
 ; MIPS32P50N1: mul {{.*}}
-; MIPS32P50N1: nop
 ; MIPS32P50N1: sw {{.*}}
 ; MIPS32P50N1: lw {{.*}}
 ; MIPS32P50N1: nop
@@ -81,7 +70,9 @@ entry:
 ; MIPS32P50N1: mul {{.*}}
 ; MIPS32P50N1: nop
 ; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
 ; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
 ; MIPS32P50N1: addiu {{.*}}
 ; MIPS32P50N1: jr ra
 ; MIPS32P50N1: nop
@@ -104,10 +95,7 @@ entry:
 ; MIPS32P110N2: lw {{.*}}
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
-; MIPS32P110N2: li {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: addiu {{.*}},1
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: sw {{.*}}
@@ -116,10 +104,7 @@ entry:
 ; MIPS32P110N2: lw {{.*}}
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
-; MIPS32P110N2: li {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: addiu {{.*}},2
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: sw {{.*}}
@@ -128,10 +113,7 @@ entry:
 ; MIPS32P110N2: lw {{.*}}
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
-; MIPS32P110N2: li {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: addiu {{.*}},3
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: sw {{.*}}
@@ -140,10 +122,7 @@ entry:
 ; MIPS32P110N2: lw {{.*}}
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
-; MIPS32P110N2: li {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: addiu {{.*}},-1
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: sw {{.*}}
@@ -152,10 +131,7 @@ entry:
 ; MIPS32P110N2: lw {{.*}}
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
-; MIPS32P110N2: li {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: addiu {{.*}},-2
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: sw {{.*}}
@@ -164,10 +140,7 @@ entry:
 ; MIPS32P110N2: lw {{.*}}
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
-; MIPS32P110N2: li {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: addiu {{.*}},-3
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: nop
 ; MIPS32P110N2: sw {{.*}}

--- a/tests_lit/llvm2ice_tests/shift.ll
+++ b/tests_lit/llvm2ice_tests/shift.ll
@@ -82,7 +82,7 @@ entry:
 ; CHECK: shl {{.*}},0x1

 ; MIPS32-LABEL: shlImmLarge
-; MIPS32: sllv
+; MIPS32: sll

 define internal i32 @shlImmNeg(i32 %val) {
 entry:
@@ -93,7 +93,7 @@ entry:
 ; CHECK: shl {{.*}},0xff

 ; MIPS32-LABEL: shlImmNeg
-; MIPS32: sllv
+; MIPS32: sll

 define internal i32 @lshrImmLarge(i32 %val) {
 entry:
@@ -104,7 +104,7 @@ entry:
 ; CHECK: shr {{.*}},0x1

 ; MIPS32-LABEL: lshrImmLarge
-; MIPS32: srlv
+; MIPS32: srl

 define internal i32 @lshrImmNeg(i32 %val) {
 entry:
@@ -115,7 +115,7 @@ entry:
 ; CHECK: shr {{.*}},0xff

 ; MIPS32-LABEL: lshrImmNeg
-; MIPS32: srlv
+; MIPS32: srl

 define internal i32 @ashrImmLarge(i32 %val) {
 entry:
@@ -126,7 +126,7 @@ entry:
 ; CHECK: sar {{.*}},0x1

 ; MIPS32-LABEL: ashrImmLarge
-; MIPS32: srav
+; MIPS32: sra

 define internal i32 @ashrImmNeg(i32 %val) {
 entry:
@@ -137,7 +137,7 @@ entry:
 ; CHECK: sar {{.*}},0xff

 ; MIPS32-LABEL: ashrImmNeg
-; MIPS32: srav
+; MIPS32: sra

 define internal i64 @shlImm64One(i64 %val) {
 entry:

--- a/tests_lit/llvm2ice_tests/switch-opt.ll
+++ b/tests_lit/llvm2ice_tests/switch-opt.ll
@@ -66,7 +66,7 @@ sw.epilog:                                        ; preds = %sw.bb2, %sw.default
 ; MIPS32: beq	{{.*}},{{.*}},{{.*}} <[[SW_BB2]]>
 ; MIPS32: b	{{.*}} <[[SW_DEFAULT:.*]]>
 ; MIPS32: <[[SW_DEFAULT]]>
-; MIPS32: li	{{.*}},27
+; MIPS32: addiu	{{.*}},27
 ; MIPS32: b	{{.*}} <[[SW_EPILOG]]>
 ; MIPS32: <[[SW_BB1]]>
 ; MIPS32: li	{{.*}},21

--- a/tests_lit/llvm2ice_tests/test_i1.ll
+++ b/tests_lit/llvm2ice_tests/test_i1.ll
@@ -34,8 +34,7 @@ entry:
 ; ARM32-LABEL: testAndTrue
 ; ARM32: and {{.*}}, #1
 ; MIPS32-LABEL: testAndTrue
-; MIPS32: 	li	[[REG:.*]],1
-; MIPS32: 	and	{{.*}},[[REG]]
+; MIPS32: 	andi	{{.*}},0x1

 ; Test that or with true uses immediate 1, not -1.
 define internal i32 @testOrTrue(i32 %arg) {
@@ -50,8 +49,7 @@ entry:
 ; ARM32-LABEL: testOrTrue
 ; ARM32: orr {{.*}}, #1
 ; MIPS32-LABEL: testOrTrue
-; MIPS32: 	li	[[REG:.*]],1
-; MIPS32: 	or	{{.*}},[[REG]]
+; MIPS32: 	ori	{{.*}},0x1

 ; Test that xor with true uses immediate 1, not -1.
 define internal i32 @testXorTrue(i32 %arg) {
@@ -66,8 +64,7 @@ entry:
 ; ARM32-LABEL: testXorTrue
 ; ARM32: eor {{.*}}, #1
 ; MIPS32-LABEL: testXorTrue
-; MIPS32: 	li	[[REG:.*]],1
-; MIPS32: 	xor	{{.*}},[[REG]]
+; MIPS32: 	xori	{{.*}},0x1

 ; Test that trunc to i1 masks correctly.
 define internal i32 @testTrunc(i32 %arg) {

--- a/tests_lit/llvm2ice_tests/uncond_br.ll
+++ b/tests_lit/llvm2ice_tests/uncond_br.ll
@@ -22,6 +22,5 @@ target:

 ; MIPS32-LABEL: uncond1
 ; MIPS32: <.Luncond1$target>:
-; MIPS32: li
-; MIPS32: addu
+; MIPS32: addiu {{.*}},1
 ; MIPS32: b {{[0-9a-f]+}} <.Luncond1$target>