Add the RSC instruction to the ARM integrated assembler.

src/DartARM32/assembler_arm.cc

@@ -248,12 +248,12 @@ void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), SBC, 1, rn, rd, o);
 }
 
-
+#if 0
+// Moved to ARM32::AssemblerARM32::rsc()f
 void Assembler::rsc(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), RSC, 0, rn, rd, o);
 }
 
-#if 0
 // Moved to ARM32::AssemblerARM32::tst()
 void Assembler::tst(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), TST, 1, rn, R0, o);

src/DartARM32/assembler_arm.h

@@ -473,15 +473,16 @@ class Assembler : public ValueObject {
   void adc(Register rd, Register rn, Operand o, Condition cond = AL);
 
   void adcs(Register rd, Register rn, Operand o, Condition cond = AL);
-#endif
 
+  // Moved to ARM32::AssemblerARM32::sbc()
   void sbc(Register rd, Register rn, Operand o, Condition cond = AL);
 
+  // Moved to ARM32::AssemblerARM32::sbc()
   void sbcs(Register rd, Register rn, Operand o, Condition cond = AL);
 
+  // Moved to ARM32::AssemblerARM32::rsc()
   void rsc(Register rd, Register rn, Operand o, Condition cond = AL);
 
-#if 0
   // Moved to ARM32::AssemblerARM32::tst();
   void tst(Register rn, Operand o, Condition cond = AL);
 #endif

src/IceAssemblerARM32.cpp

@@ -1611,6 +1611,32 @@ void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn,
              RsbName);
 }
 
+void AssemblerARM32::rsc(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  // RSC (immediate) - ARM section A8.8.155, encoding A1:
+  //   rsc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
+  //
+  // cccc0010111snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
+  //
+  // RSC (register) - ARM section A8.8.156, encoding A1:
+  //   rsc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+  //
+  // cccc0000111snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, iiiii=shift, tt=ShiftKind, and s=SetFlags.
+  //
+  // RSC (register-shifted register) - ARM section A8.8.157, encoding A1:
+  //   rsc{s}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
+  //
+  // cccc0000111fnnnnddddssss0tt1mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, ssss=Rs, tt defined <type>, and f=SetFlags.
+  constexpr const char *RscName = "rsc";
+  constexpr IValueT RscOpcode = B2 | B1 | B0; // i.e. 0111.
+  emitType01(Cond, RscOpcode, OpRd, OpRn, OpSrc1, SetFlags, RdIsPcAndSetFlags,
+             RscName);
+}
+
 void AssemblerARM32::sxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *SxtName = "sxt";
@@ -1631,7 +1657,7 @@ void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
   //
   // Sub (Immediate) - ARM section A8.8.222, encoding A1:
   //    sub{s}<c> <Rd>, <Rn>, #<RotatedImm8>
-  // Sub (Sp minus immediate) - ARM section A8.*.225, encoding A1:
+  // Sub (Sp minus immediate) - ARM section A8.8.225, encoding A1:
   //    sub{s}<c> sp, <Rn>, #<RotatedImm8>
   //
   // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,

src/IceAssemblerARM32.h

@@ -261,6 +261,9 @@ public:
   void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
+  void rsc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+           bool SetFlags, CondARM32::Cond Cond);
+
   void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 

src/IceInstARM32.cpp

@@ -543,6 +543,13 @@ template <> void InstARM32Rsb::emitIAS(const Cfg *Func) const {
     emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32Rsc::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  Asm->rsc(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Sbc::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->sbc(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());

tests_lit/assembler/arm32/rsc.ll

+; Show that we know how to translate rsc
+
+; NOTE: We use -O2 to get rid of memory stores.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+define internal i64 @NegateI64(i64 %a) {
+; ASM-LABEL:NegateI64:
+; DIS-LABEL:00000000 <NegateI64>:
+; IASM-LABEL:NegateI64:
+
+entry:
+; ASM-NEXT:.LNegateI64$entry:
+; IASM-NEXT:.LNegateI64$entry:
+
+  %res = sub i64 0, %a
+
+; ASM-NEXT:     rsbs    r0, r0, #0
+; DIS-NEXT:   0:        e2700000
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x70
+; IASM-NEXT:	.byte 0xe2
+
+; ASM-NEXT:     rsc     r1, r1, #0
+; DIS-NEXT:   4:        e2e11000
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x10
+; IASM-NEXT:	.byte 0xe1
+; IASM-NEXT:	.byte 0xe2
+
+  ret i64 %res
+}