Skip to content

S
swiftshader
Commit 3b8a15ee by Karl Schimpf
Options

Add Sbc(register) and Sbc(immediate) to integrated ARM assembler.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1424213003 .
parent 5bff61c4
Showing with 140 additions and 19 deletions
src/IceAssemblerARM32.cpp
...@@ -529,6 +529,50 @@ void AssemblerARM32::mov(const Operand *OpRd, const Operand *OpSrc, ...@@ -529,6 +529,50 @@ void AssemblerARM32::mov(const Operand *OpRd, const Operand *OpSrc,
emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src); emitType01(Cond, kInstTypeDataImmediate, Mov, SetFlags, Rn, Rd, Src);
} }
void AssemblerARM32::sbc(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
IValueT Rd;
if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
return setNeedsTextFixup();
IValueT Rn;
if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
return setNeedsTextFixup();
constexpr IValueT Sbc = B2 | B1; // 0110
IValueT Src1Value;
// TODO(kschimpf) Other possible decodings of sbc.
switch (decodeOperand(OpSrc1, Src1Value)) {
default:
return setNeedsTextFixup();
case DecodedAsRegister: {
// SBC (register) - ARM section 18.8.162, encoding A1:
// sbc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
//
// cccc0000110snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
// mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
constexpr IValueT Imm5 = 0;
Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataRegister, Sbc, SetFlags, Rn, Rd, Src1Value);
return;
}
case DecodedAsRotatedImm8: {
// SBC (Immediate) - ARM section A8.8.161, encoding A1:
// sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
// s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
emitType01(Cond, kInstTypeDataImmediate, Sbc, SetFlags, Rn, Rd, Src1Value);
return;
}
};
}
void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress, void AssemblerARM32::str(const Operand *OpRt, const Operand *OpAddress,
CondARM32::Cond Cond) { CondARM32::Cond Cond) {
IValueT Rt; IValueT Rt;
......
src/IceAssemblerARM32.h
...@@ -139,6 +139,9 @@ public: ...@@ -139,6 +139,9 @@ public:
void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
bool SetFlags, CondARM32::Cond Cond);
void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
......
src/IceInstARM32.cpp
...@@ -361,6 +361,14 @@ void InstARM32ThreeAddrGPR<InstARM32::Add>::emitIAS(const Cfg *Func) const { ...@@ -361,6 +361,14 @@ void InstARM32ThreeAddrGPR<InstARM32::Add>::emitIAS(const Cfg *Func) const {
} }
template <> template <>
void InstARM32ThreeAddrGPR<InstARM32::Sbc>::emitIAS(const Cfg *Func) const {
ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
Asm->sbc(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
if (Asm->needsTextFixup())
emitUsingTextFixup(Func);
}
template <>
void InstARM32ThreeAddrGPR<InstARM32::Sub>::emitIAS(const Cfg *Func) const { void InstARM32ThreeAddrGPR<InstARM32::Sub>::emitIAS(const Cfg *Func) const {
ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
Asm->sub(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate()); Asm->sub(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
......
tests_lit/assembler/arm32/sub.ll
; Show that we know how to translate instruction sub. ; Show that we know how to translate sub.
; NOTE: We use -O2 to get rid of memory stores.
; REQUIRES: allow_dump ; REQUIRES: allow_dump
...@@ -18,24 +20,31 @@ ...@@ -18,24 +20,31 @@
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
define internal i32 @sub1FromR0(i32 %p) { define internal i32 @Sub1FromR0(i32 %p) {
%v = sub i32 %p, 1 %v = sub i32 %p, 1
ret i32 %v ret i32 %v
} }
; ASM-LABEL: sub1FromR0: ; ASM-LABEL: Sub1FromR0:
; ASM: sub r0, r0, #1 ; ASM-NEXT: .LSub1FromR0$__0:
; ASM: bx lr ; ASM-NEXT: sub r0, r0, #1
; ASM-NEXT: bx lr
; DIS-LABEL:00000000 <sub1FromR0>: ; DIS-LABEL:00000000 <Sub1FromR0>:
; DIS-NEXT: 0: e2400001 ; DIS-NEXT: 0: e2400001
; DIS-NEXT: 4: e12fff1e
; IASM-LABEL: sub1FromR0: ; IASM-LABEL: Sub1FromR0:
; IASM: .byte 0x1 ; IASM-LABEL: .LSub1FromR0$__0:
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x40 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xe2 ; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: .byte 0x1e
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x2f
; IASM-NEXT: .byte 0xe1
define internal i32 @Sub2Regs(i32 %p1, i32 %p2) { define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
%v = sub i32 %p1, %p2 %v = sub i32 %p1, %p2
...@@ -43,15 +52,72 @@ define internal i32 @Sub2Regs(i32 %p1, i32 %p2) { ...@@ -43,15 +52,72 @@ define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
} }
; ASM-LABEL: Sub2Regs: ; ASM-LABEL: Sub2Regs:
; ASM: sub r0, r0, r1 ; ASM-NEXT: .LSub2Regs$__0:
; ASM-NEXT: bx lr ; ASM-NEXT: sub r0, r0, r1
; ASM-NEXT: bx lr
; DIS-LABEL:00000010 <Sub2Regs>: ; DIS-LABEL:00000010 <Sub2Regs>:
; DIS-NEXT: 10: e0400001 ; DIS-NEXT: 10: e0400001
; DIS-NEXT: 14: e12fff1e
; IASM-LABEL: Sub2Regs: ; IASM-LABEL: Sub2Regs:
; IASM: .byte 0x1 ; IASM-NEXT: .LSub2Regs$__0:
; IASM-NEXT: .byte 0x0 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x40 ; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xe0 ; IASM-NEXT: .byte 0x40
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x1e
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x2f
; IASM-NEXT: .byte 0xe1
define internal i64 @SubI64FromR0R1(i64 %p) {
%v = sub i64 %p, 1
ret i64 %v
}
; ASM-LABEL:SubI64FromR0R1:
; ASM-NEXT:.LSubI64FromR0R1$__0:
; ASM-NEXT: subs r0, r0, #1
; ASM-NEXT: sbc r1, r1, #0
; DIS-LABEL:00000020 <SubI64FromR0R1>:
; DIS-NEXT: 20: e2500001
; DIS-NEXT: 24: e2c11000
; IASM-LABEL:SubI64FromR0R1:
; IASM-NEXT:.LSubI64FromR0R1$__0:
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x50
; IASM-NEXT: .byte 0xe2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0xc1
; IASM-NEXT: .byte 0xe2
define internal i64 @SubI64Regs(i64 %p1, i64 %p2) {
%v = sub i64 %p1, %p2
ret i64 %v
}
; ASM-LABEL:SubI64Regs:
; ASM-NEXT:.LSubI64Regs$__0:
; ASM-NEXT: subs r0, r0, r2
; ASM-NEXT: sbc r1, r1, r3
; DIS-LABEL:00000030 <SubI64Regs>:
; DIS-NEXT: 30: e0500002
; DIS-NEXT: 34: e0c11003
; IASM-LABEL:SubI64Regs:
; IASM-NEXT:.LSubI64Regs$__0:
; IASM-NEXT: .byte 0x2
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x50
; IASM-NEXT: .byte 0xe0
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0xc1
; IASM-NEXT: .byte 0xe0
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment