Subzero, MIPS32: Floating point load/store and format conversion instructions

src/IceInstMIPS32.cpp

@@ -60,20 +60,27 @@ const char *InstMIPS32::getWidthString(Type Ty) {
   return "TBD";
 }
 
-template <> const char *InstMIPS32Addiu::Opcode = "addiu";
-template <> const char *InstMIPS32Lui::Opcode = "lui";
-template <> const char *InstMIPS32La::Opcode = "la";
-// Three-addr ops
 template <> const char *InstMIPS32Add::Opcode = "add";
 template <> const char *InstMIPS32Add_d::Opcode = "add.d";
 template <> const char *InstMIPS32Add_s::Opcode = "add.s";
+template <> const char *InstMIPS32Addiu::Opcode = "addiu";
 template <> const char *InstMIPS32Addu::Opcode = "addu";
 template <> const char *InstMIPS32And::Opcode = "and";
 template <> const char *InstMIPS32Andi::Opcode = "andi";
+template <> const char *InstMIPS32Cvt_d_l::Opcode = "cvt.d.l";
+template <> const char *InstMIPS32Cvt_d_s::Opcode = "cvt.d.s";
+template <> const char *InstMIPS32Cvt_d_w::Opcode = "cvt.d.w";
+template <> const char *InstMIPS32Cvt_s_d::Opcode = "cvt.s.d";
+template <> const char *InstMIPS32Cvt_s_l::Opcode = "cvt.s.l";
+template <> const char *InstMIPS32Cvt_s_w::Opcode = "cvt.s.w";
 template <> const char *InstMIPS32Div::Opcode = "div";
 template <> const char *InstMIPS32Div_d::Opcode = "div.d";
 template <> const char *InstMIPS32Div_s::Opcode = "div.s";
 template <> const char *InstMIPS32Divu::Opcode = "divu";
+template <> const char *InstMIPS32La::Opcode = "la";
+template <> const char *InstMIPS32Ldc1::Opcode = "ldc1";
+template <> const char *InstMIPS32Lui::Opcode = "lui";
+template <> const char *InstMIPS32Lwc1::Opcode = "lwc1";
 template <> const char *InstMIPS32Mfc1::Opcode = "mfc1";
 template <> const char *InstMIPS32Mfhi::Opcode = "mfhi";
 template <> const char *InstMIPS32Mflo::Opcode = "mflo";
@@ -89,6 +96,7 @@ template <> const char *InstMIPS32Mult::Opcode = "mult";
 template <> const char *InstMIPS32Multu::Opcode = "multu";
 template <> const char *InstMIPS32Or::Opcode = "or";
 template <> const char *InstMIPS32Ori::Opcode = "ori";
+template <> const char *InstMIPS32Sdc1::Opcode = "sdc1";
 template <> const char *InstMIPS32Sll::Opcode = "sll";
 template <> const char *InstMIPS32Sllv::Opcode = "sllv";
 template <> const char *InstMIPS32Slt::Opcode = "slt";
@@ -104,6 +112,11 @@ template <> const char *InstMIPS32Sub_d::Opcode = "sub.d";
 template <> const char *InstMIPS32Sub_s::Opcode = "sub.s";
 template <> const char *InstMIPS32Subu::Opcode = "subu";
 template <> const char *InstMIPS32Sw::Opcode = "sw";
+template <> const char *InstMIPS32Swc1::Opcode = "swc1";
+template <> const char *InstMIPS32Trunc_l_d::Opcode = "trunc.l.d";
+template <> const char *InstMIPS32Trunc_l_s::Opcode = "trunc.l.s";
+template <> const char *InstMIPS32Trunc_w_d::Opcode = "trunc.w.d";
+template <> const char *InstMIPS32Trunc_w_s::Opcode = "trunc.w.s";
 template <> const char *InstMIPS32Xor::Opcode = "xor";
 template <> const char *InstMIPS32Xori::Opcode = "xori";
 

src/IceInstMIPS32.h

@@ -127,13 +127,22 @@ public:
     Andi,
     Br,
     Call,
+    Cvt_d_l,
+    Cvt_d_s,
+    Cvt_d_w,
+    Cvt_s_d,
+    Cvt_s_l,
+    Cvt_s_w,
     Div,
     Div_d,
     Div_s,
     Divu,
     La,
     Label,
+    Ldc1,
     Lui,
+    Lw,
+    Lwc1,
     Mfc1,
     Mfhi,
     Mflo,
@@ -151,6 +160,7 @@ public:
     Or,
     Ori,
     Ret,
+    Sdc1,
     Sll,
     Sllv,
     Slt,
@@ -166,6 +176,11 @@ public:
     Sub_s,
     Subu,
     Sw,
+    Swc1,
+    Trunc_l_d,
+    Trunc_l_s,
+    Trunc_w_d,
+    Trunc_w_s,
     Xor,
     Xori
   };
@@ -708,12 +723,21 @@ using InstMIPS32Addu = InstMIPS32ThreeAddrGPR<InstMIPS32::Addu>;
 using InstMIPS32Addiu = InstMIPS32Imm16<InstMIPS32::Addiu, true>;
 using InstMIPS32And = InstMIPS32ThreeAddrGPR<InstMIPS32::And>;
 using InstMIPS32Andi = InstMIPS32Imm16<InstMIPS32::Andi>;
+using InstMIPS32Cvt_d_s = InstMIPS32TwoAddrFPR<InstMIPS32::Cvt_d_s>;
+using InstMIPS32Cvt_d_l = InstMIPS32TwoAddrFPR<InstMIPS32::Cvt_d_l>;
+using InstMIPS32Cvt_d_w = InstMIPS32TwoAddrFPR<InstMIPS32::Cvt_d_w>;
+using InstMIPS32Cvt_s_d = InstMIPS32TwoAddrFPR<InstMIPS32::Cvt_s_d>;
+using InstMIPS32Cvt_s_l = InstMIPS32TwoAddrFPR<InstMIPS32::Cvt_s_l>;
+using InstMIPS32Cvt_s_w = InstMIPS32TwoAddrFPR<InstMIPS32::Cvt_s_w>;
 using InstMIPS32Div = InstMIPS32ThreeAddrGPR<InstMIPS32::Div>;
 using InstMIPS32Div_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Div_d>;
 using InstMIPS32Div_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Div_s>;
 using InstMIPS32Divu = InstMIPS32ThreeAddrGPR<InstMIPS32::Divu>;
-using InstMIPS32Lui = InstMIPS32Imm16<InstMIPS32::Lui>;
 using InstMIPS32La = InstMIPS32UnaryopGPR<InstMIPS32::La>;
+using InstMIPS32Ldc1 = InstMIPS32Memory<InstMIPS32::Ldc1>;
+using InstMIPS32Lui = InstMIPS32Imm16<InstMIPS32::Lui>;
+using InstMIPS32Lw = InstMIPS32Memory<InstMIPS32::Lwc1>;
+using InstMIPS32Lwc1 = InstMIPS32Memory<InstMIPS32::Lwc1>;
 using InstMIPS32Mfc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mfc1>;
 using InstMIPS32Mfhi = InstMIPS32UnaryopGPR<InstMIPS32::Mfhi>;
 using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>;
@@ -729,6 +753,7 @@ using InstMIPS32Mult = InstMIPS32ThreeAddrGPR<InstMIPS32::Mult>;
 using InstMIPS32Multu = InstMIPS32ThreeAddrGPR<InstMIPS32::Multu>;
 using InstMIPS32Or = InstMIPS32ThreeAddrGPR<InstMIPS32::Or>;
 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;
+using InstMIPS32Sdc1 = InstMIPS32Memory<InstMIPS32::Sdc1>;
 using InstMIPS32Sll = InstMIPS32Imm16<InstMIPS32::Sll>;
 using InstMIPS32Sllv = InstMIPS32ThreeAddrGPR<InstMIPS32::Sllv>;
 using InstMIPS32Slt = InstMIPS32ThreeAddrGPR<InstMIPS32::Slt>;
@@ -744,6 +769,11 @@ using InstMIPS32Sub_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Sub_d>;
 using InstMIPS32Sub_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Sub_s>;
 using InstMIPS32Subu = InstMIPS32ThreeAddrGPR<InstMIPS32::Subu>;
 using InstMIPS32Sw = InstMIPS32Memory<InstMIPS32::Sw>;
+using InstMIPS32Swc1 = InstMIPS32Memory<InstMIPS32::Swc1>;
+using InstMIPS32Trunc_l_d = InstMIPS32TwoAddrFPR<InstMIPS32::Trunc_l_d>;
+using InstMIPS32Trunc_l_s = InstMIPS32TwoAddrFPR<InstMIPS32::Trunc_l_s>;
+using InstMIPS32Trunc_w_d = InstMIPS32TwoAddrFPR<InstMIPS32::Trunc_w_d>;
+using InstMIPS32Trunc_w_s = InstMIPS32TwoAddrFPR<InstMIPS32::Trunc_w_s>;
 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;
 using InstMIPS32Xor = InstMIPS32ThreeAddrGPR<InstMIPS32::Xor>;
 using InstMIPS32Xori = InstMIPS32Imm16<InstMIPS32::Xori>;

src/IceTargetLoweringMIPS32.cpp

@@ -1120,9 +1120,11 @@ void TargetMIPS32::lowerCast(const InstCast *Instr) {
     break;
   }
   case InstCast::Fptrunc:
+    // Use _cvt_d_s
     UnimplementedLoweringError(this, Instr);
     break;
   case InstCast::Fpext: {
+    // Use _cvt_s_d
     UnimplementedLoweringError(this, Instr);
     break;
   }

src/IceTargetLoweringMIPS32.h

@@ -191,6 +191,30 @@ public:
     Context.insert<InstMIPS32Addiu>(Dest, Src, Imm);
   }
 
+  void _cvt_d_l(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Cvt_d_l>(Dest, Src);
+  }
+
+  void _cvt_d_s(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Cvt_d_s>(Dest, Src);
+  }
+
+  void _cvt_d_w(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Cvt_d_w>(Dest, Src);
+  }
+
+  void _cvt_s_d(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Cvt_s_d>(Dest, Src);
+  }
+
+  void _cvt_s_l(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Cvt_s_l>(Dest, Src);
+  }
+
+  void _cvt_s_w(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Cvt_s_w>(Dest, Src);
+  }
+
   void _div(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Div>(Dest, Src0, Src1);
   }
@@ -207,6 +231,14 @@ public:
     Context.insert<InstMIPS32Divu>(Dest, Src0, Src1);
   }
 
+  void _ldc1(Variable *Value, OperandMIPS32Mem *Mem) {
+    Context.insert<InstMIPS32Ldc1>(Value, Mem);
+  }
+
+  void _lwc1(Variable *Value, OperandMIPS32Mem *Mem) {
+    Context.insert<InstMIPS32Lwc1>(Value, Mem);
+  }
+
   void _lui(Variable *Dest, uint32_t Imm) {
     Context.insert<InstMIPS32Lui>(Dest, Imm);
   }
@@ -287,6 +319,10 @@ public:
     Context.insert<InstMIPS32Ori>(Dest, Src, Imm);
   }
 
+  void _sdc1(Variable *Value, OperandMIPS32Mem *Mem) {
+    Context.insert<InstMIPS32Sdc1>(Value, Mem);
+  }
+
   void _sll(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Sll>(Dest, Src, Imm);
   }
@@ -347,6 +383,26 @@ public:
     Context.insert<InstMIPS32Sw>(Value, Mem);
   }
 
+  void _swc1(Variable *Value, OperandMIPS32Mem *Mem) {
+    Context.insert<InstMIPS32Swc1>(Value, Mem);
+  }
+
+  void _trunc_l_d(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Trunc_l_d>(Dest, Src);
+  }
+
+  void _trunc_l_s(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Trunc_l_s>(Dest, Src);
+  }
+
+  void _trunc_w_d(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Trunc_w_d>(Dest, Src);
+  }
+
+  void _trunc_w_s(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Trunc_w_s>(Dest, Src);
+  }
+
   void _xor(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Xor>(Dest, Src0, Src1);
   }