Commit 453660ff by John Porto

Subzero. Buildable, non-functional TargetLoweringX8664.

This CL adds a TargetLoweringX8664 that inherits from TargetX86Base, but other than that it does nothing to generate runnable code. Things that need to be addressed in follow up CLs: 1) lowerCall 2) lowerArguments 3) lowerRet 4) addPrologue 5) addEpilogue 6) Native 64-bit arithmetic 7) 32- to 64-bit addressing (7) will be particularly interesting. Pointers in Pexes are always 32-bit wide, so pexes have a de facto 32-bit address space. In Sandboxed mode that's solved by using RZP (i.e., r15) as a base register. For native codegen, we still need to decide what to do -- very likely we will start targeting X32. NOTE: This CL also s/IceType_ForceRexW/RexTypeForceRexW/g because I forgot to do it in the X8664 assembler cl. BUG= https://code.google.com/p/nativeclient/issues/detail?id=4077 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1257643004.
parent 59f2d925
......@@ -192,6 +192,7 @@ SRCS = \
IceInstARM32.cpp \
IceInstMIPS32.cpp \
IceInstX8632.cpp \
IceInstX8664.cpp \
IceIntrinsics.cpp \
IceLiveness.cpp \
IceOperand.cpp \
......
......@@ -845,7 +845,7 @@ protected:
private:
static constexpr Type RexTypeIrrelevant = IceType_i32;
static constexpr Type IceType_ForceRexW = IceType_i64;
static constexpr Type RexTypeForceRexW = IceType_i64;
static constexpr typename Traits::GPRRegister RexRegIrrelevant =
Traits::GPRRegister::Encoded_Reg_eax;
......
......@@ -304,7 +304,7 @@ void AssemblerX86Base<Machine>::movsx(Type SrcTy,
typename Traits::GPRRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
bool ByteSized = isByteSizedType(SrcTy);
emitRexRB(IceType_ForceRexW, dst, SrcTy, src);
emitRexRB(RexTypeForceRexW, dst, SrcTy, src);
if (ByteSized || SrcTy == IceType_i16) {
emitUint8(0x0F);
emitUint8(ByteSized ? 0xBE : 0xBF);
......@@ -321,7 +321,7 @@ void AssemblerX86Base<Machine>::movsx(Type SrcTy,
const typename Traits::Address &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
bool ByteSized = isByteSizedType(SrcTy);
emitRex(SrcTy, src, IceType_ForceRexW, dst);
emitRex(SrcTy, src, RexTypeForceRexW, dst);
if (ByteSized || SrcTy == IceType_i16) {
emitUint8(0x0F);
emitUint8(ByteSized ? 0xBE : 0xBF);
......
//===- subzero/src/IceInstX8664.cpp - X86-64 instruction implementation ---===//
//
// The Subzero Code Generator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file defines X8664 specific data related to X8664 Instructions and
/// Instruction traits. These are declared in the IceTargetLoweringX8664Traits.h
/// header file.
///
/// This file also defines X8664 operand specific methods (dump and emit.)
///
//===----------------------------------------------------------------------===//
#include "IceInstX8664.h"
#include "IceAssemblerX8664.h"
#include "IceCfg.h"
#include "IceCfgNode.h"
#include "IceConditionCodesX8664.h"
#include "IceInst.h"
#include "IceRegistersX8664.h"
#include "IceTargetLoweringX8664.h"
#include "IceOperand.h"
namespace Ice {
namespace X86Internal {
const MachineTraits<TargetX8664>::InstBrAttributesType
MachineTraits<TargetX8664>::InstBrAttributes[] = {
#define X(tag, encode, opp, dump, emit) \
{ X8664::Traits::Cond::opp, dump, emit } \
,
ICEINSTX8664BR_TABLE
#undef X
};
const MachineTraits<TargetX8664>::InstCmppsAttributesType
MachineTraits<TargetX8664>::InstCmppsAttributes[] = {
#define X(tag, emit) \
{ emit } \
,
ICEINSTX8664CMPPS_TABLE
#undef X
};
const MachineTraits<TargetX8664>::TypeAttributesType
MachineTraits<TargetX8664>::TypeAttributes[] = {
#define X(tag, elementty, cvt, sdss, pack, width, fld) \
{ cvt, sdss, pack, width, fld } \
,
ICETYPEX8664_TABLE
#undef X
};
void MachineTraits<TargetX8664>::X86Operand::dump(const Cfg *,
Ostream &Str) const {
if (BuildDefs::dump())
Str << "<OperandX8664>";
}
MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
Variable *Base,
Constant *Offset,
Variable *Index,
uint16_t Shift)
: X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
Shift(Shift) {
assert(Shift <= 3);
Vars = nullptr;
NumVars = 0;
if (Base)
++NumVars;
if (Index)
++NumVars;
if (NumVars) {
Vars = Func->allocateArrayOf<Variable *>(NumVars);
SizeT I = 0;
if (Base)
Vars[I++] = Base;
if (Index)
Vars[I++] = Index;
assert(I == NumVars);
}
}
void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
Ostream &Str = Func->getContext()->getStrEmit();
// Emit as Offset(Base,Index,1<<Shift).
// Offset is emitted without the leading '$'.
// Omit the (Base,Index,1<<Shift) part if Base==nullptr.
if (!Offset) {
// No offset, emit nothing.
} else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
if (Base == nullptr || CI->getValue())
// Emit a non-zero offset without a leading '$'.
Str << CI->getValue();
} else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
CR->emitWithoutPrefix(Func->getTarget());
} else {
llvm_unreachable("Invalid offset type for x86 mem operand");
}
if (Base) {
Str << "(";
Base->emit(Func);
if (Index) {
Str << ",";
Index->emit(Func);
if (Shift)
Str << "," << (1u << Shift);
}
Str << ")";
}
}
void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
Ostream &Str) const {
if (!BuildDefs::dump())
return;
bool Dumped = false;
Str << "[";
if (Base) {
if (Func)
Base->dump(Func);
else
Base->dump(Str);
Dumped = true;
}
if (Index) {
assert(Base);
Str << "+";
if (Shift > 0)
Str << (1u << Shift) << "*";
if (Func)
Index->dump(Func);
else
Index->dump(Str);
Dumped = true;
}
// Pretty-print the Offset.
bool OffsetIsZero = false;
bool OffsetIsNegative = false;
if (!Offset) {
OffsetIsZero = true;
} else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
OffsetIsZero = (CI->getValue() == 0);
OffsetIsNegative = (static_cast<int32_t>(CI->getValue()) < 0);
} else {
assert(llvm::isa<ConstantRelocatable>(Offset));
}
if (Dumped) {
if (!OffsetIsZero) { // Suppress if Offset is known to be 0
if (!OffsetIsNegative) // Suppress if Offset is known to be negative
Str << "+";
Offset->dump(Func, Str);
}
} else {
// There is only the offset.
Offset->dump(Func, Str);
}
Str << "]";
}
MachineTraits<TargetX8664>::Address
MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
MachineTraits<TargetX8664>::Assembler *Asm) const {
int32_t Disp = 0;
AssemblerFixup *Fixup = nullptr;
// Determine the offset (is it relocatable?)
if (getOffset()) {
if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
Disp = static_cast<int32_t>(CI->getValue());
} else if (const auto CR =
llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
Disp = CR->getOffset();
Fixup = Asm->createFixup(llvm::ELF::R_386_32, CR);
} else {
llvm_unreachable("Unexpected offset type");
}
}
// Now convert to the various possible forms.
if (getBase() && getIndex()) {
return X8664::Traits::Address(
RegX8664::getEncodedGPR(getBase()->getRegNum()),
RegX8664::getEncodedGPR(getIndex()->getRegNum()),
X8664::Traits::ScaleFactor(getShift()), Disp);
} else if (getBase()) {
return X8664::Traits::Address(
RegX8664::getEncodedGPR(getBase()->getRegNum()), Disp);
} else if (getIndex()) {
return X8664::Traits::Address(
RegX8664::getEncodedGPR(getIndex()->getRegNum()),
X8664::Traits::ScaleFactor(getShift()), Disp);
} else if (Fixup) {
return X8664::Traits::Address::Absolute(Disp, Fixup);
} else {
return X8664::Traits::Address::Absolute(Disp);
}
}
MachineTraits<TargetX8664>::Address
MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
assert(!Var->hasReg());
const ::Ice::TargetLowering *Target = Func->getTarget();
int32_t Offset =
Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
return X8664::Traits::Address(
RegX8664::getEncodedGPR(Target->getFrameOrStackReg()), Offset);
}
void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
Ostream &Str = Func->getContext()->getStrEmit();
assert(!Var->hasReg());
// The following is copied/adapted from TargetX8664::emitVariable().
const ::Ice::TargetLowering *Target = Func->getTarget();
const Type Ty = IceType_i32;
int32_t Offset =
Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
if (Offset)
Str << Offset;
Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
}
void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
Ostream &Str) const {
if (!BuildDefs::dump())
return;
switch (Part) {
case Low:
Str << "low";
break;
case High:
Str << "high";
break;
}
Str << "(";
if (Func)
Var->dump(Func);
else
Var->dump(Str);
Str << ")";
}
} // namespace X86Internal
} // end of namespace Ice
X86INSTS_DEFINE_STATIC_DATA(TargetX8664);
//===- subzero/src/IceInstX8664.h - x86-64 machine instructions -*- C++ -*-===//
//
// The Subzero Code Generator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file used to house all the X8664 instructions. Subzero has been
/// modified to use templates for X86 instructions, so all those definitions are
/// are in IceInstX86Base.h
///
/// When interacting with the X8664 target (which should only happen in the
/// X8664 TargetLowering) clients have should use the Ice::X8664::Traits::Insts
/// traits, which hides all the template verboseness behind a type alias.
///
/// For example, to create an X8664 MOV Instruction, clients should do
///
/// ::Ice::X8664::Traits::Insts::Mov::create
///
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICEINSTX8664_H
#define SUBZERO_SRC_ICEINSTX8664_H
#include "IceDefs.h"
#include "IceInst.h"
#include "IceInstX86Base.h"
#include "IceOperand.h"
#include "IceTargetLoweringX8664Traits.h"
#endif // SUBZERO_SRC_ICEINSTX8664_H
......@@ -2788,8 +2788,10 @@ template <class Machine> struct Insts {
using StoreP = InstX86StoreP<Machine>;
using StoreQ = InstX86StoreQ<Machine>;
using Nop = InstX86Nop<Machine>;
using Fld = InstX86Fld<Machine>;
using Fstp = InstX86Fstp<Machine>;
template <typename T = typename InstX86Base<Machine>::Traits>
using Fld = typename std::enable_if<T::UsesX87, InstX86Fld<Machine>>::type;
template <typename T = typename InstX86Base<Machine>::Traits>
using Fstp = typename std::enable_if<T::UsesX87, InstX86Fstp<Machine>>::type;
using Pop = InstX86Pop<Machine>;
using Push = InstX86Push<Machine>;
using Ret = InstX86Ret<Machine>;
......
......@@ -41,7 +41,9 @@ public:
static TargetX8632 *create(Cfg *Func) { return new TargetX8632(Func); }
protected:
private:
friend class ::Ice::X86Internal::TargetX86Base<TargetX8632>;
Operand *createNaClReadTPSrcOperand() {
Constant *Zero = Ctx->getConstantZero(IceType_i32);
return Traits::X86OperandMem::create(Func, IceType_i32, nullptr, Zero,
......@@ -49,9 +51,6 @@ protected:
Traits::X86OperandMem::SegReg_GS);
}
private:
friend class ::Ice::X86Internal::TargetX86Base<TargetX8632>;
explicit TargetX8632(Cfg *Func) : TargetX86Base(Func) {}
};
......@@ -61,8 +60,10 @@ class TargetDataX8632 final : public TargetDataLowering {
TargetDataX8632 &operator=(const TargetDataX8632 &) = delete;
public:
~TargetDataX8632() override = default;
static std::unique_ptr<TargetDataLowering> create(GlobalContext *Ctx) {
return std::unique_ptr<TargetDataLowering>(new TargetDataX8632(Ctx));
return makeUnique<TargetDataX8632>(Ctx);
}
void lowerGlobals(const VariableDeclarationList &Vars,
......@@ -70,11 +71,10 @@ public:
void lowerConstants() override;
void lowerJumpTables() override;
protected:
explicit TargetDataX8632(GlobalContext *Ctx);
private:
~TargetDataX8632() override = default;
ENABLE_MAKE_UNIQUE;
explicit TargetDataX8632(GlobalContext *Ctx);
template <typename T> static void emitConstantPool(GlobalContext *Ctx);
};
......
......@@ -16,13 +16,18 @@
#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664_H
#define SUBZERO_SRC_ICETARGETLOWERINGX8664_H
#include "IceAssemblerX8664.h"
#include "IceCfg.h"
#include "IceGlobalContext.h"
#include "IceInstX8664.h"
#include "IceTargetLowering.h"
#include "IceTargetLoweringX8664Traits.h"
#include "IceTargetLoweringX86Base.h"
namespace Ice {
class TargetX8664 : public TargetLowering {
class TargetX8664 final
: public ::Ice::X86Internal::TargetX86Base<TargetX8664> {
TargetX8664() = delete;
TargetX8664(const TargetX8664 &) = delete;
TargetX8664 &operator=(const TargetX8664 &) = delete;
......@@ -31,10 +36,20 @@ class TargetX8664 : public TargetLowering {
const InstJumpTable *JumpTable) const override;
public:
static TargetX8664 *create(Cfg *Func);
static TargetX8664 *create(Cfg *Func) { return new TargetX8664(Func); }
private:
explicit TargetX8664(Cfg *Func) : TargetLowering(Func) {}
friend class ::Ice::X86Internal::TargetX86Base<TargetX8664>;
explicit TargetX8664(Cfg *Func)
: ::Ice::X86Internal::TargetX86Base<TargetX8664>(Func) {}
Operand *createNaClReadTPSrcOperand() {
Variable *TDB = makeReg(IceType_i32);
InstCall *Call = makeHelperCall(H_call_read_tp, TDB, 0);
lowerCall(Call);
return TDB;
}
};
class TargetDataX8664 : public TargetDataLowering {
......@@ -59,6 +74,7 @@ private:
ENABLE_MAKE_UNIQUE;
explicit TargetDataX8664(GlobalContext *Ctx) : TargetDataLowering(Ctx) {}
template <typename T> static void emitConstantPool(GlobalContext *Ctx);
};
class TargetHeaderX8664 : public TargetHeaderLowering {
......
......@@ -342,11 +342,25 @@ protected:
void _divss(Variable *Dest, Operand *Src0) {
Context.insert(Traits::Insts::Divss::create(Func, Dest, Src0));
}
void _fld(Operand *Src0) {
Context.insert(Traits::Insts::Fld::create(Func, Src0));
}
void _fstp(Variable *Dest) {
Context.insert(Traits::Insts::Fstp::create(Func, Dest));
template <typename T = Traits>
typename std::enable_if<T::UsesX87, void>::type _fld(Operand *Src0) {
Context.insert(Traits::Insts::template Fld<>::create(Func, Src0));
}
// TODO(jpp): when implementing the X8664 calling convention, make sure x8664
// does not invoke this method, and remove it.
template <typename T = Traits>
typename std::enable_if<!T::UsesX87, void>::type _fld(Operand *) {
llvm::report_fatal_error("fld is not available in x86-64");
}
template <typename T = Traits>
typename std::enable_if<T::UsesX87, void>::type _fstp(Variable *Dest) {
Context.insert(Traits::Insts::template Fstp<>::create(Func, Dest));
}
// TODO(jpp): when implementing the X8664 calling convention, make sure x8664
// does not invoke this method, and remove it.
template <typename T = Traits>
typename std::enable_if<!T::UsesX87, void>::type _fstp(Variable *) {
llvm::report_fatal_error("fstp is not available in x86-64");
}
void _idiv(Variable *Dest, Operand *Src0, Operand *Src1) {
Context.insert(Traits::Insts::Idiv::create(Func, Dest, Src0, Src1));
......
......@@ -31,6 +31,7 @@ protected:
using ByteRegister = AssemblerX8632::Traits::ByteRegister;
using Cond = AssemblerX8632::Traits::Cond;
using GPRRegister = AssemblerX8632::Traits::GPRRegister;
using Label = ::Ice::X86Internal::Label;
using Traits = AssemblerX8632::Traits;
using XmmRegister = AssemblerX8632::Traits::XmmRegister;
using X87STRegister = AssemblerX8632::Traits::X87STRegister;
......
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