Subzero. Buildable, non-functional TargetLoweringX8664.

Makefile.standalone

@@ -192,6 +192,7 @@ SRCS = \
 	IceInstARM32.cpp \
 	IceInstMIPS32.cpp \
 	IceInstX8632.cpp \
+	IceInstX8664.cpp \
 	IceIntrinsics.cpp \
 	IceLiveness.cpp \
 	IceOperand.cpp \

src/IceAssemblerX86Base.h

@@ -845,7 +845,7 @@ protected:
 
 private:
   static constexpr Type RexTypeIrrelevant = IceType_i32;
-  static constexpr Type IceType_ForceRexW = IceType_i64;
+  static constexpr Type RexTypeForceRexW = IceType_i64;
   static constexpr typename Traits::GPRRegister RexRegIrrelevant =
       Traits::GPRRegister::Encoded_Reg_eax;
 

src/IceAssemblerX86BaseImpl.h

@@ -304,7 +304,7 @@ void AssemblerX86Base<Machine>::movsx(Type SrcTy,
                                       typename Traits::GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   bool ByteSized = isByteSizedType(SrcTy);
-  emitRexRB(IceType_ForceRexW, dst, SrcTy, src);
+  emitRexRB(RexTypeForceRexW, dst, SrcTy, src);
   if (ByteSized || SrcTy == IceType_i16) {
     emitUint8(0x0F);
     emitUint8(ByteSized ? 0xBE : 0xBF);
@@ -321,7 +321,7 @@ void AssemblerX86Base<Machine>::movsx(Type SrcTy,
                                       const typename Traits::Address &src) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   bool ByteSized = isByteSizedType(SrcTy);
-  emitRex(SrcTy, src, IceType_ForceRexW, dst);
+  emitRex(SrcTy, src, RexTypeForceRexW, dst);
   if (ByteSized || SrcTy == IceType_i16) {
     emitUint8(0x0F);
     emitUint8(ByteSized ? 0xBE : 0xBF);

src/IceInstX8664.cpp

+//===- subzero/src/IceInstX8664.cpp - X86-64 instruction implementation ---===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file defines X8664 specific data related to X8664 Instructions and
+/// Instruction traits. These are declared in the IceTargetLoweringX8664Traits.h
+/// header file.
+///
+/// This file also defines X8664 operand specific methods (dump and emit.)
+///
+//===----------------------------------------------------------------------===//
+#include "IceInstX8664.h"
+
+#include "IceAssemblerX8664.h"
+#include "IceCfg.h"
+#include "IceCfgNode.h"
+#include "IceConditionCodesX8664.h"
+#include "IceInst.h"
+#include "IceRegistersX8664.h"
+#include "IceTargetLoweringX8664.h"
+#include "IceOperand.h"
+
+namespace Ice {
+
+namespace X86Internal {
+
+const MachineTraits<TargetX8664>::InstBrAttributesType
+    MachineTraits<TargetX8664>::InstBrAttributes[] = {
+#define X(tag, encode, opp, dump, emit)                                        \
+  { X8664::Traits::Cond::opp, dump, emit }                                     \
+  ,
+        ICEINSTX8664BR_TABLE
+#undef X
+};
+
+const MachineTraits<TargetX8664>::InstCmppsAttributesType
+    MachineTraits<TargetX8664>::InstCmppsAttributes[] = {
+#define X(tag, emit)                                                           \
+  { emit }                                                                     \
+  ,
+        ICEINSTX8664CMPPS_TABLE
+#undef X
+};
+
+const MachineTraits<TargetX8664>::TypeAttributesType
+    MachineTraits<TargetX8664>::TypeAttributes[] = {
+#define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
+  { cvt, sdss, pack, width, fld }                                              \
+  ,
+        ICETYPEX8664_TABLE
+#undef X
+};
+
+void MachineTraits<TargetX8664>::X86Operand::dump(const Cfg *,
+                                                  Ostream &Str) const {
+  if (BuildDefs::dump())
+    Str << "<OperandX8664>";
+}
+
+MachineTraits<TargetX8664>::X86OperandMem::X86OperandMem(Cfg *Func, Type Ty,
+                                                         Variable *Base,
+                                                         Constant *Offset,
+                                                         Variable *Index,
+                                                         uint16_t Shift)
+    : X86Operand(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
+      Shift(Shift) {
+  assert(Shift <= 3);
+  Vars = nullptr;
+  NumVars = 0;
+  if (Base)
+    ++NumVars;
+  if (Index)
+    ++NumVars;
+  if (NumVars) {
+    Vars = Func->allocateArrayOf<Variable *>(NumVars);
+    SizeT I = 0;
+    if (Base)
+      Vars[I++] = Base;
+    if (Index)
+      Vars[I++] = Index;
+    assert(I == NumVars);
+  }
+}
+
+void MachineTraits<TargetX8664>::X86OperandMem::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  // Emit as Offset(Base,Index,1<<Shift).
+  // Offset is emitted without the leading '$'.
+  // Omit the (Base,Index,1<<Shift) part if Base==nullptr.
+  if (!Offset) {
+    // No offset, emit nothing.
+  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+    if (Base == nullptr || CI->getValue())
+      // Emit a non-zero offset without a leading '$'.
+      Str << CI->getValue();
+  } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
+    CR->emitWithoutPrefix(Func->getTarget());
+  } else {
+    llvm_unreachable("Invalid offset type for x86 mem operand");
+  }
+
+  if (Base) {
+    Str << "(";
+    Base->emit(Func);
+    if (Index) {
+      Str << ",";
+      Index->emit(Func);
+      if (Shift)
+        Str << "," << (1u << Shift);
+    }
+    Str << ")";
+  }
+}
+
+void MachineTraits<TargetX8664>::X86OperandMem::dump(const Cfg *Func,
+                                                     Ostream &Str) const {
+  if (!BuildDefs::dump())
+    return;
+  bool Dumped = false;
+  Str << "[";
+  if (Base) {
+    if (Func)
+      Base->dump(Func);
+    else
+      Base->dump(Str);
+    Dumped = true;
+  }
+  if (Index) {
+    assert(Base);
+    Str << "+";
+    if (Shift > 0)
+      Str << (1u << Shift) << "*";
+    if (Func)
+      Index->dump(Func);
+    else
+      Index->dump(Str);
+    Dumped = true;
+  }
+  // Pretty-print the Offset.
+  bool OffsetIsZero = false;
+  bool OffsetIsNegative = false;
+  if (!Offset) {
+    OffsetIsZero = true;
+  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+    OffsetIsZero = (CI->getValue() == 0);
+    OffsetIsNegative = (static_cast<int32_t>(CI->getValue()) < 0);
+  } else {
+    assert(llvm::isa<ConstantRelocatable>(Offset));
+  }
+  if (Dumped) {
+    if (!OffsetIsZero) {     // Suppress if Offset is known to be 0
+      if (!OffsetIsNegative) // Suppress if Offset is known to be negative
+        Str << "+";
+      Offset->dump(Func, Str);
+    }
+  } else {
+    // There is only the offset.
+    Offset->dump(Func, Str);
+  }
+  Str << "]";
+}
+
+MachineTraits<TargetX8664>::Address
+MachineTraits<TargetX8664>::X86OperandMem::toAsmAddress(
+    MachineTraits<TargetX8664>::Assembler *Asm) const {
+  int32_t Disp = 0;
+  AssemblerFixup *Fixup = nullptr;
+  // Determine the offset (is it relocatable?)
+  if (getOffset()) {
+    if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
+      Disp = static_cast<int32_t>(CI->getValue());
+    } else if (const auto CR =
+                   llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
+      Disp = CR->getOffset();
+      Fixup = Asm->createFixup(llvm::ELF::R_386_32, CR);
+    } else {
+      llvm_unreachable("Unexpected offset type");
+    }
+  }
+
+  // Now convert to the various possible forms.
+  if (getBase() && getIndex()) {
+    return X8664::Traits::Address(
+        RegX8664::getEncodedGPR(getBase()->getRegNum()),
+        RegX8664::getEncodedGPR(getIndex()->getRegNum()),
+        X8664::Traits::ScaleFactor(getShift()), Disp);
+  } else if (getBase()) {
+    return X8664::Traits::Address(
+        RegX8664::getEncodedGPR(getBase()->getRegNum()), Disp);
+  } else if (getIndex()) {
+    return X8664::Traits::Address(
+        RegX8664::getEncodedGPR(getIndex()->getRegNum()),
+        X8664::Traits::ScaleFactor(getShift()), Disp);
+  } else if (Fixup) {
+    return X8664::Traits::Address::Absolute(Disp, Fixup);
+  } else {
+    return X8664::Traits::Address::Absolute(Disp);
+  }
+}
+
+MachineTraits<TargetX8664>::Address
+MachineTraits<TargetX8664>::VariableSplit::toAsmAddress(const Cfg *Func) const {
+  assert(!Var->hasReg());
+  const ::Ice::TargetLowering *Target = Func->getTarget();
+  int32_t Offset =
+      Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
+  return X8664::Traits::Address(
+      RegX8664::getEncodedGPR(Target->getFrameOrStackReg()), Offset);
+}
+
+void MachineTraits<TargetX8664>::VariableSplit::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  assert(!Var->hasReg());
+  // The following is copied/adapted from TargetX8664::emitVariable().
+  const ::Ice::TargetLowering *Target = Func->getTarget();
+  const Type Ty = IceType_i32;
+  int32_t Offset =
+      Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
+  if (Offset)
+    Str << Offset;
+  Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
+}
+
+void MachineTraits<TargetX8664>::VariableSplit::dump(const Cfg *Func,
+                                                     Ostream &Str) const {
+  if (!BuildDefs::dump())
+    return;
+  switch (Part) {
+  case Low:
+    Str << "low";
+    break;
+  case High:
+    Str << "high";
+    break;
+  }
+  Str << "(";
+  if (Func)
+    Var->dump(Func);
+  else
+    Var->dump(Str);
+  Str << ")";
+}
+
+} // namespace X86Internal
+} // end of namespace Ice
+
+X86INSTS_DEFINE_STATIC_DATA(TargetX8664);

src/IceInstX8664.h

+//===- subzero/src/IceInstX8664.h - x86-64 machine instructions -*- C++ -*-===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file used to house all the X8664 instructions. Subzero has been
+/// modified to use templates for X86 instructions, so all those definitions are
+/// are in IceInstX86Base.h
+///
+/// When interacting with the X8664 target (which should only happen in the
+/// X8664 TargetLowering) clients have should use the Ice::X8664::Traits::Insts
+/// traits, which hides all the template verboseness behind a type alias.
+///
+/// For example, to create an X8664 MOV Instruction, clients should do
+///
+/// ::Ice::X8664::Traits::Insts::Mov::create
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICEINSTX8664_H
+#define SUBZERO_SRC_ICEINSTX8664_H
+
+#include "IceDefs.h"
+#include "IceInst.h"
+#include "IceInstX86Base.h"
+#include "IceOperand.h"
+#include "IceTargetLoweringX8664Traits.h"
+
+#endif // SUBZERO_SRC_ICEINSTX8664_H

src/IceInstX86Base.h

@@ -2788,8 +2788,10 @@ template <class Machine> struct Insts {
   using StoreP = InstX86StoreP<Machine>;
   using StoreQ = InstX86StoreQ<Machine>;
   using Nop = InstX86Nop<Machine>;
-  using Fld = InstX86Fld<Machine>;
-  using Fstp = InstX86Fstp<Machine>;
+  template <typename T = typename InstX86Base<Machine>::Traits>
+  using Fld = typename std::enable_if<T::UsesX87, InstX86Fld<Machine>>::type;
+  template <typename T = typename InstX86Base<Machine>::Traits>
+  using Fstp = typename std::enable_if<T::UsesX87, InstX86Fstp<Machine>>::type;
   using Pop = InstX86Pop<Machine>;
   using Push = InstX86Push<Machine>;
   using Ret = InstX86Ret<Machine>;

src/IceTargetLoweringX8632.h

@@ -41,7 +41,9 @@ public:
 
   static TargetX8632 *create(Cfg *Func) { return new TargetX8632(Func); }
 
-protected:
+private:
+  friend class ::Ice::X86Internal::TargetX86Base<TargetX8632>;
+
   Operand *createNaClReadTPSrcOperand() {
     Constant *Zero = Ctx->getConstantZero(IceType_i32);
     return Traits::X86OperandMem::create(Func, IceType_i32, nullptr, Zero,
@@ -49,9 +51,6 @@ protected:
                                          Traits::X86OperandMem::SegReg_GS);
   }
 
-private:
-  friend class ::Ice::X86Internal::TargetX86Base<TargetX8632>;
-
   explicit TargetX8632(Cfg *Func) : TargetX86Base(Func) {}
 };
 
@@ -61,8 +60,10 @@ class TargetDataX8632 final : public TargetDataLowering {
   TargetDataX8632 &operator=(const TargetDataX8632 &) = delete;
 
 public:
+  ~TargetDataX8632() override = default;
+
   static std::unique_ptr<TargetDataLowering> create(GlobalContext *Ctx) {
-    return std::unique_ptr<TargetDataLowering>(new TargetDataX8632(Ctx));
+    return makeUnique<TargetDataX8632>(Ctx);
   }
 
   void lowerGlobals(const VariableDeclarationList &Vars,
@@ -70,11 +71,10 @@ public:
   void lowerConstants() override;
   void lowerJumpTables() override;
 
-protected:
-  explicit TargetDataX8632(GlobalContext *Ctx);
-
 private:
-  ~TargetDataX8632() override = default;
+  ENABLE_MAKE_UNIQUE;
+
+  explicit TargetDataX8632(GlobalContext *Ctx);
   template <typename T> static void emitConstantPool(GlobalContext *Ctx);
 };
 

src/IceTargetLoweringX8664.cpp

-//===- subzero/src/IceTargetLoweringX8664.cpp - lowering for x86-64 -------===//
+//===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
@@ -8,36 +8,391 @@
 //===----------------------------------------------------------------------===//
 ///
 /// \file
-/// Implements the Target Lowering for x86-64.
+/// This file implements the TargetLoweringX8664 class, which
+/// consists almost entirely of the lowering sequence for each
+/// high-level instruction.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "IceDefs.h"
 #include "IceTargetLoweringX8664.h"
 
+#include "IceTargetLoweringX8664Traits.h"
+#include "IceTargetLoweringX86Base.h"
+
 namespace Ice {
 
-void TargetX8664::emitJumpTable(const Cfg *Func,
-                                const InstJumpTable *JumpTable) const {
-  (void)Func;
-  (void)JumpTable;
-  llvm::report_fatal_error("Not yet implemented");
-}
+namespace X86Internal {
+const MachineTraits<TargetX8664>::TableFcmpType
+    MachineTraits<TargetX8664>::TableFcmp[] = {
+#define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
+  {                                                                            \
+    dflt, swapS, X8664::Traits::Cond::C1, X8664::Traits::Cond::C2, swapV,      \
+        X8664::Traits::Cond::pred                                              \
+  }                                                                            \
+  ,
+        FCMPX8664_TABLE
+#undef X
+};
 
-TargetX8664 *TargetX8664::create(Cfg *) {
-  llvm::report_fatal_error("Not yet implemented");
-}
-void TargetDataX8664::lowerGlobals(const VariableDeclarationList &,
-                                   const IceString &) {
-  llvm::report_fatal_error("Not yet implemented");
+const size_t MachineTraits<TargetX8664>::TableFcmpSize =
+    llvm::array_lengthof(TableFcmp);
+
+const MachineTraits<TargetX8664>::TableIcmp32Type
+    MachineTraits<TargetX8664>::TableIcmp32[] = {
+#define X(val, C_32, C1_64, C2_64, C3_64)                                      \
+  { X8664::Traits::Cond::C_32 }                                                \
+  ,
+        ICMPX8664_TABLE
+#undef X
+};
+
+const size_t MachineTraits<TargetX8664>::TableIcmp32Size =
+    llvm::array_lengthof(TableIcmp32);
+
+const MachineTraits<TargetX8664>::TableIcmp64Type
+    MachineTraits<TargetX8664>::TableIcmp64[] = {
+#define X(val, C_32, C1_64, C2_64, C3_64)                                      \
+  {                                                                            \
+    X8664::Traits::Cond::C1_64, X8664::Traits::Cond::C2_64,                    \
+        X8664::Traits::Cond::C3_64                                             \
+  }                                                                            \
+  ,
+        ICMPX8664_TABLE
+#undef X
+};
+
+const size_t MachineTraits<TargetX8664>::TableIcmp64Size =
+    llvm::array_lengthof(TableIcmp64);
+
+const MachineTraits<TargetX8664>::TableTypeX8664AttributesType
+    MachineTraits<TargetX8664>::TableTypeX8664Attributes[] = {
+#define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
+  { elementty }                                                                \
+  ,
+        ICETYPEX8664_TABLE
+#undef X
+};
+
+const size_t MachineTraits<TargetX8664>::TableTypeX8664AttributesSize =
+    llvm::array_lengthof(TableTypeX8664Attributes);
+
+const uint32_t MachineTraits<TargetX8664>::X86_STACK_ALIGNMENT_BYTES = 16;
+const char *MachineTraits<TargetX8664>::TargetName = "X8664";
+
+} // end of namespace X86Internal
+
+namespace {
+template <typename T> struct PoolTypeConverter {};
+
+template <> struct PoolTypeConverter<float> {
+  typedef uint32_t PrimitiveIntType;
+  typedef ConstantFloat IceType;
+  static const Type Ty = IceType_f32;
+  static const char *TypeName;
+  static const char *AsmTag;
+  static const char *PrintfString;
+};
+const char *PoolTypeConverter<float>::TypeName = "float";
+const char *PoolTypeConverter<float>::AsmTag = ".long";
+const char *PoolTypeConverter<float>::PrintfString = "0x%x";
+
+template <> struct PoolTypeConverter<double> {
+  typedef uint64_t PrimitiveIntType;
+  typedef ConstantDouble IceType;
+  static const Type Ty = IceType_f64;
+  static const char *TypeName;
+  static const char *AsmTag;
+  static const char *PrintfString;
+};
+const char *PoolTypeConverter<double>::TypeName = "double";
+const char *PoolTypeConverter<double>::AsmTag = ".quad";
+const char *PoolTypeConverter<double>::PrintfString = "0x%llx";
+
+// Add converter for int type constant pooling
+template <> struct PoolTypeConverter<uint32_t> {
+  typedef uint32_t PrimitiveIntType;
+  typedef ConstantInteger32 IceType;
+  static const Type Ty = IceType_i32;
+  static const char *TypeName;
+  static const char *AsmTag;
+  static const char *PrintfString;
+};
+const char *PoolTypeConverter<uint32_t>::TypeName = "i32";
+const char *PoolTypeConverter<uint32_t>::AsmTag = ".long";
+const char *PoolTypeConverter<uint32_t>::PrintfString = "0x%x";
+
+// Add converter for int type constant pooling
+template <> struct PoolTypeConverter<uint16_t> {
+  typedef uint32_t PrimitiveIntType;
+  typedef ConstantInteger32 IceType;
+  static const Type Ty = IceType_i16;
+  static const char *TypeName;
+  static const char *AsmTag;
+  static const char *PrintfString;
+};
+const char *PoolTypeConverter<uint16_t>::TypeName = "i16";
+const char *PoolTypeConverter<uint16_t>::AsmTag = ".short";
+const char *PoolTypeConverter<uint16_t>::PrintfString = "0x%x";
+
+// Add converter for int type constant pooling
+template <> struct PoolTypeConverter<uint8_t> {
+  typedef uint32_t PrimitiveIntType;
+  typedef ConstantInteger32 IceType;
+  static const Type Ty = IceType_i8;
+  static const char *TypeName;
+  static const char *AsmTag;
+  static const char *PrintfString;
+};
+const char *PoolTypeConverter<uint8_t>::TypeName = "i8";
+const char *PoolTypeConverter<uint8_t>::AsmTag = ".byte";
+const char *PoolTypeConverter<uint8_t>::PrintfString = "0x%x";
+} // end of anonymous namespace
+
+template <typename T>
+void TargetDataX8664::emitConstantPool(GlobalContext *Ctx) {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Ctx->getStrEmit();
+  Type Ty = T::Ty;
+  SizeT Align = typeAlignInBytes(Ty);
+  ConstantList Pool = Ctx->getConstantPool(Ty);
+
+  Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",@progbits," << Align
+      << "\n";
+  Str << "\t.align\t" << Align << "\n";
+
+  // If reorder-pooled-constants option is set to true, we need to shuffle the
+  // constant pool before emitting it.
+  if (Ctx->getFlags().shouldReorderPooledConstants())
+    RandomShuffle(Pool.begin(), Pool.end(), [Ctx](uint64_t N) {
+      return (uint32_t)Ctx->getRNG().next(N);
+    });
+
+  for (Constant *C : Pool) {
+    if (!C->getShouldBePooled())
+      continue;
+    typename T::IceType *Const = llvm::cast<typename T::IceType>(C);
+    typename T::IceType::PrimType Value = Const->getValue();
+    // Use memcpy() to copy bits from Value into RawValue in a way
+    // that avoids breaking strict-aliasing rules.
+    typename T::PrimitiveIntType RawValue;
+    memcpy(&RawValue, &Value, sizeof(Value));
+    char buf[30];
+    int CharsPrinted =
+        snprintf(buf, llvm::array_lengthof(buf), T::PrintfString, RawValue);
+    assert(CharsPrinted >= 0 &&
+           (size_t)CharsPrinted < llvm::array_lengthof(buf));
+    (void)CharsPrinted; // avoid warnings if asserts are disabled
+    Const->emitPoolLabel(Str);
+    Str << ":\n\t" << T::AsmTag << "\t" << buf << "\t# " << T::TypeName << " "
+        << Value << "\n";
+  }
 }
 
 void TargetDataX8664::lowerConstants() {
-  llvm::report_fatal_error("Not yet implemented");
+  if (Ctx->getFlags().getDisableTranslation())
+    return;
+  // No need to emit constants from the int pool since (for x86) they
+  // are embedded as immediates in the instructions, just emit float/double.
+  switch (Ctx->getFlags().getOutFileType()) {
+  case FT_Elf: {
+    ELFObjectWriter *Writer = Ctx->getObjectWriter();
+
+    Writer->writeConstantPool<ConstantInteger32>(IceType_i8);
+    Writer->writeConstantPool<ConstantInteger32>(IceType_i16);
+    Writer->writeConstantPool<ConstantInteger32>(IceType_i32);
+
+    Writer->writeConstantPool<ConstantFloat>(IceType_f32);
+    Writer->writeConstantPool<ConstantDouble>(IceType_f64);
+  } break;
+  case FT_Asm:
+  case FT_Iasm: {
+    OstreamLocker L(Ctx);
+
+    emitConstantPool<PoolTypeConverter<uint8_t>>(Ctx);
+    emitConstantPool<PoolTypeConverter<uint16_t>>(Ctx);
+    emitConstantPool<PoolTypeConverter<uint32_t>>(Ctx);
+
+    emitConstantPool<PoolTypeConverter<float>>(Ctx);
+    emitConstantPool<PoolTypeConverter<double>>(Ctx);
+  } break;
+  }
+}
+
+void TargetX8664::emitJumpTable(const Cfg *Func,
+                                const InstJumpTable *JumpTable) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Ctx->getStrEmit();
+  IceString MangledName = Ctx->mangleName(Func->getFunctionName());
+  Str << "\t.section\t.rodata." << MangledName
+      << "$jumptable,\"a\",@progbits\n";
+  Str << "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n";
+  Str << InstJumpTable::makeName(MangledName, JumpTable->getId()) << ":";
+
+  // On X8664 ILP32 pointers are 32-bit hence the use of .long
+  for (SizeT I = 0; I < JumpTable->getNumTargets(); ++I)
+    Str << "\n\t.long\t" << JumpTable->getTarget(I)->getAsmName();
+  Str << "\n";
 }
 
 void TargetDataX8664::lowerJumpTables() {
-  llvm::report_fatal_error("Not yet implemented");
+  switch (Ctx->getFlags().getOutFileType()) {
+  case FT_Elf: {
+    ELFObjectWriter *Writer = Ctx->getObjectWriter();
+    for (const JumpTableData &JumpTable : *Ctx->getJumpTables())
+      // TODO(jpp): not 386.
+      Writer->writeJumpTable(JumpTable, llvm::ELF::R_386_32);
+  } break;
+  case FT_Asm:
+    // Already emitted from Cfg
+    break;
+  case FT_Iasm: {
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Ctx->getStrEmit();
+    for (const JumpTableData &JT : *Ctx->getJumpTables()) {
+      Str << "\t.section\t.rodata." << JT.getFunctionName()
+          << "$jumptable,\"a\",@progbits\n";
+      Str << "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n";
+      Str << InstJumpTable::makeName(JT.getFunctionName(), JT.getId()) << ":";
+
+      // On X8664 ILP32 pointers are 32-bit hence the use of .long
+      for (intptr_t TargetOffset : JT.getTargetOffsets())
+        Str << "\n\t.long\t" << JT.getFunctionName() << "+" << TargetOffset;
+      Str << "\n";
+    }
+  } break;
+  }
+}
+
+void TargetDataX8664::lowerGlobals(const VariableDeclarationList &Vars,
+                                   const IceString &SectionSuffix) {
+  switch (Ctx->getFlags().getOutFileType()) {
+  case FT_Elf: {
+    ELFObjectWriter *Writer = Ctx->getObjectWriter();
+    // TODO(jpp): not 386.
+    Writer->writeDataSection(Vars, llvm::ELF::R_386_32, SectionSuffix);
+  } break;
+  case FT_Asm:
+  case FT_Iasm: {
+    const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly();
+    OstreamLocker L(Ctx);
+    for (const VariableDeclaration *Var : Vars) {
+      if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
+        emitGlobal(*Var, SectionSuffix);
+      }
+    }
+  } break;
+  }
 }
 
+// In some cases, there are x-macros tables for both high-level and
+// low-level instructions/operands that use the same enum key value.
+// The tables are kept separate to maintain a proper separation
+// between abstraction layers.  There is a risk that the tables could
+// get out of sync if enum values are reordered or if entries are
+// added or deleted.  The following dummy namespaces use
+// static_asserts to ensure everything is kept in sync.
+
+namespace {
+// Validate the enum values in FCMPX8664_TABLE.
+namespace dummy1 {
+// Define a temporary set of enum values based on low-level table
+// entries.
+enum _tmp_enum {
+#define X(val, dflt, swapS, C1, C2, swapV, pred) _tmp_##val,
+  FCMPX8664_TABLE
+#undef X
+      _num
+};
+// Define a set of constants based on high-level table entries.
+#define X(tag, str) static const int _table1_##tag = InstFcmp::tag;
+ICEINSTFCMP_TABLE
+#undef X
+// Define a set of constants based on low-level table entries, and
+// ensure the table entry keys are consistent.
+#define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
+  static const int _table2_##val = _tmp_##val;                                 \
+  static_assert(                                                               \
+      _table1_##val == _table2_##val,                                          \
+      "Inconsistency between FCMPX8664_TABLE and ICEINSTFCMP_TABLE");
+FCMPX8664_TABLE
+#undef X
+// Repeat the static asserts with respect to the high-level table
+// entries in case the high-level table has extra entries.
+#define X(tag, str)                                                            \
+  static_assert(                                                               \
+      _table1_##tag == _table2_##tag,                                          \
+      "Inconsistency between FCMPX8664_TABLE and ICEINSTFCMP_TABLE");
+ICEINSTFCMP_TABLE
+#undef X
+} // end of namespace dummy1
+
+// Validate the enum values in ICMPX8664_TABLE.
+namespace dummy2 {
+// Define a temporary set of enum values based on low-level table
+// entries.
+enum _tmp_enum {
+#define X(val, C_32, C1_64, C2_64, C3_64) _tmp_##val,
+  ICMPX8664_TABLE
+#undef X
+      _num
+};
+// Define a set of constants based on high-level table entries.
+#define X(tag, str) static const int _table1_##tag = InstIcmp::tag;
+ICEINSTICMP_TABLE
+#undef X
+// Define a set of constants based on low-level table entries, and
+// ensure the table entry keys are consistent.
+#define X(val, C_32, C1_64, C2_64, C3_64)                                      \
+  static const int _table2_##val = _tmp_##val;                                 \
+  static_assert(                                                               \
+      _table1_##val == _table2_##val,                                          \
+      "Inconsistency between ICMPX8664_TABLE and ICEINSTICMP_TABLE");
+ICMPX8664_TABLE
+#undef X
+// Repeat the static asserts with respect to the high-level table
+// entries in case the high-level table has extra entries.
+#define X(tag, str)                                                            \
+  static_assert(                                                               \
+      _table1_##tag == _table2_##tag,                                          \
+      "Inconsistency between ICMPX8664_TABLE and ICEINSTICMP_TABLE");
+ICEINSTICMP_TABLE
+#undef X
+} // end of namespace dummy2
+
+// Validate the enum values in ICETYPEX8664_TABLE.
+namespace dummy3 {
+// Define a temporary set of enum values based on low-level table
+// entries.
+enum _tmp_enum {
+#define X(tag, elementty, cvt, sdss, pack, width, fld) _tmp_##tag,
+  ICETYPEX8664_TABLE
+#undef X
+      _num
+};
+// Define a set of constants based on high-level table entries.
+#define X(tag, sizeLog2, align, elts, elty, str)                               \
+  static const int _table1_##tag = tag;
+ICETYPE_TABLE
+#undef X
+// Define a set of constants based on low-level table entries, and
+// ensure the table entry keys are consistent.
+#define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
+  static const int _table2_##tag = _tmp_##tag;                                 \
+  static_assert(_table1_##tag == _table2_##tag,                                \
+                "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE");
+ICETYPEX8664_TABLE
+#undef X
+// Repeat the static asserts with respect to the high-level table
+// entries in case the high-level table has extra entries.
+#define X(tag, sizeLog2, align, elts, elty, str)                               \
+  static_assert(_table1_##tag == _table2_##tag,                                \
+                "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE");
+ICETYPE_TABLE
+#undef X
+} // end of namespace dummy3
+} // end of anonymous namespace
+
 } // end of namespace Ice

src/IceTargetLoweringX8664.h

@@ -16,13 +16,18 @@
 #ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664_H
 #define SUBZERO_SRC_ICETARGETLOWERINGX8664_H
 
+#include "IceAssemblerX8664.h"
 #include "IceCfg.h"
 #include "IceGlobalContext.h"
+#include "IceInstX8664.h"
 #include "IceTargetLowering.h"
+#include "IceTargetLoweringX8664Traits.h"
+#include "IceTargetLoweringX86Base.h"
 
 namespace Ice {
 
-class TargetX8664 : public TargetLowering {
+class TargetX8664 final
+    : public ::Ice::X86Internal::TargetX86Base<TargetX8664> {
   TargetX8664() = delete;
   TargetX8664(const TargetX8664 &) = delete;
   TargetX8664 &operator=(const TargetX8664 &) = delete;
@@ -31,10 +36,20 @@ class TargetX8664 : public TargetLowering {
                      const InstJumpTable *JumpTable) const override;
 
 public:
-  static TargetX8664 *create(Cfg *Func);
+  static TargetX8664 *create(Cfg *Func) { return new TargetX8664(Func); }
 
 private:
-  explicit TargetX8664(Cfg *Func) : TargetLowering(Func) {}
+  friend class ::Ice::X86Internal::TargetX86Base<TargetX8664>;
+
+  explicit TargetX8664(Cfg *Func)
+      : ::Ice::X86Internal::TargetX86Base<TargetX8664>(Func) {}
+
+  Operand *createNaClReadTPSrcOperand() {
+    Variable *TDB = makeReg(IceType_i32);
+    InstCall *Call = makeHelperCall(H_call_read_tp, TDB, 0);
+    lowerCall(Call);
+    return TDB;
+  }
 };
 
 class TargetDataX8664 : public TargetDataLowering {
@@ -59,6 +74,7 @@ private:
   ENABLE_MAKE_UNIQUE;
 
   explicit TargetDataX8664(GlobalContext *Ctx) : TargetDataLowering(Ctx) {}
+  template <typename T> static void emitConstantPool(GlobalContext *Ctx);
 };
 
 class TargetHeaderX8664 : public TargetHeaderLowering {

src/IceTargetLoweringX8664Traits.h

@@ -23,6 +23,7 @@
 #include "IceOperand.h"
 #include "IceRegistersX8664.h"
 #include "IceTargetLowering.h"
+#include "IceTargetLoweringX8664.def"
 
 namespace Ice {
 
@@ -36,6 +37,7 @@ namespace X86Internal {
 
 template <class Machine> struct Insts;
 template <class Machine> struct MachineTraits;
+template <class Machine> class TargetX86Base;
 
 template <> struct MachineTraits<TargetX8664> {
   //----------------------------------------------------------------------------
@@ -282,7 +284,425 @@ template <> struct MachineTraits<TargetX8664> {
   //      \/_____/\/_____/\/_/   \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/
   //
   //----------------------------------------------------------------------------
+  enum InstructionSet {
+    Begin,
+    // SSE2 is the PNaCl baseline instruction set.
+    SSE2 = Begin,
+    SSE4_1,
+    End
+  };
+
+  static const char *TargetName;
+
+  static IceString getRegName(SizeT RegNum, Type Ty) {
+    assert(RegNum < RegisterSet::Reg_NUM);
+    static const struct {
+      const char *const Name8;
+      const char *const Name16;
+      const char *const Name /*32*/;
+      const char *const Name64;
+    } RegNames[] = {
+#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
+          stackptr, frameptr, isInt, isFP)                                     \
+  { name8, name16, name32, name64 }                                            \
+  ,
+        REGX8664_TABLE
+#undef X
+    };
+
+    switch (Ty) {
+    case IceType_i1:
+    case IceType_i8:
+      return RegNames[RegNum].Name8;
+    case IceType_i16:
+      return RegNames[RegNum].Name16;
+    case IceType_i64:
+      return RegNames[RegNum].Name64;
+    default:
+      return RegNames[RegNum].Name;
+    }
+  }
+
+  static void initRegisterSet(llvm::SmallBitVector *IntegerRegisters,
+                              llvm::SmallBitVector *IntegerRegistersI8,
+                              llvm::SmallBitVector *FloatRegisters,
+                              llvm::SmallBitVector *VectorRegisters,
+                              llvm::SmallBitVector *ScratchRegs) {
+#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
+          stackptr, frameptr, isInt, isFP)                                     \
+  (*IntegerRegisters)[RegisterSet::val] = isInt;                               \
+  (*IntegerRegistersI8)[RegisterSet::val] = 1;                                 \
+  (*FloatRegisters)[RegisterSet::val] = isFP;                                  \
+  (*VectorRegisters)[RegisterSet::val] = isFP;                                 \
+  (*ScratchRegs)[RegisterSet::val] = scratch;
+    REGX8664_TABLE;
+#undef X
+  }
+
+  static llvm::SmallBitVector
+  getRegisterSet(TargetLowering::RegSetMask Include,
+                 TargetLowering::RegSetMask Exclude) {
+    llvm::SmallBitVector Registers(RegisterSet::Reg_NUM);
+
+#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
+          stackptr, frameptr, isInt, isFP)                                     \
+  if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave))         \
+    Registers[RegisterSet::val] = true;                                        \
+  if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave))       \
+    Registers[RegisterSet::val] = true;                                        \
+  if (stackptr && (Include & ::Ice::TargetLowering::RegSet_StackPointer))      \
+    Registers[RegisterSet::val] = true;                                        \
+  if (frameptr && (Include & ::Ice::TargetLowering::RegSet_FramePointer))      \
+    Registers[RegisterSet::val] = true;                                        \
+  if (scratch && (Exclude & ::Ice::TargetLowering::RegSet_CallerSave))         \
+    Registers[RegisterSet::val] = false;                                       \
+  if (preserved && (Exclude & ::Ice::TargetLowering::RegSet_CalleeSave))       \
+    Registers[RegisterSet::val] = false;                                       \
+  if (stackptr && (Exclude & ::Ice::TargetLowering::RegSet_StackPointer))      \
+    Registers[RegisterSet::val] = false;                                       \
+  if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer))      \
+    Registers[RegisterSet::val] = false;
+
+    REGX8664_TABLE
+
+#undef X
+
+    return Registers;
+  }
+
+  static void
+  makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func,
+                                llvm::SmallVectorImpl<int32_t> &Permutation,
+                                const llvm::SmallBitVector &ExcludeRegisters) {
+    // TODO(stichnot): Declaring Permutation this way loses type/size
+    // information.  Fix this in conjunction with the caller-side TODO.
+    assert(Permutation.size() >= RegisterSet::Reg_NUM);
+    // Expected upper bound on the number of registers in a single equivalence
+    // class.  For x86-64, this would comprise the 16 XMM registers.  This is
+    // for performance, not correctness.
+    static const unsigned MaxEquivalenceClassSize = 8;
+    typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
+    typedef std::map<uint32_t, RegisterList> EquivalenceClassMap;
+    EquivalenceClassMap EquivalenceClasses;
+    SizeT NumShuffled = 0, NumPreserved = 0;
+
+// Build up the equivalence classes of registers by looking at the register
+// properties as well as whether the registers should be explicitly excluded
+// from shuffling.
+#define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
+          stackptr, frameptr, isInt, isFP)                                     \
+  if (ExcludeRegisters[RegisterSet::val]) {                                    \
+    /* val stays the same in the resulting permutation. */                     \
+    Permutation[RegisterSet::val] = RegisterSet::val;                          \
+    ++NumPreserved;                                                            \
+  } else {                                                                     \
+    const uint32_t Index = (scratch << 0) | (preserved << 1) |                 \
+                           (/*isI8=*/1 << 2) | (isInt << 3) | (isFP << 4);     \
+    /* val is assigned to an equivalence class based on its properties. */     \
+    EquivalenceClasses[Index].push_back(RegisterSet::val);                     \
+  }
+    REGX8664_TABLE
+#undef X
+
+    RandomNumberGeneratorWrapper RNG(Ctx->getRNG());
+
+    // Shuffle the resulting equivalence classes.
+    for (auto I : EquivalenceClasses) {
+      const RegisterList &List = I.second;
+      RegisterList Shuffled(List);
+      RandomShuffle(Shuffled.begin(), Shuffled.end(), RNG);
+      for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) {
+        Permutation[List[SI]] = Shuffled[SI];
+        ++NumShuffled;
+      }
+    }
+
+    assert(NumShuffled + NumPreserved == RegisterSet::Reg_NUM);
+
+    if (Func->isVerbose(IceV_Random)) {
+      OstreamLocker L(Func->getContext());
+      Ostream &Str = Func->getContext()->getStrDump();
+      Str << "Register equivalence classes:\n";
+      for (auto I : EquivalenceClasses) {
+        Str << "{";
+        const RegisterList &List = I.second;
+        bool First = true;
+        for (int32_t Register : List) {
+          if (!First)
+            Str << " ";
+          First = false;
+          Str << getRegName(Register, IceType_i32);
+        }
+        Str << "}\n";
+      }
+    }
+  }
+
+  /// The maximum number of arguments to pass in XMM registers
+  static const uint32_t X86_MAX_XMM_ARGS = 4;
+  /// The number of bits in a byte
+  static const uint32_t X86_CHAR_BIT = 8;
+  /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it
+  /// is used as an argument to std::max(), and the default std::less<T> has an
+  /// operator(T const&, T const&) which requires this member to have an
+  /// address.
+  static const uint32_t X86_STACK_ALIGNMENT_BYTES;
+  /// Size of the return address on the stack
+  static const uint32_t X86_RET_IP_SIZE_BYTES = 4;
+  /// The number of different NOP instructions
+  static const uint32_t X86_NUM_NOP_VARIANTS = 5;
+
+  /// Value is in bytes. Return Value adjusted to the next highest multiple
+  /// of the stack alignment.
+  static uint32_t applyStackAlignment(uint32_t Value) {
+    return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
+  }
+
+  /// Return the type which the elements of the vector have in the X86
+  /// representation of the vector.
+  static Type getInVectorElementType(Type Ty) {
+    assert(isVectorType(Ty));
+    size_t Index = static_cast<size_t>(Ty);
+    (void)Index;
+    assert(Index < TableTypeX8664AttributesSize);
+    return TableTypeX8664Attributes[Ty].InVectorElementType;
+  }
+
+  // Note: The following data structures are defined in
+  // IceTargetLoweringX8664.cpp.
+
+  /// The following table summarizes the logic for lowering the fcmp
+  /// instruction. There is one table entry for each of the 16 conditions.
+  ///
+  /// The first four columns describe the case when the operands are floating
+  /// point scalar values.  A comment in lowerFcmp() describes the lowering
+  /// template.  In the most general case, there is a compare followed by two
+  /// conditional branches, because some fcmp conditions don't map to a single
+  /// x86 conditional branch.  However, in many cases it is possible to swap the
+  /// operands in the comparison and have a single conditional branch.  Since
+  /// it's quite tedious to validate the table by hand, good execution tests are
+  /// helpful.
+  ///
+  /// The last two columns describe the case when the operands are vectors of
+  /// floating point values.  For most fcmp conditions, there is a clear mapping
+  /// to a single x86 cmpps instruction variant.  Some fcmp conditions require
+  /// special code to handle and these are marked in the table with a
+  /// Cmpps_Invalid predicate.
+  /// {@
+  static const struct TableFcmpType {
+    uint32_t Default;
+    bool SwapScalarOperands;
+    Cond::BrCond C1, C2;
+    bool SwapVectorOperands;
+    Cond::CmppsCond Predicate;
+  } TableFcmp[];
+  static const size_t TableFcmpSize;
+  /// @}
+
+  /// The following table summarizes the logic for lowering the icmp instruction
+  /// for i32 and narrower types.  Each icmp condition has a clear mapping to an
+  /// x86 conditional branch instruction.
+  /// {@
+  static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
+  static const size_t TableIcmp32Size;
+  /// @}
+
+  /// The following table summarizes the logic for lowering the icmp instruction
+  /// for the i64 type.  For Eq and Ne, two separate 32-bit comparisons and
+  /// conditional branches are needed.  For the other conditions, three separate
+  /// conditional branches are needed.
+  /// {@
+  static const struct TableIcmp64Type {
+    Cond::BrCond C1, C2, C3;
+  } TableIcmp64[];
+  static const size_t TableIcmp64Size;
+  /// @}
+
+  static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
+    size_t Index = static_cast<size_t>(Cond);
+    assert(Index < TableIcmp32Size);
+    return TableIcmp32[Index].Mapping;
+  }
+
+  static const struct TableTypeX8664AttributesType {
+    Type InVectorElementType;
+  } TableTypeX8664Attributes[];
+  static const size_t TableTypeX8664AttributesSize;
+
+  //----------------------------------------------------------------------------
+  //      __  __   __  ______  ______
+  //    /\ \/\ "-.\ \/\  ___\/\__  _\
+  //    \ \ \ \ \-.  \ \___  \/_/\ \/
+  //     \ \_\ \_\\"\_\/\_____\ \ \_\
+  //      \/_/\/_/ \/_/\/_____/  \/_/
+  //
+  //----------------------------------------------------------------------------
+  using Insts = ::Ice::X86Internal::Insts<TargetX8664>;
+
+  using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8664>;
   using Assembler = X8664::AssemblerX8664;
+
+  /// X86Operand extends the Operand hierarchy.  Its subclasses are
+  /// X86OperandMem and VariableSplit.
+  class X86Operand : public ::Ice::Operand {
+    X86Operand() = delete;
+    X86Operand(const X86Operand &) = delete;
+    X86Operand &operator=(const X86Operand &) = delete;
+
+  public:
+    enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
+    using ::Ice::Operand::dump;
+
+    void dump(const Cfg *, Ostream &Str) const override;
+
+  protected:
+    X86Operand(OperandKindX8664 Kind, Type Ty)
+        : Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {}
+  };
+
+  /// X86OperandMem represents the m64 addressing mode, with optional base and
+  /// index registers, a constant offset, and a fixed shift value for the index
+  /// register.
+  class X86OperandMem : public X86Operand {
+    X86OperandMem() = delete;
+    X86OperandMem(const X86OperandMem &) = delete;
+    X86OperandMem &operator=(const X86OperandMem &) = delete;
+
+  public:
+    enum SegmentRegisters { DefaultSegment = -1, SegReg_NUM };
+    static X86OperandMem *
+    create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
+           Variable *Index = nullptr, uint16_t Shift = 0,
+           SegmentRegisters SegmentRegister = DefaultSegment) {
+      assert(SegmentRegister == DefaultSegment);
+      (void)SegmentRegister;
+      return new (Func->allocate<X86OperandMem>())
+          X86OperandMem(Func, Ty, Base, Offset, Index, Shift);
+    }
+    Variable *getBase() const { return Base; }
+    Constant *getOffset() const { return Offset; }
+    Variable *getIndex() const { return Index; }
+    uint16_t getShift() const { return Shift; }
+    SegmentRegisters getSegmentRegister() const { return DefaultSegment; }
+    void emitSegmentOverride(Assembler *) const {}
+    Address toAsmAddress(Assembler *Asm) const;
+
+    void emit(const Cfg *Func) const override;
+    using X86Operand::dump;
+    void dump(const Cfg *Func, Ostream &Str) const override;
+
+    static bool classof(const Operand *Operand) {
+      return Operand->getKind() == static_cast<OperandKind>(kMem);
+    }
+
+    void setRandomized(bool R) { Randomized = R; }
+
+    bool getRandomized() const { return Randomized; }
+
+  private:
+    X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
+                  Variable *Index, uint16_t Shift);
+
+    Variable *Base;
+    Constant *Offset;
+    Variable *Index;
+    uint16_t Shift;
+    /// A flag to show if this memory operand is a randomized one. Randomized
+    /// memory operands are generated in
+    /// TargetX86Base::randomizeOrPoolImmediate()
+    bool Randomized = false;
+  };
+
+  /// VariableSplit is a way to treat an f64 memory location as a pair of i32
+  /// locations (Low and High).  This is needed for some cases of the Bitcast
+  /// instruction.  Since it's not possible for integer registers to access the
+  /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
+  /// the stack and then accesses through the VariableSplit.
+  // TODO(jpp): remove references to VariableSplit from IceInstX86Base as 64bit
+  // targets can natively handle these.
+  class VariableSplit : public X86Operand {
+    VariableSplit() = delete;
+    VariableSplit(const VariableSplit &) = delete;
+    VariableSplit &operator=(const VariableSplit &) = delete;
+
+  public:
+    enum Portion { Low, High };
+    static VariableSplit *create(Cfg *Func, Variable *Var, Portion Part) {
+      return new (Func->allocate<VariableSplit>())
+          VariableSplit(Func, Var, Part);
+    }
+    int32_t getOffset() const { return Part == High ? 4 : 0; }
+
+    Address toAsmAddress(const Cfg *Func) const;
+    void emit(const Cfg *Func) const override;
+    using X86Operand::dump;
+    void dump(const Cfg *Func, Ostream &Str) const override;
+
+    static bool classof(const Operand *Operand) {
+      return Operand->getKind() == static_cast<OperandKind>(kSplit);
+    }
+
+  private:
+    VariableSplit(Cfg *Func, Variable *Var, Portion Part)
+        : X86Operand(kSplit, IceType_i32), Var(Var), Part(Part) {
+      assert(Var->getType() == IceType_f64);
+      Vars = Func->allocateArrayOf<Variable *>(1);
+      Vars[0] = Var;
+      NumVars = 1;
+    }
+
+    Variable *Var;
+    Portion Part;
+  };
+
+  /// SpillVariable decorates a Variable by linking it to another Variable.
+  /// When stack frame offsets are computed, the SpillVariable is given a
+  /// distinct stack slot only if its linked Variable has a register.  If the
+  /// linked Variable has a stack slot, then the Variable and SpillVariable
+  /// share that slot.
+  class SpillVariable : public Variable {
+    SpillVariable() = delete;
+    SpillVariable(const SpillVariable &) = delete;
+    SpillVariable &operator=(const SpillVariable &) = delete;
+
+  public:
+    static SpillVariable *create(Cfg *Func, Type Ty, SizeT Index) {
+      return new (Func->allocate<SpillVariable>()) SpillVariable(Ty, Index);
+    }
+    const static OperandKind SpillVariableKind =
+        static_cast<OperandKind>(kVariable_Target);
+    static bool classof(const Operand *Operand) {
+      return Operand->getKind() == SpillVariableKind;
+    }
+    void setLinkedTo(Variable *Var) { LinkedTo = Var; }
+    Variable *getLinkedTo() const { return LinkedTo; }
+    // Inherit dump() and emit() from Variable.
+
+  private:
+    SpillVariable(Type Ty, SizeT Index)
+        : Variable(SpillVariableKind, Ty, Index), LinkedTo(nullptr) {}
+    Variable *LinkedTo;
+  };
+
+  // Note: The following data structures are defined in IceInstX8664.cpp.
+
+  static const struct InstBrAttributesType {
+    Cond::BrCond Opposite;
+    const char *DisplayString;
+    const char *EmitString;
+  } InstBrAttributes[];
+
+  static const struct InstCmppsAttributesType {
+    const char *EmitString;
+  } InstCmppsAttributes[];
+
+  static const struct TypeAttributesType {
+    const char *CvtString;   // i (integer), s (single FP), d (double FP)
+    const char *SdSsString;  // ss, sd, or <blank>
+    const char *PackString;  // b, w, d, or <blank>
+    const char *WidthString; // b, w, l, q, or <blank>
+    const char *FldString;   // s, l, or <blank>
+  } TypeAttributes[];
 };
 
 } // end of namespace X86Internal

src/IceTargetLoweringX86Base.h

@@ -342,11 +342,25 @@ protected:
   void _divss(Variable *Dest, Operand *Src0) {
     Context.insert(Traits::Insts::Divss::create(Func, Dest, Src0));
   }
-  void _fld(Operand *Src0) {
-    Context.insert(Traits::Insts::Fld::create(Func, Src0));
-  }
-  void _fstp(Variable *Dest) {
-    Context.insert(Traits::Insts::Fstp::create(Func, Dest));
+  template <typename T = Traits>
+  typename std::enable_if<T::UsesX87, void>::type _fld(Operand *Src0) {
+    Context.insert(Traits::Insts::template Fld<>::create(Func, Src0));
+  }
+  // TODO(jpp): when implementing the X8664 calling convention, make sure x8664
+  // does not invoke this method, and remove it.
+  template <typename T = Traits>
+  typename std::enable_if<!T::UsesX87, void>::type _fld(Operand *) {
+    llvm::report_fatal_error("fld is not available in x86-64");
+  }
+  template <typename T = Traits>
+  typename std::enable_if<T::UsesX87, void>::type _fstp(Variable *Dest) {
+    Context.insert(Traits::Insts::template Fstp<>::create(Func, Dest));
+  }
+  // TODO(jpp): when implementing the X8664 calling convention, make sure x8664
+  // does not invoke this method, and remove it.
+  template <typename T = Traits>
+  typename std::enable_if<!T::UsesX87, void>::type _fstp(Variable *) {
+    llvm::report_fatal_error("fstp is not available in x86-64");
   }
   void _idiv(Variable *Dest, Operand *Src0, Operand *Src1) {
     Context.insert(Traits::Insts::Idiv::create(Func, Dest, Src0, Src1));

unittest/AssemblerX8632/TestUtil.h

@@ -31,6 +31,7 @@ protected:
   using ByteRegister = AssemblerX8632::Traits::ByteRegister;
   using Cond = AssemblerX8632::Traits::Cond;
   using GPRRegister = AssemblerX8632::Traits::GPRRegister;
+  using Label = ::Ice::X86Internal::Label;
   using Traits = AssemblerX8632::Traits;
   using XmmRegister = AssemblerX8632::Traits::XmmRegister;
   using X87STRegister = AssemblerX8632::Traits::X87STRegister;