LLVM 10: Add configs/common and configs/linux.

third_party/llvm-10.0/configs/common/include/llvm/IR/IntrinsicsBPF.h

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Intrinsic Function Source Fragment                                         *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_IR_INTRINSIC_BPF_ENUMS_H
+#define LLVM_IR_INTRINSIC_BPF_ENUMS_H
+
+namespace llvm {
+namespace Intrinsic {
+enum BPFIntrinsics : unsigned {
+// Enum values for intrinsics
+    bpf_load_byte = 1864,                             // llvm.bpf.load.byte
+    bpf_load_half,                             // llvm.bpf.load.half
+    bpf_load_word,                             // llvm.bpf.load.word
+    bpf_preserve_field_info,                   // llvm.bpf.preserve.field.info
+    bpf_pseudo,                                // llvm.bpf.pseudo
+}; // enum
+} // namespace Intrinsic
+} // namespace llvm
+
+#endif

third_party/llvm-10.0/configs/common/include/llvm/IR/IntrinsicsR600.h

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Intrinsic Function Source Fragment                                         *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_IR_INTRINSIC_R600_ENUMS_H
+#define LLVM_IR_INTRINSIC_R600_ENUMS_H
+
+namespace llvm {
+namespace Intrinsic {
+enum R600Intrinsics : unsigned {
+// Enum values for intrinsics
+    r600_cube = 6004,                                 // llvm.r600.cube
+    r600_ddx,                                  // llvm.r600.ddx
+    r600_ddy,                                  // llvm.r600.ddy
+    r600_dot4,                                 // llvm.r600.dot4
+    r600_group_barrier,                        // llvm.r600.group.barrier
+    r600_implicitarg_ptr,                      // llvm.r600.implicitarg.ptr
+    r600_kill,                                 // llvm.r600.kill
+    r600_rat_store_typed,                      // llvm.r600.rat.store.typed
+    r600_read_global_size_x,                   // llvm.r600.read.global.size.x
+    r600_read_global_size_y,                   // llvm.r600.read.global.size.y
+    r600_read_global_size_z,                   // llvm.r600.read.global.size.z
+    r600_read_local_size_x,                    // llvm.r600.read.local.size.x
+    r600_read_local_size_y,                    // llvm.r600.read.local.size.y
+    r600_read_local_size_z,                    // llvm.r600.read.local.size.z
+    r600_read_ngroups_x,                       // llvm.r600.read.ngroups.x
+    r600_read_ngroups_y,                       // llvm.r600.read.ngroups.y
+    r600_read_ngroups_z,                       // llvm.r600.read.ngroups.z
+    r600_read_tgid_x,                          // llvm.r600.read.tgid.x
+    r600_read_tgid_y,                          // llvm.r600.read.tgid.y
+    r600_read_tgid_z,                          // llvm.r600.read.tgid.z
+    r600_read_tidig_x,                         // llvm.r600.read.tidig.x
+    r600_read_tidig_y,                         // llvm.r600.read.tidig.y
+    r600_read_tidig_z,                         // llvm.r600.read.tidig.z
+    r600_recipsqrt_clamped,                    // llvm.r600.recipsqrt.clamped
+    r600_recipsqrt_ieee,                       // llvm.r600.recipsqrt.ieee
+    r600_store_stream_output,                  // llvm.r600.store.stream.output
+    r600_store_swizzle,                        // llvm.r600.store.swizzle
+    r600_tex,                                  // llvm.r600.tex
+    r600_texc,                                 // llvm.r600.texc
+    r600_txb,                                  // llvm.r600.txb
+    r600_txbc,                                 // llvm.r600.txbc
+    r600_txf,                                  // llvm.r600.txf
+    r600_txl,                                  // llvm.r600.txl
+    r600_txlc,                                 // llvm.r600.txlc
+    r600_txq,                                  // llvm.r600.txq
+}; // enum
+} // namespace Intrinsic
+} // namespace llvm
+
+#endif

third_party/llvm-10.0/configs/common/include/llvm/IR/IntrinsicsRISCV.h

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Intrinsic Function Source Fragment                                         *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_IR_INTRINSIC_RISCV_ENUMS_H
+#define LLVM_IR_INTRINSIC_RISCV_ENUMS_H
+
+namespace llvm {
+namespace Intrinsic {
+enum RISCVIntrinsics : unsigned {
+// Enum values for intrinsics
+    riscv_masked_atomicrmw_add_i32 = 6039,            // llvm.riscv.masked.atomicrmw.add.i32
+    riscv_masked_atomicrmw_add_i64,            // llvm.riscv.masked.atomicrmw.add.i64
+    riscv_masked_atomicrmw_max_i32,            // llvm.riscv.masked.atomicrmw.max.i32
+    riscv_masked_atomicrmw_max_i64,            // llvm.riscv.masked.atomicrmw.max.i64
+    riscv_masked_atomicrmw_min_i32,            // llvm.riscv.masked.atomicrmw.min.i32
+    riscv_masked_atomicrmw_min_i64,            // llvm.riscv.masked.atomicrmw.min.i64
+    riscv_masked_atomicrmw_nand_i32,           // llvm.riscv.masked.atomicrmw.nand.i32
+    riscv_masked_atomicrmw_nand_i64,           // llvm.riscv.masked.atomicrmw.nand.i64
+    riscv_masked_atomicrmw_sub_i32,            // llvm.riscv.masked.atomicrmw.sub.i32
+    riscv_masked_atomicrmw_sub_i64,            // llvm.riscv.masked.atomicrmw.sub.i64
+    riscv_masked_atomicrmw_umax_i32,           // llvm.riscv.masked.atomicrmw.umax.i32
+    riscv_masked_atomicrmw_umax_i64,           // llvm.riscv.masked.atomicrmw.umax.i64
+    riscv_masked_atomicrmw_umin_i32,           // llvm.riscv.masked.atomicrmw.umin.i32
+    riscv_masked_atomicrmw_umin_i64,           // llvm.riscv.masked.atomicrmw.umin.i64
+    riscv_masked_atomicrmw_xchg_i32,           // llvm.riscv.masked.atomicrmw.xchg.i32
+    riscv_masked_atomicrmw_xchg_i64,           // llvm.riscv.masked.atomicrmw.xchg.i64
+    riscv_masked_cmpxchg_i32,                  // llvm.riscv.masked.cmpxchg.i32
+    riscv_masked_cmpxchg_i64,                  // llvm.riscv.masked.cmpxchg.i64
+}; // enum
+} // namespace Intrinsic
+} // namespace llvm
+
+#endif

third_party/llvm-10.0/configs/common/include/llvm/IR/IntrinsicsWebAssembly.h

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Intrinsic Function Source Fragment                                         *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_IR_INTRINSIC_WASM_ENUMS_H
+#define LLVM_IR_INTRINSIC_WASM_ENUMS_H
+
+namespace llvm {
+namespace Intrinsic {
+enum WASMIntrinsics : unsigned {
+// Enum values for intrinsics
+    wasm_alltrue = 6285,                              // llvm.wasm.alltrue
+    wasm_anytrue,                              // llvm.wasm.anytrue
+    wasm_atomic_notify,                        // llvm.wasm.atomic.notify
+    wasm_atomic_wait_i32,                      // llvm.wasm.atomic.wait.i32
+    wasm_atomic_wait_i64,                      // llvm.wasm.atomic.wait.i64
+    wasm_avgr_unsigned,                        // llvm.wasm.avgr.unsigned
+    wasm_bitselect,                            // llvm.wasm.bitselect
+    wasm_data_drop,                            // llvm.wasm.data.drop
+    wasm_dot,                                  // llvm.wasm.dot
+    wasm_extract_exception,                    // llvm.wasm.extract.exception
+    wasm_get_ehselector,                       // llvm.wasm.get.ehselector
+    wasm_get_exception,                        // llvm.wasm.get.exception
+    wasm_landingpad_index,                     // llvm.wasm.landingpad.index
+    wasm_lsda,                                 // llvm.wasm.lsda
+    wasm_memory_grow,                          // llvm.wasm.memory.grow
+    wasm_memory_init,                          // llvm.wasm.memory.init
+    wasm_memory_size,                          // llvm.wasm.memory.size
+    wasm_narrow_signed,                        // llvm.wasm.narrow.signed
+    wasm_narrow_unsigned,                      // llvm.wasm.narrow.unsigned
+    wasm_qfma,                                 // llvm.wasm.qfma
+    wasm_qfms,                                 // llvm.wasm.qfms
+    wasm_rethrow_in_catch,                     // llvm.wasm.rethrow.in.catch
+    wasm_sub_saturate_signed,                  // llvm.wasm.sub.saturate.signed
+    wasm_sub_saturate_unsigned,                // llvm.wasm.sub.saturate.unsigned
+    wasm_swizzle,                              // llvm.wasm.swizzle
+    wasm_throw,                                // llvm.wasm.throw
+    wasm_tls_align,                            // llvm.wasm.tls.align
+    wasm_tls_base,                             // llvm.wasm.tls.base
+    wasm_tls_size,                             // llvm.wasm.tls.size
+    wasm_trunc_saturate_signed,                // llvm.wasm.trunc.saturate.signed
+    wasm_trunc_saturate_unsigned,              // llvm.wasm.trunc.saturate.unsigned
+    wasm_trunc_signed,                         // llvm.wasm.trunc.signed
+    wasm_trunc_unsigned,                       // llvm.wasm.trunc.unsigned
+    wasm_widen_high_signed,                    // llvm.wasm.widen.high.signed
+    wasm_widen_high_unsigned,                  // llvm.wasm.widen.high.unsigned
+    wasm_widen_low_signed,                     // llvm.wasm.widen.low.signed
+    wasm_widen_low_unsigned,                   // llvm.wasm.widen.low.unsigned
+}; // enum
+} // namespace Intrinsic
+} // namespace llvm
+
+#endif

third_party/llvm-10.0/configs/common/include/llvm/IR/IntrinsicsXCore.h

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Intrinsic Function Source Fragment                                         *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_IR_INTRINSIC_XCORE_ENUMS_H
+#define LLVM_IR_INTRINSIC_XCORE_ENUMS_H
+
+namespace llvm {
+namespace Intrinsic {
+enum XCOREIntrinsics : unsigned {
+// Enum values for intrinsics
+    xcore_bitrev = 7494,                              // llvm.xcore.bitrev
+    xcore_checkevent,                          // llvm.xcore.checkevent
+    xcore_chkct,                               // llvm.xcore.chkct
+    xcore_clre,                                // llvm.xcore.clre
+    xcore_clrpt,                               // llvm.xcore.clrpt
+    xcore_clrsr,                               // llvm.xcore.clrsr
+    xcore_crc32,                               // llvm.xcore.crc32
+    xcore_crc8,                                // llvm.xcore.crc8
+    xcore_edu,                                 // llvm.xcore.edu
+    xcore_eeu,                                 // llvm.xcore.eeu
+    xcore_endin,                               // llvm.xcore.endin
+    xcore_freer,                               // llvm.xcore.freer
+    xcore_geted,                               // llvm.xcore.geted
+    xcore_getet,                               // llvm.xcore.getet
+    xcore_getid,                               // llvm.xcore.getid
+    xcore_getps,                               // llvm.xcore.getps
+    xcore_getr,                                // llvm.xcore.getr
+    xcore_getst,                               // llvm.xcore.getst
+    xcore_getts,                               // llvm.xcore.getts
+    xcore_in,                                  // llvm.xcore.in
+    xcore_inct,                                // llvm.xcore.inct
+    xcore_initcp,                              // llvm.xcore.initcp
+    xcore_initdp,                              // llvm.xcore.initdp
+    xcore_initlr,                              // llvm.xcore.initlr
+    xcore_initpc,                              // llvm.xcore.initpc
+    xcore_initsp,                              // llvm.xcore.initsp
+    xcore_inshr,                               // llvm.xcore.inshr
+    xcore_int,                                 // llvm.xcore.int
+    xcore_mjoin,                               // llvm.xcore.mjoin
+    xcore_msync,                               // llvm.xcore.msync
+    xcore_out,                                 // llvm.xcore.out
+    xcore_outct,                               // llvm.xcore.outct
+    xcore_outshr,                              // llvm.xcore.outshr
+    xcore_outt,                                // llvm.xcore.outt
+    xcore_peek,                                // llvm.xcore.peek
+    xcore_setc,                                // llvm.xcore.setc
+    xcore_setclk,                              // llvm.xcore.setclk
+    xcore_setd,                                // llvm.xcore.setd
+    xcore_setev,                               // llvm.xcore.setev
+    xcore_setps,                               // llvm.xcore.setps
+    xcore_setpsc,                              // llvm.xcore.setpsc
+    xcore_setpt,                               // llvm.xcore.setpt
+    xcore_setrdy,                              // llvm.xcore.setrdy
+    xcore_setsr,                               // llvm.xcore.setsr
+    xcore_settw,                               // llvm.xcore.settw
+    xcore_setv,                                // llvm.xcore.setv
+    xcore_sext,                                // llvm.xcore.sext
+    xcore_ssync,                               // llvm.xcore.ssync
+    xcore_syncr,                               // llvm.xcore.syncr
+    xcore_testct,                              // llvm.xcore.testct
+    xcore_testwct,                             // llvm.xcore.testwct
+    xcore_waitevent,                           // llvm.xcore.waitevent
+    xcore_zext,                                // llvm.xcore.zext
+}; // enum
+} // namespace Intrinsic
+} // namespace llvm
+
+#endif

third_party/llvm-10.0/configs/common/include/llvm/IR/cmake_install.cmake

+# Install script for directory: /home/ben/src/llvm-project/llvm/include/llvm/IR
+
+# Set the install prefix
+if(NOT DEFINED CMAKE_INSTALL_PREFIX)
+  set(CMAKE_INSTALL_PREFIX "/usr/local")
+endif()
+string(REGEX REPLACE "/$" "" CMAKE_INSTALL_PREFIX "${CMAKE_INSTALL_PREFIX}")
+
+# Set the install configuration name.
+if(NOT DEFINED CMAKE_INSTALL_CONFIG_NAME)
+  if(BUILD_TYPE)
+    string(REGEX REPLACE "^[^A-Za-z0-9_]+" ""
+           CMAKE_INSTALL_CONFIG_NAME "${BUILD_TYPE}")
+  else()
+    set(CMAKE_INSTALL_CONFIG_NAME "Debug")
+  endif()
+  message(STATUS "Install configuration: \"${CMAKE_INSTALL_CONFIG_NAME}\"")
+endif()
+
+# Set the component getting installed.
+if(NOT CMAKE_INSTALL_COMPONENT)
+  if(COMPONENT)
+    message(STATUS "Install component: \"${COMPONENT}\"")
+    set(CMAKE_INSTALL_COMPONENT "${COMPONENT}")
+  else()
+    set(CMAKE_INSTALL_COMPONENT)
+  endif()
+endif()
+
+# Install shared libraries without execute permission?
+if(NOT DEFINED CMAKE_INSTALL_SO_NO_EXE)
+  set(CMAKE_INSTALL_SO_NO_EXE "1")
+endif()
+
+# Is this installation the result of a crosscompile?
+if(NOT DEFINED CMAKE_CROSSCOMPILING)
+  set(CMAKE_CROSSCOMPILING "FALSE")
+endif()
+

third_party/llvm-10.0/configs/common/include/llvm/Support/VCSRevision.h

+#define LLVM_REVISION "d32170dbd5b0d54436537b6b75beaf44324e0c28"
+#define LLVM_REPOSITORY "https://github.com/llvm/llvm-project.git"

third_party/llvm-10.0/configs/common/lib/Target/AArch64/AArch64GenExegesis.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Exegesis Tables                                                            *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+static const char* AArch64PfmCounterNames[] = {
+  "CPU_CYCLES", // 0
+};
+
+
+static const PfmCountersInfo AArch64DefaultPfmCounters = {
+  AArch64PfmCounterNames[0],  // Cycle counter
+  nullptr,  // No uops counter.
+  nullptr,  // No issue counters.
+  0
+};
+
+// Sorted (by CpuName) array of pfm counters.
+static const CpuAndPfmCounters AArch64CpuPfmCounters[] = {
+  { "", &AArch64DefaultPfmCounters },
+};
+

third_party/llvm-10.0/configs/common/lib/Target/AArch64/AArch64GenGICombiner.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Global Combiner                                                            *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
+#include "llvm/ADT/SparseBitVector.h"
+namespace llvm {
+extern cl::OptionCategory GICombinerOptionCategory;
+} // end namespace llvm
+#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
+
+#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
+class AArch64GenPreLegalizerCombinerHelper {
+  SparseBitVector<> DisabledRules;
+
+public:
+  bool parseCommandLineOption();
+  bool isRuleDisabled(unsigned ID) const;
+  bool setRuleDisabled(StringRef RuleIdentifier);
+
+  bool tryCombineAll(
+    GISelChangeObserver &Observer,
+    MachineInstr &MI,
+    MachineIRBuilder &B,
+    CombinerHelper &Helper) const;
+};
+
+static Optional<uint64_t> getRuleIdxForIdentifier(StringRef RuleIdentifier) {
+  uint64_t I;
+  // getAtInteger(...) returns false on success
+  bool Parsed = !RuleIdentifier.getAsInteger(0, I);
+  if (Parsed)
+    return I;
+
+#ifndef NDEBUG
+  switch (RuleIdentifier.size()) {
+  default: break;
+  case 9:	 // 1 string to match.
+    if (memcmp(RuleIdentifier.data()+0, "copy_prop", 9) != 0)
+      break;
+    return 0;	 // "copy_prop"
+  case 15:	 // 1 string to match.
+    if (memcmp(RuleIdentifier.data()+0, "extending_loads", 15) != 0)
+      break;
+    return 2;	 // "extending_loads"
+  case 19:	 // 1 string to match.
+    if (memcmp(RuleIdentifier.data()+0, "ptr_add_immed_chain", 19) != 0)
+      break;
+    return 1;	 // "ptr_add_immed_chain"
+  case 26:	 // 2 strings to match.
+    switch (RuleIdentifier[0]) {
+    default: break;
+    case 'c':	 // 1 string to match.
+      if (memcmp(RuleIdentifier.data()+1, "ombine_indexed_load_store", 25) != 0)
+        break;
+      return 3;	 // "combine_indexed_load_store"
+    case 'e':	 // 1 string to match.
+      if (memcmp(RuleIdentifier.data()+1, "lide_br_by_inverting_cond", 25) != 0)
+        break;
+      return 4;	 // "elide_br_by_inverting_cond"
+    }
+    break;
+  }
+#endif // ifndef NDEBUG
+
+  return None;
+}
+bool AArch64GenPreLegalizerCombinerHelper::setRuleDisabled(StringRef RuleIdentifier) {
+  std::pair<StringRef, StringRef> RangePair = RuleIdentifier.split('-');
+  if (!RangePair.second.empty()) {
+    const auto First = getRuleIdxForIdentifier(RangePair.first);
+    const auto Last = getRuleIdxForIdentifier(RangePair.second);
+    if (!First.hasValue() || !Last.hasValue())
+      return false;
+    if (First >= Last)
+      report_fatal_error("Beginning of range should be before end of range");
+    for (auto I = First.getValue(); I < Last.getValue(); ++I)
+      DisabledRules.set(I);
+    return true;
+  } else {
+    const auto I = getRuleIdxForIdentifier(RangePair.first);
+    if (!I.hasValue())
+      return false;
+    DisabledRules.set(I.getValue());
+    return true;
+  }
+  return false;
+}
+bool AArch64GenPreLegalizerCombinerHelper::isRuleDisabled(unsigned RuleID) const {
+  return DisabledRules.test(RuleID);
+}
+#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
+
+#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
+
+cl::list<std::string> AArch64PreLegalizerCombinerHelperOption(
+    "aarch64prelegalizercombinerhelper-disable-rule",
+    cl::desc("Disable one or more combiner rules temporarily in the AArch64PreLegalizerCombinerHelper pass"),
+    cl::CommaSeparated,
+    cl::Hidden,
+    cl::cat(GICombinerOptionCategory));
+
+bool AArch64GenPreLegalizerCombinerHelper::parseCommandLineOption() {
+  for (const auto &Identifier : AArch64PreLegalizerCombinerHelperOption)
+    if (!setRuleDisabled(Identifier))
+      return false;
+  return true;
+}
+
+bool AArch64GenPreLegalizerCombinerHelper::tryCombineAll(
+    GISelChangeObserver &Observer,
+    MachineInstr &MI,
+    MachineIRBuilder &B,
+    CombinerHelper &Helper) const {
+  MachineBasicBlock *MBB = MI.getParent();
+  MachineFunction *MF = MBB->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  SmallVector<MachineInstr *, 8> MIs = { &MI };
+
+  (void)MBB; (void)MF; (void)MRI;
+
+  // Match data
+  PtrAddChain MatchData1;
+  PreferredTuple MatchData2;
+  IndexedLoadStoreMatchInfo MatchData3;
+
+  int Partition = -1;
+  Partition = -1;
+  switch (MIs[0]->getOpcode()) {
+  case TargetOpcode::COPY: Partition = 0; break;
+  case TargetOpcode::G_PTR_ADD: Partition = 1; break;
+  case TargetOpcode::G_LOAD: Partition = 2; break;
+  case TargetOpcode::G_SEXTLOAD: Partition = 3; break;
+  case TargetOpcode::G_ZEXTLOAD: Partition = 4; break;
+  case TargetOpcode::G_STORE: Partition = 5; break;
+  case TargetOpcode::G_BR: Partition = 6; break;
+  }
+  // Default case but without conflicting with potential default case in selection.
+  if (Partition == -1) return false;
+  if (Partition == 0 /* TargetOpcode::COPY */) {
+    // Leaf name: copy_prop
+    // Rule: copy_prop
+    if (!isRuleDisabled(0)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineCopy(*MIs[0]); 
+          return true;
+      }()) {
+        Helper.applyCombineCopy(*MIs[0]); 
+        return true;
+      }
+    }
+    return false;
+  }
+  if (Partition == 1 /* TargetOpcode::G_PTR_ADD */) {
+    // Leaf name: ptr_add_immed_chain
+    // Rule: ptr_add_immed_chain
+    if (!isRuleDisabled(1)) {
+      if (1
+          && [&]() {
+           return Helper.matchPtrAddImmedChain(*MIs[0], MatchData1); 
+          return true;
+      }()) {
+        Helper.applyPtrAddImmedChain(*MIs[0], MatchData1); 
+        return true;
+      }
+    }
+    return false;
+  }
+  if (Partition == 2 /* TargetOpcode::G_LOAD */) {
+    // Leaf name: extending_loads
+    // Rule: extending_loads
+    if (!isRuleDisabled(2)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2); 
+          return true;
+      }()) {
+        Helper.applyCombineExtendingLoads(*MIs[0], MatchData2); 
+        return true;
+      }
+    }
+    // Leaf name: combine_indexed_load_store
+    // Rule: combine_indexed_load_store
+    if (!isRuleDisabled(3)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 
+          return true;
+      }()) {
+        Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 
+        return true;
+      }
+    }
+    return false;
+  }
+  if (Partition == 3 /* TargetOpcode::G_SEXTLOAD */) {
+    // Leaf name: extending_loads
+    // Rule: extending_loads
+    if (!isRuleDisabled(2)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2); 
+          return true;
+      }()) {
+        Helper.applyCombineExtendingLoads(*MIs[0], MatchData2); 
+        return true;
+      }
+    }
+    // Leaf name: combine_indexed_load_store
+    // Rule: combine_indexed_load_store
+    if (!isRuleDisabled(3)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 
+          return true;
+      }()) {
+        Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 
+        return true;
+      }
+    }
+    return false;
+  }
+  if (Partition == 4 /* TargetOpcode::G_ZEXTLOAD */) {
+    // Leaf name: extending_loads
+    // Rule: extending_loads
+    if (!isRuleDisabled(2)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2); 
+          return true;
+      }()) {
+        Helper.applyCombineExtendingLoads(*MIs[0], MatchData2); 
+        return true;
+      }
+    }
+    // Leaf name: combine_indexed_load_store
+    // Rule: combine_indexed_load_store
+    if (!isRuleDisabled(3)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 
+          return true;
+      }()) {
+        Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 
+        return true;
+      }
+    }
+    return false;
+  }
+  if (Partition == 5 /* TargetOpcode::G_STORE */) {
+    // Leaf name: combine_indexed_load_store
+    // Rule: combine_indexed_load_store
+    if (!isRuleDisabled(3)) {
+      if (1
+          && [&]() {
+           return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3); 
+          return true;
+      }()) {
+        Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3); 
+        return true;
+      }
+    }
+    return false;
+  }
+  if (Partition == 6 /* TargetOpcode::G_BR */) {
+    // Leaf name: elide_br_by_inverting_cond
+    // Rule: elide_br_by_inverting_cond
+    if (!isRuleDisabled(4)) {
+      if (1
+          && [&]() {
+           return Helper.matchElideBrByInvertingCond(*MIs[0]); 
+          return true;
+      }()) {
+        Helper.applyElideBrByInvertingCond(*MIs[0]); 
+        return true;
+      }
+    }
+    return false;
+  }
+
+  return false;
+}
+#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP

third_party/llvm-10.0/configs/common/lib/Target/AArch64/AArch64GenMCPseudoLowering.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Pseudo-instruction MC lowering Source Fragment                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+bool AArch64AsmPrinter::
+emitPseudoExpansionLowering(MCStreamer &OutStreamer,
+                            const MachineInstr *MI) {
+  return false;
+}
+

third_party/llvm-10.0/configs/common/lib/Target/AArch64/AArch64GenRegisterBank.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Register Bank Source Fragments                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_REGBANK_DECLARATIONS
+#undef GET_REGBANK_DECLARATIONS
+namespace llvm {
+namespace AArch64 {
+enum {
+  CCRegBankID,
+  FPRRegBankID,
+  GPRRegBankID,
+  NumRegisterBanks,
+};
+} // end namespace AArch64
+} // end namespace llvm
+#endif // GET_REGBANK_DECLARATIONS
+
+#ifdef GET_TARGET_REGBANK_CLASS
+#undef GET_TARGET_REGBANK_CLASS
+private:
+  static RegisterBank *RegBanks[];
+
+protected:
+  AArch64GenRegisterBankInfo();
+
+#endif // GET_TARGET_REGBANK_CLASS
+
+#ifdef GET_TARGET_REGBANK_IMPL
+#undef GET_TARGET_REGBANK_IMPL
+namespace llvm {
+namespace AArch64 {
+const uint32_t CCRegBankCoverageData[] = {
+    // 0-31
+    (1u << (AArch64::CCRRegClassID - 0)) |
+    0,
+    // 32-63
+    0,
+    // 64-95
+    0,
+    // 96-127
+    0,
+};
+const uint32_t FPRRegBankCoverageData[] = {
+    // 0-31
+    (1u << (AArch64::FPR8RegClassID - 0)) |
+    (1u << (AArch64::FPR16RegClassID - 0)) |
+    (1u << (AArch64::FPR32RegClassID - 0)) |
+    (1u << (AArch64::FPR64RegClassID - 0)) |
+    (1u << (AArch64::DDRegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (AArch64::FPR128RegClassID - 32)) |
+    (1u << (AArch64::DDDRegClassID - 32)) |
+    (1u << (AArch64::DDDDRegClassID - 32)) |
+    (1u << (AArch64::QQRegClassID - 32)) |
+    (1u << (AArch64::QQQRegClassID - 32)) |
+    (1u << (AArch64::FPR128_loRegClassID - 32)) |
+    (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
+    (1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+    (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
+    (1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
+    0,
+    // 64-95
+    (1u << (AArch64::QQQQRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
+    (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 64)) |
+    0,
+    // 96-127
+    (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID - 96)) |
+    0,
+};
+const uint32_t GPRRegBankCoverageData[] = {
+    // 0-31
+    (1u << (AArch64::GPR64allRegClassID - 0)) |
+    (1u << (AArch64::GPR32allRegClassID - 0)) |
+    (1u << (AArch64::GPR64RegClassID - 0)) |
+    (1u << (AArch64::GPR32RegClassID - 0)) |
+    (1u << (AArch64::GPR64commonRegClassID - 0)) |
+    (1u << (AArch64::GPR32spRegClassID - 0)) |
+    (1u << (AArch64::GPR32commonRegClassID - 0)) |
+    (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 0)) |
+    (1u << (AArch64::GPR64noip_and_tcGPR64RegClassID - 0)) |
+    (1u << (AArch64::GPR64argRegClassID - 0)) |
+    (1u << (AArch64::GPR32argRegClassID - 0)) |
+    (1u << (AArch64::tcGPR64RegClassID - 0)) |
+    (1u << (AArch64::rtcGPR64RegClassID - 0)) |
+    (1u << (AArch64::GPR64noipRegClassID - 0)) |
+    (1u << (AArch64::GPR64spRegClassID - 0)) |
+    (1u << (AArch64::GPR64sponlyRegClassID - 0)) |
+    (1u << (AArch64::GPR32sponlyRegClassID - 0)) |
+    0,
+    // 32-63
+    0,
+    // 64-95
+    0,
+    // 96-127
+    0,
+};
+
+RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 108);
+RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 108);
+RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 108);
+} // end namespace AArch64
+
+RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
+    &AArch64::CCRegBank,
+    &AArch64::FPRRegBank,
+    &AArch64::GPRRegBank,
+};
+
+AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo()
+    : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {
+  // Assert that RegBank indices match their ID's
+#ifndef NDEBUG
+  unsigned Index = 0;
+  for (const auto &RB : RegBanks)
+    assert(Index++ == RB->getID() && "Index != ID");
+#endif // NDEBUG
+}
+} // end namespace llvm
+#endif // GET_TARGET_REGBANK_IMPL

third_party/llvm-10.0/configs/common/lib/Target/ARM/ARMGenRegisterBank.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Register Bank Source Fragments                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_REGBANK_DECLARATIONS
+#undef GET_REGBANK_DECLARATIONS
+namespace llvm {
+namespace ARM {
+enum {
+  FPRRegBankID,
+  GPRRegBankID,
+  NumRegisterBanks,
+};
+} // end namespace ARM
+} // end namespace llvm
+#endif // GET_REGBANK_DECLARATIONS
+
+#ifdef GET_TARGET_REGBANK_CLASS
+#undef GET_TARGET_REGBANK_CLASS
+private:
+  static RegisterBank *RegBanks[];
+
+protected:
+  ARMGenRegisterBankInfo();
+
+#endif // GET_TARGET_REGBANK_CLASS
+
+#ifdef GET_TARGET_REGBANK_IMPL
+#undef GET_TARGET_REGBANK_IMPL
+namespace llvm {
+namespace ARM {
+const uint32_t FPRRegBankCoverageData[] = {
+    // 0-31
+    (1u << (ARM::HPRRegClassID - 0)) |
+    (1u << (ARM::SPRRegClassID - 0)) |
+    (1u << (ARM::SPR_8RegClassID - 0)) |
+    (1u << (ARM::FPWithVPRRegClassID - 0)) |
+    (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
+    (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (ARM::DPRRegClassID - 32)) |
+    (1u << (ARM::DPR_VFP2RegClassID - 32)) |
+    (1u << (ARM::DPR_8RegClassID - 32)) |
+    (1u << (ARM::QPRRegClassID - 32)) |
+    (1u << (ARM::MQPRRegClassID - 32)) |
+    (1u << (ARM::QPR_VFP2RegClassID - 32)) |
+    (1u << (ARM::QPR_8RegClassID - 32)) |
+    0,
+    // 64-95
+    0,
+    // 96-127
+    0,
+};
+const uint32_t GPRRegBankCoverageData[] = {
+    // 0-31
+    (1u << (ARM::GPRRegClassID - 0)) |
+    (1u << (ARM::GPRnopcRegClassID - 0)) |
+    (1u << (ARM::rGPRRegClassID - 0)) |
+    (1u << (ARM::tGPRRegClassID - 0)) |
+    (1u << (ARM::tGPR_and_tGPREvenRegClassID - 0)) |
+    (1u << (ARM::tGPREven_and_tGPR_and_tcGPRRegClassID - 0)) |
+    (1u << (ARM::tGPR_and_tGPROddRegClassID - 0)) |
+    (1u << (ARM::tGPROdd_and_tcGPRRegClassID - 0)) |
+    (1u << (ARM::tGPR_and_tcGPRRegClassID - 0)) |
+    (1u << (ARM::tGPREvenRegClassID - 0)) |
+    (1u << (ARM::hGPR_and_tGPREvenRegClassID - 0)) |
+    (1u << (ARM::GPRlrRegClassID - 0)) |
+    (1u << (ARM::tGPREven_and_tcGPRRegClassID - 0)) |
+    (1u << (ARM::GPRwithAPSRnosp_and_hGPRRegClassID - 0)) |
+    (1u << (ARM::hGPR_and_tGPROddRegClassID - 0)) |
+    (1u << (ARM::tGPROddRegClassID - 0)) |
+    (1u << (ARM::tcGPRRegClassID - 0)) |
+    (1u << (ARM::GPRnopc_and_hGPRRegClassID - 0)) |
+    (1u << (ARM::GPRspRegClassID - 0)) |
+    (1u << (ARM::tGPRwithpcRegClassID - 0)) |
+    (1u << (ARM::hGPRRegClassID - 0)) |
+    (1u << (ARM::GPRwithAPSRRegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (ARM::hGPR_and_tcGPRRegClassID - 32)) |
+    (1u << (ARM::hGPR_and_tGPRwithpcRegClassID - 32)) |
+    0,
+    // 64-95
+    0,
+    // 96-127
+    0,
+};
+
+RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 122);
+RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 122);
+} // end namespace ARM
+
+RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
+    &ARM::FPRRegBank,
+    &ARM::GPRRegBank,
+};
+
+ARMGenRegisterBankInfo::ARMGenRegisterBankInfo()
+    : RegisterBankInfo(RegBanks, ARM::NumRegisterBanks) {
+  // Assert that RegBank indices match their ID's
+#ifndef NDEBUG
+  unsigned Index = 0;
+  for (const auto &RB : RegBanks)
+    assert(Index++ == RB->getID() && "Index != ID");
+#endif // NDEBUG
+}
+} // end namespace llvm
+#endif // GET_TARGET_REGBANK_IMPL

third_party/llvm-10.0/configs/common/lib/Target/Mips/MipsGenExegesis.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Exegesis Tables                                                            *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+static const char* MipsPfmCounterNames[] = {
+  "CYCLES", // 0
+};
+
+
+static const PfmCountersInfo MipsDefaultPfmCounters = {
+  MipsPfmCounterNames[0],  // Cycle counter
+  nullptr,  // No uops counter.
+  nullptr,  // No issue counters.
+  0
+};
+
+// Sorted (by CpuName) array of pfm counters.
+static const CpuAndPfmCounters MipsCpuPfmCounters[] = {
+  { "", &MipsDefaultPfmCounters },
+};
+

third_party/llvm-10.0/configs/common/lib/Target/Mips/MipsGenRegisterBank.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Register Bank Source Fragments                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_REGBANK_DECLARATIONS
+#undef GET_REGBANK_DECLARATIONS
+namespace llvm {
+namespace Mips {
+enum {
+  FPRBRegBankID,
+  GPRBRegBankID,
+  NumRegisterBanks,
+};
+} // end namespace Mips
+} // end namespace llvm
+#endif // GET_REGBANK_DECLARATIONS
+
+#ifdef GET_TARGET_REGBANK_CLASS
+#undef GET_TARGET_REGBANK_CLASS
+private:
+  static RegisterBank *RegBanks[];
+
+protected:
+  MipsGenRegisterBankInfo();
+
+#endif // GET_TARGET_REGBANK_CLASS
+
+#ifdef GET_TARGET_REGBANK_IMPL
+#undef GET_TARGET_REGBANK_IMPL
+namespace llvm {
+namespace Mips {
+const uint32_t FPRBRegBankCoverageData[] = {
+    // 0-31
+    (1u << (Mips::FGR32RegClassID - 0)) |
+    (1u << (Mips::FGRCCRegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (Mips::FGR64RegClassID - 32)) |
+    (1u << (Mips::AFGR64RegClassID - 32)) |
+    0,
+    // 64-95
+    (1u << (Mips::MSA128DRegClassID - 64)) |
+    (1u << (Mips::MSA128BRegClassID - 64)) |
+    (1u << (Mips::MSA128HRegClassID - 64)) |
+    (1u << (Mips::MSA128WRegClassID - 64)) |
+    (1u << (Mips::MSA128WEvensRegClassID - 64)) |
+    0,
+};
+const uint32_t GPRBRegBankCoverageData[] = {
+    // 0-31
+    (1u << (Mips::GPR32RegClassID - 0)) |
+    (1u << (Mips::GPR32NONZERORegClassID - 0)) |
+    (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
+    (1u << (Mips::CPU16RegsRegClassID - 0)) |
+    (1u << (Mips::GPRMM16RegClassID - 0)) |
+    (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
+    (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
+    (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
+    (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
+    (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
+    (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
+    (1u << (Mips::CPUSPRegRegClassID - 0)) |
+    (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
+    (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
+    (1u << (Mips::CPURARegRegClassID - 0)) |
+    (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
+    (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
+    (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (Mips::SP32RegClassID - 32)) |
+    (1u << (Mips::GP32RegClassID - 32)) |
+    (1u << (Mips::GPR32ZERORegClassID - 32)) |
+    0,
+    // 64-95
+    0,
+};
+
+RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
+RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
+} // end namespace Mips
+
+RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
+    &Mips::FPRBRegBank,
+    &Mips::GPRBRegBank,
+};
+
+MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
+    : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
+  // Assert that RegBank indices match their ID's
+#ifndef NDEBUG
+  unsigned Index = 0;
+  for (const auto &RB : RegBanks)
+    assert(Index++ == RB->getID() && "Index != ID");
+#endif // NDEBUG
+}
+} // end namespace llvm
+#endif // GET_TARGET_REGBANK_IMPL

third_party/llvm-10.0/configs/common/lib/Target/PowerPC/PPCGenExegesis.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Exegesis Tables                                                            *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+static const char* PPCPfmCounterNames[] = {
+  "CYCLES", // 0
+};
+
+
+static const PfmCountersInfo PPCDefaultPfmCounters = {
+  PPCPfmCounterNames[0],  // Cycle counter
+  nullptr,  // No uops counter.
+  nullptr,  // No issue counters.
+  0
+};
+
+// Sorted (by CpuName) array of pfm counters.
+static const CpuAndPfmCounters PPCCpuPfmCounters[] = {
+  { "", &PPCDefaultPfmCounters },
+};
+

third_party/llvm-10.0/configs/common/lib/Target/X86/X86GenExegesis.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Exegesis Tables                                                            *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+static const char* X86PfmCounterNames[] = {
+  "cpu_clk_unhalted", // 0
+  "cycles_not_in_halt", // 1
+  "dispatched_fpu:pipe0", // 2
+  "dispatched_fpu:pipe1", // 3
+  "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0", // 4
+  "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1", // 5
+  "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2", // 6
+  "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3", // 7
+  "div_op_count", // 8
+  "fpu_pipe_assignment:total0", // 9
+  "fpu_pipe_assignment:total1", // 10
+  "fpu_pipe_assignment:total2", // 11
+  "fpu_pipe_assignment:total3", // 12
+  "retired_uops", // 13
+  "unhalted_core_cycles", // 14
+  "uops_dispatched_port:port_0", // 15
+  "uops_dispatched_port:port_1", // 16
+  "uops_dispatched_port:port_2", // 17
+  "uops_dispatched_port:port_2 + uops_dispatched_port:port_3", // 18
+  "uops_dispatched_port:port_3", // 19
+  "uops_dispatched_port:port_4", // 20
+  "uops_dispatched_port:port_5", // 21
+  "uops_dispatched_port:port_6", // 22
+  "uops_dispatched_port:port_7", // 23
+  "uops_executed_port:port_0", // 24
+  "uops_executed_port:port_1", // 25
+  "uops_executed_port:port_2", // 26
+  "uops_executed_port:port_3", // 27
+  "uops_executed_port:port_4", // 28
+  "uops_executed_port:port_5", // 29
+  "uops_executed_port:port_6", // 30
+  "uops_executed_port:port_7", // 31
+  "uops_issued:any", // 32
+  "uops_retired", // 33
+  "uops_retired:all", // 34
+  "uops_retired:any", // 35
+};
+
+static const PfmCountersInfo::IssueCounter X86PfmIssueCounters[] = {
+  { X86PfmCounterNames[4], "PdFPU0"},
+  { X86PfmCounterNames[5], "PdFPU1"},
+  { X86PfmCounterNames[6], "PdFPU2"},
+  { X86PfmCounterNames[7], "PdFPU3"},
+  { X86PfmCounterNames[4], "SrFPU0"},
+  { X86PfmCounterNames[5], "SrFPU1"},
+  { X86PfmCounterNames[6], "SrFPU2"},
+  { X86PfmCounterNames[24], "BWPort0"},
+  { X86PfmCounterNames[25], "BWPort1"},
+  { X86PfmCounterNames[26], "BWPort2"},
+  { X86PfmCounterNames[27], "BWPort3"},
+  { X86PfmCounterNames[28], "BWPort4"},
+  { X86PfmCounterNames[29], "BWPort5"},
+  { X86PfmCounterNames[30], "BWPort6"},
+  { X86PfmCounterNames[31], "BWPort7"},
+  { X86PfmCounterNames[2], "BtFPU0"},
+  { X86PfmCounterNames[3], "BtFPU1"},
+  { X86PfmCounterNames[2], "JFPU0"},
+  { X86PfmCounterNames[3], "JFPU1"},
+  { X86PfmCounterNames[24], "HWPort0"},
+  { X86PfmCounterNames[25], "HWPort1"},
+  { X86PfmCounterNames[26], "HWPort2"},
+  { X86PfmCounterNames[27], "HWPort3"},
+  { X86PfmCounterNames[28], "HWPort4"},
+  { X86PfmCounterNames[29], "HWPort5"},
+  { X86PfmCounterNames[30], "HWPort6"},
+  { X86PfmCounterNames[31], "HWPort7"},
+  { X86PfmCounterNames[15], "SBPort0"},
+  { X86PfmCounterNames[16], "SBPort1"},
+  { X86PfmCounterNames[18], "SBPort23"},
+  { X86PfmCounterNames[20], "SBPort4"},
+  { X86PfmCounterNames[21], "SBPort5"},
+  { X86PfmCounterNames[15], "SKLPort0"},
+  { X86PfmCounterNames[16], "SKLPort1"},
+  { X86PfmCounterNames[17], "SKLPort2"},
+  { X86PfmCounterNames[19], "SKLPort3"},
+  { X86PfmCounterNames[20], "SKLPort4"},
+  { X86PfmCounterNames[21], "SKLPort5"},
+  { X86PfmCounterNames[22], "SKLPort6"},
+  { X86PfmCounterNames[23], "SKLPort7"},
+  { X86PfmCounterNames[15], "SKXPort0"},
+  { X86PfmCounterNames[16], "SKXPort1"},
+  { X86PfmCounterNames[17], "SKXPort2"},
+  { X86PfmCounterNames[19], "SKXPort3"},
+  { X86PfmCounterNames[20], "SKXPort4"},
+  { X86PfmCounterNames[21], "SKXPort5"},
+  { X86PfmCounterNames[22], "SKXPort6"},
+  { X86PfmCounterNames[23], "SKXPort7"},
+  { X86PfmCounterNames[9], "ZnFPU0"},
+  { X86PfmCounterNames[10], "ZnFPU1"},
+  { X86PfmCounterNames[11], "ZnFPU2"},
+  { X86PfmCounterNames[12], "ZnFPU3"},
+  { X86PfmCounterNames[8], "ZnDivider"},
+};
+
+static const PfmCountersInfo X86AtomPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[35],  // Uops counter
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86BdVer2PfmCounters = {
+  X86PfmCounterNames[0],  // Cycle counter
+  X86PfmCounterNames[13],  // Uops counter
+  X86PfmIssueCounters + 0, 4 // Issue counters.
+};
+
+static const PfmCountersInfo X86BdVer3PfmCounters = {
+  X86PfmCounterNames[0],  // Cycle counter
+  X86PfmCounterNames[13],  // Uops counter
+  X86PfmIssueCounters + 4, 3 // Issue counters.
+};
+
+static const PfmCountersInfo X86BroadwellPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[32],  // Uops counter
+  X86PfmIssueCounters + 7, 8 // Issue counters.
+};
+
+static const PfmCountersInfo X86BtVer1PfmCounters = {
+  X86PfmCounterNames[0],  // Cycle counter
+  X86PfmCounterNames[13],  // Uops counter
+  X86PfmIssueCounters + 15, 2 // Issue counters.
+};
+
+static const PfmCountersInfo X86BtVer2PfmCounters = {
+  X86PfmCounterNames[0],  // Cycle counter
+  X86PfmCounterNames[13],  // Uops counter
+  X86PfmIssueCounters + 17, 2 // Issue counters.
+};
+
+static const PfmCountersInfo X86CorePfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[35],  // Uops counter
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86DefaultAMDPfmCounters = {
+  X86PfmCounterNames[0],  // Cycle counter
+  X86PfmCounterNames[13],  // Uops counter
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86DefaultPfmCounters = {
+  nullptr,  // No cycle counter.
+  nullptr,  // No uops counter.
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86HaswellPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[32],  // Uops counter
+  X86PfmIssueCounters + 19, 8 // Issue counters.
+};
+
+static const PfmCountersInfo X86KnightPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[34],  // Uops counter
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86PentiumPfmCounters = {
+  X86PfmCounterNames[0],  // Cycle counter
+  X86PfmCounterNames[33],  // Uops counter
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86SLMPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[35],  // Uops counter
+  nullptr,  // No issue counters.
+  0
+};
+
+static const PfmCountersInfo X86SandyBridgePfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[32],  // Uops counter
+  X86PfmIssueCounters + 27, 5 // Issue counters.
+};
+
+static const PfmCountersInfo X86SkylakeClientPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[32],  // Uops counter
+  X86PfmIssueCounters + 32, 8 // Issue counters.
+};
+
+static const PfmCountersInfo X86SkylakeServerPfmCounters = {
+  X86PfmCounterNames[14],  // Cycle counter
+  X86PfmCounterNames[32],  // Uops counter
+  X86PfmIssueCounters + 40, 8 // Issue counters.
+};
+
+static const PfmCountersInfo X86ZnVer1PfmCounters = {
+  X86PfmCounterNames[1],  // Cycle counter
+  X86PfmCounterNames[13],  // Uops counter
+  X86PfmIssueCounters + 48, 5 // Issue counters.
+};
+
+// Sorted (by CpuName) array of pfm counters.
+static const CpuAndPfmCounters X86CpuPfmCounters[] = {
+  { "", &X86DefaultPfmCounters },
+  { "amdfam10", &X86DefaultAMDPfmCounters },
+  { "athlon", &X86DefaultAMDPfmCounters },
+  { "athlon-4", &X86DefaultAMDPfmCounters },
+  { "athlon-fx", &X86DefaultAMDPfmCounters },
+  { "athlon-mp", &X86DefaultAMDPfmCounters },
+  { "athlon-tbird", &X86DefaultAMDPfmCounters },
+  { "athlon-xp", &X86DefaultAMDPfmCounters },
+  { "athlon64", &X86DefaultAMDPfmCounters },
+  { "athlon64-sse3", &X86DefaultAMDPfmCounters },
+  { "atom", &X86AtomPfmCounters },
+  { "barcelona", &X86DefaultAMDPfmCounters },
+  { "bdver1", &X86BdVer2PfmCounters },
+  { "bdver2", &X86BdVer2PfmCounters },
+  { "bdver3", &X86BdVer3PfmCounters },
+  { "bdver4", &X86BdVer3PfmCounters },
+  { "bonnell", &X86AtomPfmCounters },
+  { "broadwell", &X86BroadwellPfmCounters },
+  { "btver1", &X86BtVer1PfmCounters },
+  { "btver2", &X86BtVer2PfmCounters },
+  { "cannonlake", &X86SkylakeServerPfmCounters },
+  { "cascadelake", &X86SkylakeServerPfmCounters },
+  { "core2", &X86CorePfmCounters },
+  { "corei7", &X86CorePfmCounters },
+  { "goldmont", &X86SLMPfmCounters },
+  { "goldmont-plus", &X86SLMPfmCounters },
+  { "haswell", &X86HaswellPfmCounters },
+  { "icelake-client", &X86SkylakeServerPfmCounters },
+  { "icelake-server", &X86SkylakeServerPfmCounters },
+  { "ivybridge", &X86SandyBridgePfmCounters },
+  { "k8", &X86DefaultAMDPfmCounters },
+  { "k8-sse3", &X86DefaultAMDPfmCounters },
+  { "knl", &X86KnightPfmCounters },
+  { "knm", &X86KnightPfmCounters },
+  { "nehalem", &X86CorePfmCounters },
+  { "opteron", &X86DefaultAMDPfmCounters },
+  { "opteron-sse3", &X86DefaultAMDPfmCounters },
+  { "penryn", &X86CorePfmCounters },
+  { "pentium-m", &X86PentiumPfmCounters },
+  { "pentium2", &X86PentiumPfmCounters },
+  { "pentium3", &X86PentiumPfmCounters },
+  { "pentium3m", &X86PentiumPfmCounters },
+  { "pentiumpro", &X86PentiumPfmCounters },
+  { "prescott", &X86CorePfmCounters },
+  { "sandybridge", &X86SandyBridgePfmCounters },
+  { "silvermont", &X86SLMPfmCounters },
+  { "skylake", &X86SkylakeClientPfmCounters },
+  { "skylake-avx512", &X86SkylakeServerPfmCounters },
+  { "tremont", &X86SLMPfmCounters },
+  { "westmere", &X86CorePfmCounters },
+  { "yonah", &X86CorePfmCounters },
+  { "znver1", &X86ZnVer1PfmCounters },
+};
+

third_party/llvm-10.0/configs/common/lib/Target/X86/X86GenRegisterBank.inc

+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Register Bank Source Fragments                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_REGBANK_DECLARATIONS
+#undef GET_REGBANK_DECLARATIONS
+namespace llvm {
+namespace X86 {
+enum {
+  GPRRegBankID,
+  VECRRegBankID,
+  NumRegisterBanks,
+};
+} // end namespace X86
+} // end namespace llvm
+#endif // GET_REGBANK_DECLARATIONS
+
+#ifdef GET_TARGET_REGBANK_CLASS
+#undef GET_TARGET_REGBANK_CLASS
+private:
+  static RegisterBank *RegBanks[];
+
+protected:
+  X86GenRegisterBankInfo();
+
+#endif // GET_TARGET_REGBANK_CLASS
+
+#ifdef GET_TARGET_REGBANK_IMPL
+#undef GET_TARGET_REGBANK_IMPL
+namespace llvm {
+namespace X86 {
+const uint32_t GPRRegBankCoverageData[] = {
+    // 0-31
+    (1u << (X86::GR8RegClassID - 0)) |
+    (1u << (X86::GR16RegClassID - 0)) |
+    (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
+    (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
+    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
+    (1u << (X86::GR8_NOREXRegClassID - 0)) |
+    (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
+    (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
+    (1u << (X86::GR16_NOREXRegClassID - 0)) |
+    (1u << (X86::GR16_ABCDRegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (X86::GR32RegClassID - 32)) |
+    (1u << (X86::GR32_NOSPRegClassID - 32)) |
+    (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
+    (1u << (X86::GR32_NOREXRegClassID - 32)) |
+    (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
+    (1u << (X86::GR32_ABCDRegClassID - 32)) |
+    (1u << (X86::GR32_TCRegClassID - 32)) |
+    (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) |
+    (1u << (X86::GR32_ADRegClassID - 32)) |
+    (1u << (X86::GR32_DCRegClassID - 32)) |
+    (1u << (X86::GR32_AD_and_GR32_DCRegClassID - 32)) |
+    (1u << (X86::GR32_CBRegClassID - 32)) |
+    (1u << (X86::GR32_CB_and_GR32_DCRegClassID - 32)) |
+    (1u << (X86::GR32_SIDIRegClassID - 32)) |
+    (1u << (X86::GR32_BSIRegClassID - 32)) |
+    (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 32)) |
+    (1u << (X86::GR32_DIBPRegClassID - 32)) |
+    (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 32)) |
+    (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
+    (1u << (X86::GR32_BPSPRegClassID - 32)) |
+    (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 32)) |
+    (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 32)) |
+    0,
+    // 64-95
+    (1u << (X86::GR64RegClassID - 64)) |
+    (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) |
+    (1u << (X86::GR64_NOSPRegClassID - 64)) |
+    (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 64)) |
+    (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 64)) |
+    (1u << (X86::GR64_ADRegClassID - 64)) |
+    (1u << (X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID - 64)) |
+    (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
+    (1u << (X86::GR64_ABCDRegClassID - 64)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 64)) |
+    (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 64)) |
+    (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) |
+    (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 64)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) |
+    (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
+    (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) |
+    (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 64)) |
+    (1u << (X86::GR64_TCRegClassID - 64)) |
+    (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
+    (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) |
+    (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
+    (1u << (X86::GR64_NOREXRegClassID - 64)) |
+    (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) |
+    (1u << (X86::GR64_TCW64RegClassID - 64)) |
+    0,
+    // 96-127
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_DCRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) |
+    (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) |
+    (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) |
+    0,
+};
+const uint32_t VECRRegBankCoverageData[] = {
+    // 0-31
+    (1u << (X86::FR32XRegClassID - 0)) |
+    0,
+    // 32-63
+    (1u << (X86::FR32RegClassID - 32)) |
+    0,
+    // 64-95
+    (1u << (X86::FR64XRegClassID - 64)) |
+    (1u << (X86::FR64RegClassID - 64)) |
+    0,
+    // 96-127
+    (1u << (X86::VR512RegClassID - 96)) |
+    (1u << (X86::VR128XRegClassID - 96)) |
+    (1u << (X86::VR256XRegClassID - 96)) |
+    (1u << (X86::VR512_0_15RegClassID - 96)) |
+    (1u << (X86::VR128RegClassID - 96)) |
+    (1u << (X86::VR256RegClassID - 96)) |
+    0,
+};
+
+RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 118);
+RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 118);
+} // end namespace X86
+
+RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
+    &X86::GPRRegBank,
+    &X86::VECRRegBank,
+};
+
+X86GenRegisterBankInfo::X86GenRegisterBankInfo()
+    : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) {
+  // Assert that RegBank indices match their ID's
+#ifndef NDEBUG
+  unsigned Index = 0;
+  for (const auto &RB : RegBanks)
+    assert(Index++ == RB->getID() && "Index != ID");
+#endif // NDEBUG
+}
+} // end namespace llvm
+#endif // GET_TARGET_REGBANK_IMPL

third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmParsers.def

+/*===- llvm/Config/AsmParsers.def - LLVM Assembly Parsers -------*- C++ -*-===*\
+|*                                                                            *|
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
+|* Exceptions.                                                                *|
+|* See https://llvm.org/LICENSE.txt for license information.                  *|
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *|
+|*                                                                            *|
+|*===----------------------------------------------------------------------===*|
+|*                                                                            *|
+|* This file enumerates all of the assembly-language parsers                  *|
+|* supported by this build of LLVM. Clients of this file should define        *|
+|* the LLVM_ASM_PARSER macro to be a function-like macro with a               *|
+|* single parameter (the name of the target whose assembly can be             *|
+|* generated); including this file will then enumerate all of the             *|
+|* targets with assembly parsers.                                             *|
+|*                                                                            *|
+|* The set of targets supported by LLVM is generated at configuration         *|
+|* time, at which point this header is generated. Do not modify this          *|
+|* header directly.                                                           *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_ASM_PARSER
+#  error Please define the macro LLVM_ASM_PARSER(TargetName)
+#endif
+
+LLVM_ASM_PARSER(AArch64)
+LLVM_ASM_PARSER(AMDGPU)
+LLVM_ASM_PARSER(ARM)
+LLVM_ASM_PARSER(BPF)
+LLVM_ASM_PARSER(Hexagon)
+LLVM_ASM_PARSER(Lanai)
+LLVM_ASM_PARSER(Mips)
+LLVM_ASM_PARSER(MSP430)
+LLVM_ASM_PARSER(PowerPC)
+LLVM_ASM_PARSER(RISCV)
+LLVM_ASM_PARSER(Sparc)
+LLVM_ASM_PARSER(SystemZ)
+LLVM_ASM_PARSER(WebAssembly)
+LLVM_ASM_PARSER(X86)
+
+
+#undef LLVM_ASM_PARSER

third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmPrinters.def

+/*===- llvm/Config/AsmPrinters.def - LLVM Assembly Printers -----*- C++ -*-===*\
+|*                                                                            *|
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
+|* Exceptions.                                                                *|
+|* See https://llvm.org/LICENSE.txt for license information.                  *|
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *|
+|*                                                                            *|
+|*===----------------------------------------------------------------------===*|
+|*                                                                            *|
+|* This file enumerates all of the assembly-language printers                 *|
+|* supported by this build of LLVM. Clients of this file should define        *|
+|* the LLVM_ASM_PRINTER macro to be a function-like macro with a              *|
+|* single parameter (the name of the target whose assembly can be             *|
+|* generated); including this file will then enumerate all of the             *|
+|* targets with assembly printers.                                            *|
+|*                                                                            *|
+|* The set of targets supported by LLVM is generated at configuration         *|
+|* time, at which point this header is generated. Do not modify this          *|
+|* header directly.                                                           *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_ASM_PRINTER
+#  error Please define the macro LLVM_ASM_PRINTER(TargetName)
+#endif
+
+LLVM_ASM_PRINTER(AArch64)
+LLVM_ASM_PRINTER(AMDGPU)
+LLVM_ASM_PRINTER(ARM)
+LLVM_ASM_PRINTER(BPF)
+LLVM_ASM_PRINTER(Hexagon)
+LLVM_ASM_PRINTER(Lanai)
+LLVM_ASM_PRINTER(Mips)
+LLVM_ASM_PRINTER(MSP430)
+LLVM_ASM_PRINTER(NVPTX)
+LLVM_ASM_PRINTER(PowerPC)
+LLVM_ASM_PRINTER(RISCV)
+LLVM_ASM_PRINTER(Sparc)
+LLVM_ASM_PRINTER(SystemZ)
+LLVM_ASM_PRINTER(WebAssembly)
+LLVM_ASM_PRINTER(X86)
+LLVM_ASM_PRINTER(XCore)
+
+
+#undef LLVM_ASM_PRINTER

third_party/llvm-10.0/configs/linux/include/llvm/Config/Disassemblers.def

+/*===- llvm/Config/Disassemblers.def - LLVM Assembly Parsers ----*- C++ -*-===*\
+|*                                                                            *|
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
+|* Exceptions.                                                                *|
+|* See https://llvm.org/LICENSE.txt for license information.                  *|
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *|
+|*                                                                            *|
+|*===----------------------------------------------------------------------===*|
+|*                                                                            *|
+|* This file enumerates all of the assembly-language parsers                  *|
+|* supported by this build of LLVM. Clients of this file should define        *|
+|* the LLVM_DISASSEMBLER macro to be a function-like macro with a             *|
+|* single parameter (the name of the target whose assembly can be             *|
+|* generated); including this file will then enumerate all of the             *|
+|* targets with assembly parsers.                                             *|
+|*                                                                            *|
+|* The set of targets supported by LLVM is generated at configuration         *|
+|* time, at which point this header is generated. Do not modify this          *|
+|* header directly.                                                           *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_DISASSEMBLER
+#  error Please define the macro LLVM_DISASSEMBLER(TargetName)
+#endif
+
+LLVM_DISASSEMBLER(AArch64)
+LLVM_DISASSEMBLER(AMDGPU)
+LLVM_DISASSEMBLER(ARM)
+LLVM_DISASSEMBLER(BPF)
+LLVM_DISASSEMBLER(Hexagon)
+LLVM_DISASSEMBLER(Lanai)
+LLVM_DISASSEMBLER(Mips)
+LLVM_DISASSEMBLER(MSP430)
+LLVM_DISASSEMBLER(PowerPC)
+LLVM_DISASSEMBLER(RISCV)
+LLVM_DISASSEMBLER(Sparc)
+LLVM_DISASSEMBLER(SystemZ)
+LLVM_DISASSEMBLER(WebAssembly)
+LLVM_DISASSEMBLER(X86)
+LLVM_DISASSEMBLER(XCore)
+
+
+#undef LLVM_DISASSEMBLER

third_party/llvm-10.0/configs/linux/include/llvm/Config/Targets.def

+/*===- llvm/Config/Targets.def - LLVM Target Architectures ------*- C++ -*-===*\
+|*                                                                            *|
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM          *|
+|* Exceptions.                                                                *|
+|* See https://llvm.org/LICENSE.txt for license information.                  *|
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    *|
+|*                                                                            *|
+|*===----------------------------------------------------------------------===*|
+|*                                                                            *|
+|* This file enumerates all of the target architectures supported by          *|
+|* this build of LLVM. Clients of this file should define the                 *|
+|* LLVM_TARGET macro to be a function-like macro with a single                *|
+|* parameter (the name of the target); including this file will then          *|
+|* enumerate all of the targets.                                              *|
+|*                                                                            *|
+|* The set of targets supported by LLVM is generated at configuration         *|
+|* time, at which point this header is generated. Do not modify this          *|
+|* header directly.                                                           *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#ifndef LLVM_TARGET
+#  error Please define the macro LLVM_TARGET(TargetName)
+#endif
+
+LLVM_TARGET(AArch64)
+LLVM_TARGET(AMDGPU)
+LLVM_TARGET(ARM)
+LLVM_TARGET(BPF)
+LLVM_TARGET(Hexagon)
+LLVM_TARGET(Lanai)
+LLVM_TARGET(Mips)
+LLVM_TARGET(MSP430)
+LLVM_TARGET(NVPTX)
+LLVM_TARGET(PowerPC)
+LLVM_TARGET(RISCV)
+LLVM_TARGET(Sparc)
+LLVM_TARGET(SystemZ)
+LLVM_TARGET(WebAssembly)
+LLVM_TARGET(X86)
+LLVM_TARGET(XCore)
+
+
+#undef LLVM_TARGET

third_party/llvm-10.0/configs/linux/include/llvm/Config/abi-breaking.h

+/*===------- llvm/Config/abi-breaking.h - llvm configuration -------*- C -*-===*/
+/*                                                                            */
+/* Part of the LLVM Project, under the Apache License v2.0 with LLVM          */
+/* Exceptions.                                                                */
+/* See https://llvm.org/LICENSE.txt for license information.                  */
+/* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    */
+/*                                                                            */
+/*===----------------------------------------------------------------------===*/
+
+/* This file controls the C++ ABI break introduced in LLVM public header. */
+
+#ifndef LLVM_ABI_BREAKING_CHECKS_H
+#define LLVM_ABI_BREAKING_CHECKS_H
+
+/* Define to enable checks that alter the LLVM C++ ABI */
+#define LLVM_ENABLE_ABI_BREAKING_CHECKS 1
+
+/* Define to enable reverse iteration of unordered llvm containers */
+#define LLVM_ENABLE_REVERSE_ITERATION 0
+
+/* Allow selectively disabling link-time mismatch checking so that header-only
+   ADT content from LLVM can be used without linking libSupport. */
+#if !LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING
+
+// ABI_BREAKING_CHECKS protection: provides link-time failure when clients build
+// mismatch with LLVM
+#if defined(_MSC_VER)
+// Use pragma with MSVC
+#define LLVM_XSTR(s) LLVM_STR(s)
+#define LLVM_STR(s) #s
+#pragma detect_mismatch("LLVM_ENABLE_ABI_BREAKING_CHECKS", LLVM_XSTR(LLVM_ENABLE_ABI_BREAKING_CHECKS))
+#undef LLVM_XSTR
+#undef LLVM_STR
+#elif defined(_WIN32) || defined(__CYGWIN__) // Win32 w/o #pragma detect_mismatch
+// FIXME: Implement checks without weak.
+#elif defined(__cplusplus)
+#if !(defined(_AIX) && defined(__GNUC__) && !defined(__clang__))
+#define LLVM_HIDDEN_VISIBILITY __attribute__ ((visibility("hidden")))
+#else
+// GCC on AIX does not support visibility attributes. Symbols are not
+// exported by default on AIX.
+#define LLVM_HIDDEN_VISIBILITY
+#endif
+namespace llvm {
+#if LLVM_ENABLE_ABI_BREAKING_CHECKS
+extern int EnableABIBreakingChecks;
+LLVM_HIDDEN_VISIBILITY
+__attribute__((weak)) int *VerifyEnableABIBreakingChecks =
+    &EnableABIBreakingChecks;
+#else
+extern int DisableABIBreakingChecks;
+LLVM_HIDDEN_VISIBILITY
+__attribute__((weak)) int *VerifyDisableABIBreakingChecks =
+    &DisableABIBreakingChecks;
+#endif
+}
+#undef LLVM_HIDDEN_VISIBILITY
+#endif // _MSC_VER
+
+#endif // LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING
+
+#endif

third_party/llvm-10.0/configs/linux/include/llvm/Config/config.h

+#ifndef CONFIG_H
+#define CONFIG_H
+
+/* Exported configuration */
+#include "llvm/Config/llvm-config.h"
+
+/* Bug report URL. */
+#define BUG_REPORT_URL "https://bugs.llvm.org/"
+
+/* Define to 1 to enable backtraces, and to 0 otherwise. */
+#define ENABLE_BACKTRACES 1
+
+/* Define to 1 to enable crash overrides, and to 0 otherwise. */
+#define ENABLE_CRASH_OVERRIDES 1
+
+/* Define to 1 to enable crash memory dumps, and to 0 otherwise. */
+#define LLVM_ENABLE_CRASH_DUMPS 0
+
+/* Define to 1 if you have the `backtrace' function. */
+#define HAVE_BACKTRACE TRUE
+
+#define BACKTRACE_HEADER <execinfo.h>
+
+/* Define to 1 if you have the <CrashReporterClient.h> header file. */
+/* #undef HAVE_CRASHREPORTERCLIENT_H */
+
+/* can use __crashreporter_info__ */
+#define HAVE_CRASHREPORTER_INFO 0
+
+/* Define to 1 if you have the declaration of `arc4random', and to 0 if you
+   don't. */
+#define HAVE_DECL_ARC4RANDOM 0
+
+/* Define to 1 if you have the declaration of `FE_ALL_EXCEPT', and to 0 if you
+   don't. */
+#define HAVE_DECL_FE_ALL_EXCEPT 1
+
+/* Define to 1 if you have the declaration of `FE_INEXACT', and to 0 if you
+   don't. */
+#define HAVE_DECL_FE_INEXACT 1
+
+/* Define to 1 if you have the declaration of `strerror_s', and to 0 if you
+   don't. */
+#define HAVE_DECL_STRERROR_S 0
+
+/* Define to 1 if you have the DIA SDK installed, and to 0 if you don't. */
+#define LLVM_ENABLE_DIA_SDK 0
+
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#define HAVE_DLFCN_H 1
+
+/* Define if dlopen() is available on this platform. */
+#define HAVE_DLOPEN 1
+
+/* Define if dladdr() is available on this platform. */
+/* #undef HAVE_DLADDR */
+
+/* Define to 1 if you have the <errno.h> header file. */
+#define HAVE_ERRNO_H 1
+
+/* Define to 1 if you have the <fcntl.h> header file. */
+#define HAVE_FCNTL_H 1
+
+/* Define to 1 if you have the <fenv.h> header file. */
+#define HAVE_FENV_H 1
+
+/* Define if libffi is available on this platform. */
+/* #undef HAVE_FFI_CALL */
+
+/* Define to 1 if you have the <ffi/ffi.h> header file. */
+/* #undef HAVE_FFI_FFI_H */
+
+/* Define to 1 if you have the <ffi.h> header file. */
+/* #undef HAVE_FFI_H */
+
+/* Define to 1 if you have the `futimens' function. */
+#define HAVE_FUTIMENS 1
+
+/* Define to 1 if you have the `futimes' function. */
+#define HAVE_FUTIMES 1
+
+/* Define to 1 if you have the `getpagesize' function. */
+#define HAVE_GETPAGESIZE 1
+
+/* Define to 1 if you have the `getrlimit' function. */
+#define HAVE_GETRLIMIT 1
+
+/* Define to 1 if you have the `getrusage' function. */
+#define HAVE_GETRUSAGE 1
+
+/* Define to 1 if you have the `isatty' function. */
+#define HAVE_ISATTY 1
+
+/* Define to 1 if you have the `edit' library (-ledit). */
+/* #undef HAVE_LIBEDIT */
+
+/* Define to 1 if you have the `pfm' library (-lpfm). */
+/* #undef HAVE_LIBPFM */
+
+/* Define to 1 if you have the `psapi' library (-lpsapi). */
+/* #undef HAVE_LIBPSAPI */
+
+/* Define to 1 if you have the `pthread' library (-lpthread). */
+#define HAVE_LIBPTHREAD 1
+
+/* Define to 1 if you have the `pthread_getname_np' function. */
+#define HAVE_PTHREAD_GETNAME_NP 1
+
+/* Define to 1 if you have the `pthread_setname_np' function. */
+#define HAVE_PTHREAD_SETNAME_NP 1
+
+/* Define to 1 if you have the `z' library (-lz). */
+#define HAVE_LIBZ 1
+
+/* Define to 1 if you have the <link.h> header file. */
+#define HAVE_LINK_H 1
+
+/* Define to 1 if you have the `lseek64' function. */
+#define HAVE_LSEEK64 1
+
+/* Define to 1 if you have the <mach/mach.h> header file. */
+/* #undef HAVE_MACH_MACH_H */
+
+/* Define to 1 if you have the `mallctl' function. */
+/* #undef HAVE_MALLCTL */
+
+/* Define to 1 if you have the `mallinfo' function. */
+#define HAVE_MALLINFO 1
+
+/* Define to 1 if you have the <malloc/malloc.h> header file. */
+/* #undef HAVE_MALLOC_MALLOC_H */
+
+/* Define to 1 if you have the `malloc_zone_statistics' function. */
+/* #undef HAVE_MALLOC_ZONE_STATISTICS */
+
+/* Define to 1 if you have the `posix_fallocate' function. */
+#define HAVE_POSIX_FALLOCATE 1
+
+/* Define to 1 if you have the `posix_spawn' function. */
+#define HAVE_POSIX_SPAWN 1
+
+/* Define to 1 if you have the `pread' function. */
+#define HAVE_PREAD 1
+
+/* Have pthread_getspecific */
+#define HAVE_PTHREAD_GETSPECIFIC 1
+
+/* Define to 1 if you have the <pthread.h> header file. */
+#define HAVE_PTHREAD_H 1
+
+/* Have pthread_mutex_lock */
+#define HAVE_PTHREAD_MUTEX_LOCK 1
+
+/* Have pthread_rwlock_init */
+#define HAVE_PTHREAD_RWLOCK_INIT 1
+
+/* Define to 1 if you have the `sbrk' function. */
+#define HAVE_SBRK 1
+
+/* Define to 1 if you have the `setenv' function. */
+#define HAVE_SETENV 1
+
+/* Define to 1 if you have the `sched_getaffinity' function. */
+#define HAVE_SCHED_GETAFFINITY 1
+
+/* Define to 1 if you have the `CPU_COUNT' macro. */
+#define HAVE_CPU_COUNT 1
+
+/* Define to 1 if you have the `setrlimit' function. */
+#define HAVE_SETRLIMIT 1
+
+/* Define to 1 if you have the `sigaltstack' function. */
+#define HAVE_SIGALTSTACK 1
+
+/* Define to 1 if you have the <signal.h> header file. */
+#define HAVE_SIGNAL_H 1
+
+/* Define to 1 if you have the `strerror' function. */
+#define HAVE_STRERROR 1
+
+/* Define to 1 if you have the `strerror_r' function. */
+#define HAVE_STRERROR_R 1
+
+/* Define to 1 if you have the `sysconf' function. */
+#define HAVE_SYSCONF 1
+
+/* Define to 1 if you have the <sys/ioctl.h> header file. */
+#define HAVE_SYS_IOCTL_H 1
+
+/* Define to 1 if you have the <sys/mman.h> header file. */
+#define HAVE_SYS_MMAN_H 1
+
+/* Define to 1 if you have the <sys/param.h> header file. */
+#define HAVE_SYS_PARAM_H 1
+
+/* Define to 1 if you have the <sys/resource.h> header file. */
+#define HAVE_SYS_RESOURCE_H 1
+
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#define HAVE_SYS_STAT_H 1
+
+/* Define to 1 if you have the <sys/time.h> header file. */
+#define HAVE_SYS_TIME_H 1
+
+/* Define to 1 if stat struct has st_mtimespec member .*/
+/* #undef HAVE_STRUCT_STAT_ST_MTIMESPEC_TV_NSEC */
+
+/* Define to 1 if stat struct has st_mtim member. */
+#define HAVE_STRUCT_STAT_ST_MTIM_TV_NSEC 1
+
+/* Define to 1 if you have the <sys/types.h> header file. */
+#define HAVE_SYS_TYPES_H 1
+
+/* Define if the setupterm() function is supported this platform. */
+/* #undef HAVE_TERMINFO */
+
+/* Define if the xar_open() function is supported this platform. */
+/* #undef HAVE_LIBXAR */
+
+/* Define to 1 if you have the <termios.h> header file. */
+#define HAVE_TERMIOS_H 1
+
+/* Define to 1 if you have the <unistd.h> header file. */
+#define HAVE_UNISTD_H 1
+
+/* Define to 1 if you have the <valgrind/valgrind.h> header file. */
+/* #undef HAVE_VALGRIND_VALGRIND_H */
+
+/* Define to 1 if you have the <zlib.h> header file. */
+#define HAVE_ZLIB_H 1
+
+/* Have host's _alloca */
+/* #undef HAVE__ALLOCA */
+
+/* Define to 1 if you have the `_chsize_s' function. */
+/* #undef HAVE__CHSIZE_S */
+
+/* Define to 1 if you have the `_Unwind_Backtrace' function. */
+#define HAVE__UNWIND_BACKTRACE 1
+
+/* Have host's __alloca */
+/* #undef HAVE___ALLOCA */
+
+/* Have host's __ashldi3 */
+/* #undef HAVE___ASHLDI3 */
+
+/* Have host's __ashrdi3 */
+/* #undef HAVE___ASHRDI3 */
+
+/* Have host's __chkstk */
+/* #undef HAVE___CHKSTK */
+
+/* Have host's __chkstk_ms */
+/* #undef HAVE___CHKSTK_MS */
+
+/* Have host's __cmpdi2 */
+/* #undef HAVE___CMPDI2 */
+
+/* Have host's __divdi3 */
+/* #undef HAVE___DIVDI3 */
+
+/* Have host's __fixdfdi */
+/* #undef HAVE___FIXDFDI */
+
+/* Have host's __fixsfdi */
+/* #undef HAVE___FIXSFDI */
+
+/* Have host's __floatdidf */
+/* #undef HAVE___FLOATDIDF */
+
+/* Have host's __lshrdi3 */
+/* #undef HAVE___LSHRDI3 */
+
+/* Have host's __main */
+/* #undef HAVE___MAIN */
+
+/* Have host's __moddi3 */
+/* #undef HAVE___MODDI3 */
+
+/* Have host's __udivdi3 */
+/* #undef HAVE___UDIVDI3 */
+
+/* Have host's __umoddi3 */
+/* #undef HAVE___UMODDI3 */
+
+/* Have host's ___chkstk */
+/* #undef HAVE____CHKSTK */
+
+/* Have host's ___chkstk_ms */
+/* #undef HAVE____CHKSTK_MS */
+
+/* Linker version detected at compile time. */
+/* #undef HOST_LINK_VERSION */
+
+/* Target triple LLVM will generate code for by default */
+/* Doesn't use `cmakedefine` because it is allowed to be empty. */
+#define LLVM_DEFAULT_TARGET_TRIPLE "x86_64-unknown-linux-gnu"
+
+/* Define if zlib compression is available */
+#define LLVM_ENABLE_ZLIB 1
+
+/* Define if overriding target triple is enabled */
+/* #undef LLVM_TARGET_TRIPLE_ENV */
+
+/* LLVM version information */
+/* #undef LLVM_VERSION_INFO */
+
+/* Whether tools show host and target info when invoked with --version */
+#define LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO 1
+
+/* Define if libxml2 is supported on this platform. */
+#define LLVM_LIBXML2_ENABLED 1
+
+/* Define to the extension used for shared libraries, say, ".so". */
+#define LTDL_SHLIB_EXT ".so"
+
+/* Define to the address where bug reports for this package should be sent. */
+#define PACKAGE_BUGREPORT "https://bugs.llvm.org/"
+
+/* Define to the full name of this package. */
+#define PACKAGE_NAME "LLVM"
+
+/* Define to the full name and version of this package. */
+#define PACKAGE_STRING "LLVM 10.0.0"
+
+/* Define to the version of this package. */
+#define PACKAGE_VERSION "10.0.0"
+
+/* Define to the vendor of this package. */
+/* #undef PACKAGE_VENDOR */
+
+/* Define as the return type of signal handlers (`int' or `void'). */
+#define RETSIGTYPE void
+
+/* Define if std::is_trivially_copyable is supported */
+#define HAVE_STD_IS_TRIVIALLY_COPYABLE 1
+
+/* Define to a function implementing stricmp */
+/* #undef stricmp */
+
+/* Define to a function implementing strdup */
+/* #undef strdup */
+
+/* Whether GlobalISel rule coverage is being collected */
+#define LLVM_GISEL_COV_ENABLED 0
+
+/* Define if we have z3 and want to build it */
+/* #undef LLVM_WITH_Z3 */
+
+/* Define to the default GlobalISel coverage file prefix */
+/* #undef LLVM_GISEL_COV_PREFIX */
+
+/* Whether Timers signpost passes in Xcode Instruments */
+#define LLVM_SUPPORT_XCODE_SIGNPOSTS 0
+
+#endif

third_party/llvm-10.0/configs/linux/include/llvm/Config/llvm-config.h

+/*===------- llvm/Config/llvm-config.h - llvm configuration -------*- C -*-===*/
+/*                                                                            */
+/* Part of the LLVM Project, under the Apache License v2.0 with LLVM          */
+/* Exceptions.                                                                */
+/* See https://llvm.org/LICENSE.txt for license information.                  */
+/* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception                    */
+/*                                                                            */
+/*===----------------------------------------------------------------------===*/
+
+/* This file enumerates variables from the LLVM configuration so that they
+   can be in exported headers and won't override package specific directives.
+   This is a C header that can be included in the llvm-c headers. */
+
+#ifndef LLVM_CONFIG_H
+#define LLVM_CONFIG_H
+
+/* Define if LLVM_ENABLE_DUMP is enabled */
+/* #undef LLVM_ENABLE_DUMP */
+
+/* Target triple LLVM will generate code for by default */
+#define LLVM_DEFAULT_TARGET_TRIPLE "x86_64-unknown-linux-gnu"
+
+/* Define if threads enabled */
+#define LLVM_ENABLE_THREADS 1
+
+/* Has gcc/MSVC atomic intrinsics */
+#define LLVM_HAS_ATOMICS 1
+
+/* Host triple LLVM will be executed on */
+#define LLVM_HOST_TRIPLE "x86_64-unknown-linux-gnu"
+
+/* LLVM architecture name for the native architecture, if available */
+#define LLVM_NATIVE_ARCH X86
+
+/* LLVM name for the native AsmParser init function, if available */
+#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
+
+/* LLVM name for the native AsmPrinter init function, if available */
+#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
+
+/* LLVM name for the native Disassembler init function, if available */
+#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler
+
+/* LLVM name for the native Target init function, if available */
+#define LLVM_NATIVE_TARGET LLVMInitializeX86Target
+
+/* LLVM name for the native TargetInfo init function, if available */
+#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo
+
+/* LLVM name for the native target MC init function, if available */
+#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC
+
+/* Define if this is Unixish platform */
+#define LLVM_ON_UNIX 1
+
+/* Define if we have the Intel JIT API runtime support library */
+#define LLVM_USE_INTEL_JITEVENTS 0
+
+/* Define if we have the oprofile JIT-support library */
+#define LLVM_USE_OPROFILE 0
+
+/* Define if we have the perf JIT-support library */
+#define LLVM_USE_PERF 0
+
+/* Major version of the LLVM API */
+#define LLVM_VERSION_MAJOR 10
+
+/* Minor version of the LLVM API */
+#define LLVM_VERSION_MINOR 0
+
+/* Patch version of the LLVM API */
+#define LLVM_VERSION_PATCH 0
+
+/* LLVM version string */
+#define LLVM_VERSION_STRING "10.0.0"
+
+/* Whether LLVM records statistics for use with GetStatistics(),
+ * PrintStatistics() or PrintStatisticsJSON()
+ */
+#define LLVM_FORCE_ENABLE_STATS 0
+
+#endif