Subzero: Don't "and" i1 values with 1.

In x86 lowering, i1 values are held in i8 register and memory slots. We were conservatively "and"ing them with 1 before zero-extending them for some lowering operations, but this "and" with 1 is unnecessary and just clutters the code. We continue the invariant that all i1-produced values in an i8 slot are either 0 or 1. BUG= https://code.google.com/p/nativeclient/issues/detail?id=4095 R=jpp@chromium.org Review URL: https://codereview.chromium.org/1394413002 .

Subzero: Don't "and" i1 values with 1.
485d0773 · Jim Stichnoth · 69a85b14 · 485d0773 · 485d0773 · 485d0773
Commit 485d0773 authored Oct 09, 2015 by Jim Stichnoth
4 changed files
--- a/src/IceTargetLoweringX86BaseImpl.h
+++ b/src/IceTargetLoweringX86BaseImpl.h
@@ -2047,15 +2047,10 @@ void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
      } else {
        _movzx(Tmp, Src0RM);
      }
-      if (Src0RM->getType() == IceType_i1) {
-        Constant *One = Ctx->getConstantInt32(1);
-        _and(Tmp, One);
-      }
      _mov(DestLo, Tmp);
      _mov(DestHi, Zero);
    } else if (Src0RM->getType() == IceType_i1) {
-      // t = Src0RM; t &= 1; Dest = t
-      Constant *One = Ctx->getConstantInt32(1);
+      // t = Src0RM; Dest = t
      Type DestTy = Dest->getType();
      Variable *T = nullptr;
      if (DestTy == IceType_i8) {
@@ -2069,7 +2064,6 @@ void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
        T = makeReg(DestTy == IceType_i64 ? IceType_i64 : IceType_i32);
        _movzx(T, Src0RM);
      }
-      _and(T, One);
      _mov(Dest, T);
    } else {
      // t1 = movzx src; dst = t1

--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -841,12 +841,12 @@ entry:
 ; CHECK-LABEL: trunc64To1
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK:      and     eax,0x1
-; CHECK:      and     eax,0x1
+; CHECK-NOT:  and     eax,0x1
 ;
 ; OPTM1-LABEL: trunc64To1
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1:      and     eax,0x1
-; OPTM1:      and     eax,0x1
+; OPTM1-NOT:  and     eax,0x1

 ; ARM32-LABEL: trunc64To1
 ; ARM32: and r0, r0, #1

--- a/tests_lit/llvm2ice_tests/fp.convert.ll
+++ b/tests_lit/llvm2ice_tests/fp.convert.ll
@@ -256,7 +256,7 @@ entry:
 }
 ; CHECK-LABEL: doubleToUnsigned1
 ; CHECK: cvttsd2si
-; CHECK: and eax,0x1
+; CHECK-NOT: and eax,0x1
 ; ARM32-LABEL: doubleToUnsigned1
 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]]
@@ -272,7 +272,7 @@ entry:
 }
 ; CHECK-LABEL: floatToUnsigned1
 ; CHECK: cvttss2si
-; CHECK: and eax,0x1
+; CHECK-NOT: and eax,0x1
 ; ARM32-LABEL: floatToUnsigned1
 ; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]]

--- a/tests_lit/llvm2ice_tests/test_i1.ll
+++ b/tests_lit/llvm2ice_tests/test_i1.ll
@@ -87,7 +87,7 @@ entry:
 ; match the trunc instruction
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction (NOTE: no mov need between i1 and i8).
-; CHECK: and {{.*}},0x1
+; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextI8
 ; ARM32: and {{.*}}, #1
 ; ARM32: and {{.*}}, #1
@@ -105,7 +105,7 @@ entry:
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction (note 32-bit reg is used because it's shorter).
 ; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}}
-; CHECK: and [[REG]],0x1
+; CHECK-NOT: and [[REG]],0x1

 ; ARM32-LABEL: testZextI16
 ; match the trunc instruction
@@ -125,7 +125,7 @@ entry:
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction
 ; CHECK: movzx
-; CHECK: and {{.*}},0x1
+; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextI32
 ; ARM32: and {{.*}}, #1
 ; ARM32: and {{.*}}, #1
@@ -142,7 +142,6 @@ entry:
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction
 ; CHECK: movzx
-; CHECK: and {{.*}},0x1
 ; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: testZextI64
 ; ARM32: and {{.*}}, #1
@@ -257,7 +256,7 @@ define internal i32 @testZextTrue() {
 }
 ; CHECK-LABEL: testZextTrue
 ; CHECK: movzx
-; CHECK: and {{.*}},0x1
+; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextTrue
 ; ARM32: mov{{.*}}, #1
 ; ARM32: and {{.*}}, #1