Add recognizing register-shifted forms in ARM assembler.

src/IceAssemblerARM32.cpp

@@ -199,6 +199,9 @@ enum DecodedResult {
   // Value=000000000000000000000iiiii0000000 iiii defines the Imm5 value to
   // shift.
   DecodedAsShiftImm5,
+  // i.e. iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
+  // kind, and iiiii is the shift amount.
+  DecodedAsShiftedRegister,
   // Value is 32bit integer constant.
   DecodedAsConstI32
 };
@@ -228,6 +231,7 @@ IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
 }
 
 DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
+  Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
@@ -247,6 +251,18 @@ DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
     Value = Const->getValue();
     return DecodedAsConstI32;
   }
+  if (const auto *FlexReg = llvm::dyn_cast<OperandARM32FlexReg>(Opnd)) {
+    Operand *Amt = FlexReg->getShiftAmt();
+    if (const auto *Imm5 = llvm::dyn_cast<OperandARM32ShAmtImm>(Amt)) {
+      IValueT Rm;
+      if (decodeOperand(FlexReg->getReg(), Rm) != DecodedAsRegister)
+        return CantDecode;
+      Value =
+          encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5->getShAmtImm());
+      return DecodedAsShiftedRegister;
+    }
+    // TODO(kschimpf): Handle case where Amt is a register?
+  }
   if (const auto *ShImm = llvm::dyn_cast<OperandARM32ShAmtImm>(Opnd)) {
     const IValueT Immed5 = ShImm->getShAmtImm();
     assert(Immed5 < (1 << kShiftImmBits));
@@ -271,6 +287,7 @@ IValueT decodeImmRegOffset(RegARM32::GPRRegister Reg, IOffsetT Offset,
 // based on how ARM represents the address. Returns how the value was encoded.
 DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value,
                             const AssemblerARM32::TargetInfo &TInfo) {
+  Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
@@ -500,6 +517,12 @@ void AssemblerARM32::emitType01(IValueT Opcode, IValueT Rd, IValueT Rn,
                RuleChecks);
     return;
   }
+  case DecodedAsShiftedRegister: {
+    // Form is defined in case DecodedAsRegister. (i.e. XXX (register)).
+    emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value,
+               RuleChecks);
+    return;
+  }
   case DecodedAsConstI32: {
     // See if we can convert this to an XXX (immediate).
     IValueT RotateAmt;

tests_lit/assembler/arm32/cmp.ll

+; Test that we handle cmp (register) and cmp (immediate).
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+define internal i32 @cmpEqI8(i32 %a, i32 %b) {
+; ASM-LABEL:cmpEqI8:
+; DIS-LABEL:00000000 <cmpEqI8>:
+; IASM-LABEL:cmpEqI8:
+
+
+entry:
+; ASM-NEXT:.LcmpEqI8$entry:
+; IASM-NEXT:.LcmpEqI8$entry:
+
+  %b.arg_trunc = trunc i32 %b to i8
+  %a.arg_trunc = trunc i32 %a to i8
+
+; ASM-NEXT:     sub     sp, sp, #24
+; DIS-NEXT:   0:        e24dd018
+; IASM-NEXT:    .byte 0x18
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     str     r0, [sp, #20]
+; ASM-NEXT:     # [sp, #20] = def.pseudo 
+; DIS-NEXT:   4:        e58d0014
+; IASM-NEXT:    .byte 0x14
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x8d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     str     r1, [sp, #16]
+; ASM-NEXT:     # [sp, #16] = def.pseudo 
+; DIS-NEXT:   8:        e58d1010
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x8d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     ldr     r0, [sp, #16]
+; DIS-NEXT:   c:        e59d0010
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x9d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     strb    r0, [sp, #12]
+; ASM-NEXT:     # [sp, #12] = def.pseudo 
+; DIS-NEXT:  10:       e5cd000c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xcd
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     ldr     r0, [sp, #20]
+; DIS-NEXT:  14:        e59d0014
+; IASM-NEXT:    .byte 0x14
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x9d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     strb    r0, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:  18:        e5cd0008
+; IASM-NEXT:    .byte 0x8
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xcd
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     mov     r0, #0
+; DIS-NEXT:  1c:        e3a00000
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe3
+
+; ASM-NEXT:     ldrb    r1, [sp, #8]
+; DIS-NEXT:  20:        e5dd1008
+; IASM-NEXT:    .byte 0x8
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0xdd
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     lsl     r1, r1, #24
+; DIS-NEXT:  24:        e1a01c01
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0x1c
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe1
+
+; ASM-NEXT:     ldrb    r2, [sp, #12]
+; DIS-NEXT:  28:        e5dd200c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0x20
+; IASM-NEXT:    .byte 0xdd
+; IASM-NEXT:    .byte 0xe5
+
+; ******** CMP instruction test **************
+
+  %cmp = icmp eq i8 %a.arg_trunc, %b.arg_trunc
+
+; ASM-NEXT:        cmp     r1, r2, lsl #24
+; DIS-NEXT:  2c:        e1510c02
+; IASM-NEXT:    .byte 0x2
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0x51
+; IASM-NEXT:    .byte 0xe1
+
+  %cmp.ret_ext = zext i1 %cmp to i32
+  ret i32 %cmp.ret_ext
+}
+
+define internal i32 @cmpEqI32(i32 %a, i32 %b) {
+; ASM-LABEL:cmpEqI32:
+; DIS-LABEL:00000050 <cmpEqI32>:
+; IASM-LABEL:cmpEqI32:
+
+entry:
+; ASM-NEXT:.LcmpEqI32$entry:
+; IASM-NEXT:.LcmpEqI32$entry:
+
+; ASM-NEXT:     sub     sp, sp, #16
+; DIS-NEXT:  50:        e24dd010
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     str     r0, [sp, #12]
+; ASM-NEXT:     # [sp, #12] = def.pseudo 
+; DIS-NEXT:  54:        e58d000c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x8d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     str     r1, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:  58:        e58d1008
+; IASM-NEXT:    .byte 0x8
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x8d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     mov     r0, #0
+; DIS-NEXT:  5c:        e3a00000
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe3
+
+; ASM-NEXT:     ldr     r1, [sp, #12]
+; DIS-NEXT:  60:        e59d100c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x9d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     ldr     r2, [sp, #8]
+; DIS-NEXT:  64:        e59d2008
+; IASM-NEXT:    .byte 0x8
+; IASM-NEXT:    .byte 0x20
+; IASM-NEXT:    .byte 0x9d
+; IASM-NEXT:    .byte 0xe5
+
+; ******** CMP instruction test **************
+
+  %cmp = icmp eq i32 %a, %b
+
+; ASM-NEXT:     cmp     r1, r2
+; DIS-NEXT:  68:        e1510002
+; IASM-NEXT:    .byte 0x2
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x51
+; IASM-NEXT:    .byte 0xe1
+
+  %cmp.ret_ext = zext i1 %cmp to i32
+  ret i32 %cmp.ret_ext
+}