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swiftshader
Commit 4b6e4b44 by John Porto
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Subzero. ARM32. Refactors atomic intrinsics lowering.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1409863006 .
parent 816fd68f
Showing with 103 additions and 44 deletions
crosstest/test_sync_atomic.cpp
...@@ -47,7 +47,8 @@ ...@@ -47,7 +47,8 @@
if (fetch) { \ if (fetch) { \
return __sync_fetch_and_##inst(ptr, 42); \ return __sync_fetch_and_##inst(ptr, 42); \
} else { \ } else { \
return __sync_##inst##_and_fetch(ptr, 99); \ const type value = static_cast<type>(0xaaaaaaaaaaaaaaaaull); \
return __sync_##inst##_and_fetch(ptr, value); \
} \ } \
} }
......
pydir/build-runtime.py
...@@ -65,14 +65,27 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -65,14 +65,27 @@ def MakeRuntimesForTarget(target_info, ll_files,
'-target=' + target_info.triple, '-target=' + target_info.triple,
'-c', '-c',
'{srcdir}/szrt_profiler.c'.format(srcdir=srcdir), '{srcdir}/szrt_profiler.c'.format(srcdir=srcdir),
'-o', TmpFile('{dir}/szrt_profiler_native_{target}.o') '-o', TmpFile('{dir}/szrt_native_profiler_{target}.o')
], echo=verbose)
# Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
shellcmd(['llvm-mc',
'-triple=' + target_info.triple, '--defsym NATIVE=1',
'-filetype=obj',
'-o', TmpFile('{dir}/szrt_native_asm_{target}.o'),
'{srcdir}/szrt_asm_{target}.s'.format(
srcdir=srcdir, target=target_info.target)
], echo=verbose) ], echo=verbose)
# Write full szrt_native_{target}.o. # Write full szrt_native_{target}.o.
PartialLink([TmpFile('{dir}/szrt_native_{target}.tmp.o'), PartialLink([TmpFile('{dir}/szrt_native_{target}.tmp.o'),
TmpFile('{dir}/szrt_profiler_native_{target}.o')], TmpFile('{dir}/szrt_native_asm_{target}.o'),
TmpFile('{dir}/szrt_native_profiler_{target}.o')],
['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)], ['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)],
OutFile('{rtdir}/szrt_native_{target}.o'), OutFile('{rtdir}/szrt_native_{target}.o'),
verbose) verbose)
shellcmd(['le32-nacl-objcopy',
'--strip-symbol=NATIVE',
OutFile('{rtdir}/szrt_native_{target}.o')])
# Helper function for building the sandboxed runtime. # Helper function for building the sandboxed runtime.
def MakeSandboxedRuntime(): def MakeSandboxedRuntime():
"""Builds just the sandboxed runtime.""" """Builds just the sandboxed runtime."""
...@@ -82,8 +95,26 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -82,8 +95,26 @@ def MakeRuntimesForTarget(target_info, ll_files,
Translate(ll_files, Translate(ll_files,
['-mtriple=' + targets.ConvertTripleToNaCl(target_info.triple)] + ['-mtriple=' + targets.ConvertTripleToNaCl(target_info.triple)] +
target_info.llc_flags, target_info.llc_flags,
OutFile('{rtdir}/szrt_sb_{target}.o'), TmpFile('{dir}/szrt_sb_{target}.tmp.o'),
verbose) verbose)
# Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
shellcmd(['llvm-mc',
'-triple=' + targets.ConvertTripleToNaCl(target_info.triple),
'--defsym NACL=1',
'-filetype=obj',
'-o', TmpFile('{dir}/szrt_sb_asm_{target}.o'),
'{srcdir}/szrt_asm_{target}.s'.format(
srcdir=srcdir, target=target_info.target)
], echo=verbose)
PartialLink([TmpFile('{dir}/szrt_sb_{target}.tmp.o'),
TmpFile('{dir}/szrt_sb_asm_{target}.o')],
['-m {ld_emu}'.format(ld_emu=target_info.sb_emu)],
OutFile('{rtdir}/szrt_sb_{target}.o'),
verbose)
shellcmd(['le32-nacl-objcopy',
'--strip-symbol=NACL',
OutFile('{rtdir}/szrt_sb_{target}.o')])
# Helper function for building the Non-SFI runtime. # Helper function for building the Non-SFI runtime.
def MakeNonsfiRuntime(): def MakeNonsfiRuntime():
"""Builds just the nonsfi runtime.""" """Builds just the nonsfi runtime."""
...@@ -96,18 +127,22 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -96,18 +127,22 @@ def MakeRuntimesForTarget(target_info, ll_files,
verbose) verbose)
# Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o. # Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
shellcmd(['llvm-mc', shellcmd(['llvm-mc',
'-triple=' + target_info.triple, '-triple=' + target_info.triple, '--defsym NONSFI=1',
'-filetype=obj', '-filetype=obj',
'-o', TmpFile('{dir}/szrt_asm_{target}.o'), '-o', TmpFile('{dir}/szrt_nonsfi_asm_{target}.o'),
'{srcdir}/szrt_asm_{target}.s'.format( '{srcdir}/szrt_asm_{target}.s'.format(
srcdir=srcdir, target=target_info.target) srcdir=srcdir, target=target_info.target)
], echo=verbose) ], echo=verbose)
# Write full szrt_nonsfi_{target}.o. # Write full szrt_nonsfi_{target}.o.
PartialLink([TmpFile('{dir}/szrt_nonsfi_{target}.tmp.o'), PartialLink([TmpFile('{dir}/szrt_nonsfi_{target}.tmp.o'),
TmpFile('{dir}/szrt_asm_{target}.o')], TmpFile('{dir}/szrt_nonsfi_asm_{target}.o')],
['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)], ['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)],
OutFile('{rtdir}/szrt_nonsfi_{target}.o'), OutFile('{rtdir}/szrt_nonsfi_{target}.o'),
verbose) verbose)
shellcmd(['le32-nacl-objcopy',
'--strip-symbol=NONSFI',
OutFile('{rtdir}/szrt_nonsfi_{target}.o')])
# Run the helper functions. # Run the helper functions.
MakeNativeRuntime() MakeNativeRuntime()
......
pydir/targets.py
...@@ -18,13 +18,14 @@ def FindARMCrossInclude(): ...@@ -18,13 +18,14 @@ def FindARMCrossInclude():
TargetInfo = namedtuple('TargetInfo', TargetInfo = namedtuple('TargetInfo',
['target', 'compiler_arch', 'triple', 'llc_flags', ['target', 'compiler_arch', 'triple', 'llc_flags',
'ld_emu', 'cross_headers']) 'ld_emu', 'sb_emu', 'cross_headers'])
X8632Target = TargetInfo(target='x8632', X8632Target = TargetInfo(target='x8632',
compiler_arch='x8632', compiler_arch='x8632',
triple='i686-none-linux', triple='i686-none-linux',
llc_flags=['-mcpu=pentium4m'], llc_flags=['-mcpu=pentium4m'],
ld_emu='elf_i386_nacl', ld_emu='elf_i386_nacl',
sb_emu='elf_i386_nacl',
cross_headers=[]) cross_headers=[])
X8664Target = TargetInfo(target='x8664', X8664Target = TargetInfo(target='x8664',
...@@ -32,6 +33,7 @@ X8664Target = TargetInfo(target='x8664', ...@@ -32,6 +33,7 @@ X8664Target = TargetInfo(target='x8664',
triple='x86_64-none-linux-gnux32', triple='x86_64-none-linux-gnux32',
llc_flags=['-mcpu=x86-64'], llc_flags=['-mcpu=x86-64'],
ld_emu='elf32_x86_64_nacl', ld_emu='elf32_x86_64_nacl',
sb_emu='elf_x86_64_nacl',
cross_headers=[]) cross_headers=[])
ARM32Target = TargetInfo(target='arm32', ARM32Target = TargetInfo(target='arm32',
...@@ -41,6 +43,7 @@ ARM32Target = TargetInfo(target='arm32', ...@@ -41,6 +43,7 @@ ARM32Target = TargetInfo(target='arm32',
'-float-abi=hard', '-float-abi=hard',
'-mattr=+neon'], '-mattr=+neon'],
ld_emu='armelf_nacl', ld_emu='armelf_nacl',
sb_emu='armelf_nacl',
cross_headers=['-isystem', FindARMCrossInclude()]) cross_headers=['-isystem', FindARMCrossInclude()])
def ConvertTripleToNaCl(nonsfi_triple): def ConvertTripleToNaCl(nonsfi_triple):
......
runtime/szrt_asm_arm32.s
...@@ -14,6 +14,3 @@ ...@@ -14,6 +14,3 @@
.text .text
.p2alignl 4,0xE7FEDEF0 .p2alignl 4,0xE7FEDEF0
.globl __nacl_read_tp
__nacl_read_tp:
b __aeabi_read_tp
runtime/szrt_asm_x8632.s
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
.text .text
.p2align 5,0xf4 .p2align 5,0xf4
.ifdef NONSFI
.globl __Sz_getIP_eax .globl __Sz_getIP_eax
__Sz_getIP_eax: __Sz_getIP_eax:
movl (%esp), %eax movl (%esp), %eax
...@@ -49,3 +50,4 @@ __Sz_getIP_esi: ...@@ -49,3 +50,4 @@ __Sz_getIP_esi:
__Sz_getIP_edi: __Sz_getIP_edi:
movl (%esp), %edi movl (%esp), %edi
ret ret
.endif # NONSFI
src/IceRegAlloc.cpp
...@@ -642,7 +642,7 @@ void LinearScan::allocateFreeRegister(IterationState &Iter, bool Filtered) { ...@@ -642,7 +642,7 @@ void LinearScan::allocateFreeRegister(IterationState &Iter, bool Filtered) {
*RegNumBVIter(Filtered ? Iter.Free : Iter.FreeUnfiltered).begin(); *RegNumBVIter(Filtered ? Iter.Free : Iter.FreeUnfiltered).begin();
Iter.Cur->setRegNumTmp(RegNum); Iter.Cur->setRegNumTmp(RegNum);
if (Filtered) if (Filtered)
dumpLiveRangeTrace("Allocating ", Iter.Cur); dumpLiveRangeTrace("Allocating Y ", Iter.Cur);
else else
dumpLiveRangeTrace("Allocating X ", Iter.Cur); dumpLiveRangeTrace("Allocating X ", Iter.Cur);
const llvm::SmallBitVector &Aliases = *RegAliases[RegNum]; const llvm::SmallBitVector &Aliases = *RegAliases[RegNum];
...@@ -768,7 +768,7 @@ void LinearScan::handleNoFreeRegisters(IterationState &Iter) { ...@@ -768,7 +768,7 @@ void LinearScan::handleNoFreeRegisters(IterationState &Iter) {
++RegUses[RegAlias]; ++RegUses[RegAlias];
} }
Active.push_back(Iter.Cur); Active.push_back(Iter.Cur);
dumpLiveRangeTrace("Allocating ", Iter.Cur); dumpLiveRangeTrace("Allocating Z ", Iter.Cur);
} }
void LinearScan::assignFinalRegisters( void LinearScan::assignFinalRegisters(
......
src/IceTargetLoweringARM32.h
...@@ -246,8 +246,29 @@ protected: ...@@ -246,8 +246,29 @@ protected:
Operand *Src1); Operand *Src1);
CondWhenTrue lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0, CondWhenTrue lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
Operand *Src1); Operand *Src1);
CondWhenTrue lowerIcmpCond(InstIcmp::ICond Condition, Operand *Src0,
Operand *Src1);
CondWhenTrue lowerIcmpCond(const InstIcmp *Instr); CondWhenTrue lowerIcmpCond(const InstIcmp *Instr);
void lowerIcmp(const InstIcmp *Instr) override; void lowerIcmp(const InstIcmp *Instr) override;
/// Emits the basic sequence for lower-linked/store-exclusive loops:
///
/// retry:
/// ldrex tmp, [Addr]
/// StoreValue = Operation(tmp)
/// strexCond success, StoreValue, [Addr]
/// cmpCond success, #0
/// bne retry
///
/// Operation needs to return which value to strex in Addr, it must not change
/// the flags if Cond is not AL, and must not emit any instructions that could
/// end up writing to memory. Operation also needs to handle fake-defing for
/// i64 handling.
void
lowerLoadLinkedStoreExclusive(Type Ty, Operand *Addr,
std::function<Variable *(Variable *)> Operation,
CondARM32::Cond Cond = CondARM32::AL);
void lowerInt64AtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
Operand *Val);
void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr, void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
Operand *Val); Operand *Val);
void lowerIntrinsicCall(const InstIntrinsicCall *Instr) override; void lowerIntrinsicCall(const InstIntrinsicCall *Instr) override;
...@@ -360,13 +381,14 @@ protected: ...@@ -360,13 +381,14 @@ protected:
CondARM32::Cond Pred = CondARM32::AL) { CondARM32::Cond Pred = CondARM32::AL) {
Context.insert<InstARM32Ldr>(Dest, Addr, Pred); Context.insert<InstARM32Ldr>(Dest, Addr, Pred);
} }
void _ldrex(Variable *Dest, OperandARM32Mem *Addr, InstARM32Ldrex *_ldrex(Variable *Dest, OperandARM32Mem *Addr,
CondARM32::Cond Pred = CondARM32::AL) { CondARM32::Cond Pred = CondARM32::AL) {
Context.insert<InstARM32Ldrex>(Dest, Addr, Pred); auto *Ldrex = Context.insert<InstARM32Ldrex>(Dest, Addr, Pred);
if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) { if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) {
Context.insert<InstFakeDef>(Dest64->getLo(), Dest); Context.insert<InstFakeDef>(Dest64->getLo(), Dest);
Context.insert<InstFakeDef>(Dest64->getHi(), Dest); Context.insert<InstFakeDef>(Dest64->getHi(), Dest);
} }
return Ldrex;
} }
void _lsl(Variable *Dest, Variable *Src0, Operand *Src1, void _lsl(Variable *Dest, Variable *Src0, Operand *Src1,
CondARM32::Cond Pred = CondARM32::AL) { CondARM32::Cond Pred = CondARM32::AL) {
......
tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
...@@ -246,10 +246,10 @@ entry: ...@@ -246,10 +246,10 @@ entry:
; CHECK: movq QWORD {{.*}},x{{.*}} ; CHECK: movq QWORD {{.*}},x{{.*}}
; CHECK: mfence ; CHECK: mfence
; ARM32-LABEL: test_atomic_store_64_const ; ARM32-LABEL: test_atomic_store_64_const
; ARM32: dmb
; ARM32: movw [[T0:r[0-9]+]], #12274 ; ARM32: movw [[T0:r[0-9]+]], #12274
; ARM32: movt [[T0]], #29646 ; ARM32: movt [[T0]], #29646
; ARM32: movw r{{[0-9]+}}, #2874 ; ARM32: movw r{{[0-9]+}}, #2874
; ARM32: dmb
; ARM32: .L[[RETRY:.*]]: ; ARM32: .L[[RETRY:.*]]:
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]]
; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]] ; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]]
...@@ -342,7 +342,7 @@ entry: ...@@ -342,7 +342,7 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: adds ; ARM32: adds
; ARM32-NEXT: adc ; ARM32: adc
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -359,7 +359,7 @@ entry: ...@@ -359,7 +359,7 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: adds ; ARM32: adds
; ARM32-NEXT: adc ; ARM32: adc
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -400,7 +400,7 @@ eblock: ...@@ -400,7 +400,7 @@ eblock:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: adds ; ARM32: adds
; ARM32-NEXT: adc ; ARM32: adc
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -457,7 +457,7 @@ err: ...@@ -457,7 +457,7 @@ err:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: adds ; ARM32: adds
; ARM32-NEXT: adc ; ARM32: adc
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -543,7 +543,7 @@ entry: ...@@ -543,7 +543,7 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: subs ; ARM32: subs
; ARM32-NEXT: sbc ; ARM32: sbc
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -602,9 +602,9 @@ entry: ...@@ -602,9 +602,9 @@ entry:
} }
; CHECK-LABEL: test_atomic_rmw_or_8_global ; CHECK-LABEL: test_atomic_rmw_or_8_global
; ARM32-LABEL: test_atomic_rmw_or_8_global ; ARM32-LABEL: test_atomic_rmw_or_8_global
; ARM32: dmb
; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal8 ; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal8
; ARM32: movt [[PTR]], #:upper16:SzGlobal8 ; ARM32: movt [[PTR]], #:upper16:SzGlobal8
; ARM32: dmb
; ARM32: ldrexb r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: ldrexb r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: orr ; ARM32: orr
; ARM32: strexb ; ARM32: strexb
...@@ -643,9 +643,9 @@ entry: ...@@ -643,9 +643,9 @@ entry:
} }
; CHECK-LABEL: test_atomic_rmw_or_16_global ; CHECK-LABEL: test_atomic_rmw_or_16_global
; ARM32-LABEL: test_atomic_rmw_or_16_global ; ARM32-LABEL: test_atomic_rmw_or_16_global
; ARM32: dmb
; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal16 ; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal16
; ARM32: movt [[PTR]], #:upper16:SzGlobal16 ; ARM32: movt [[PTR]], #:upper16:SzGlobal16
; ARM32: dmb
; ARM32: ldrexh r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: ldrexh r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: orr ; ARM32: orr
; ARM32: strexh ; ARM32: strexh
...@@ -680,9 +680,9 @@ entry: ...@@ -680,9 +680,9 @@ entry:
} }
; CHECK-LABEL: test_atomic_rmw_or_32_global ; CHECK-LABEL: test_atomic_rmw_or_32_global
; ARM32-LABEL: test_atomic_rmw_or_32_global ; ARM32-LABEL: test_atomic_rmw_or_32_global
; ARM32: dmb
; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal32 ; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal32
; ARM32: movt [[PTR]], #:upper16:SzGlobal32 ; ARM32: movt [[PTR]], #:upper16:SzGlobal32
; ARM32: dmb
; ARM32: ldrex r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: ldrex r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: orr ; ARM32: orr
; ARM32: strex ; ARM32: strex
...@@ -709,7 +709,7 @@ entry: ...@@ -709,7 +709,7 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: orr ; ARM32: orr
; ARM32-NEXT: orr ; ARM32: orr
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -819,7 +819,7 @@ entry: ...@@ -819,7 +819,7 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: and ; ARM32: and
; ARM32-NEXT: and ; ARM32: and
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -927,7 +927,7 @@ entry: ...@@ -927,7 +927,7 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: eor ; ARM32: eor
; ARM32-NEXT: eor ; ARM32: eor
; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}] ; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1067,8 +1067,8 @@ entry: ...@@ -1067,8 +1067,8 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexb ; ARM32: ldrexb
; ARM32: cmp ; ARM32: cmp
; ARM32: {{strb|mov}}
; ARM32: strexbeq ; ARM32: strexbeq
; ARM32: {{strb|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1091,8 +1091,8 @@ entry: ...@@ -1091,8 +1091,8 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexh ; ARM32: ldrexh
; ARM32: cmp ; ARM32: cmp
; ARM32: {{strh|mov}}
; ARM32: strexheq ; ARM32: strexheq
; ARM32: {{strh|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1112,8 +1112,8 @@ entry: ...@@ -1112,8 +1112,8 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrex ; ARM32: ldrex
; ARM32: cmp ; ARM32: cmp
; ARM32: {{str|mov}}
; ARM32: strexeq ; ARM32: strexeq
; ARM32: {{str|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1140,10 +1140,10 @@ entry: ...@@ -1140,10 +1140,10 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}} ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
; ARM32: cmp ; ARM32: cmp
; ARM32-NEXT: cmpeq ; ARM32: cmpeq
; ARM32: mov
; ARM32: mov
; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: {{str|mov}}ne
; ARM32: {{str|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1163,10 +1163,10 @@ entry: ...@@ -1163,10 +1163,10 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}} ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
; ARM32: cmp ; ARM32: cmp
; ARM32-NEXT: cmpeq ; ARM32: cmpeq
; ARM32: mov
; ARM32: mov
; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: {{str|mov}}ne
; ARM32: {{str|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1195,10 +1195,10 @@ entry: ...@@ -1195,10 +1195,10 @@ entry:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}} ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
; ARM32: cmp ; ARM32: cmp
; ARM32-NEXT: cmpeq ; ARM32: cmpeq
; ARM32: mov
; ARM32: mov
; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: {{str|mov}}ne
; ARM32: {{str|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1241,10 +1241,10 @@ eblock: ...@@ -1241,10 +1241,10 @@ eblock:
; ARM32: dmb ; ARM32: dmb
; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}} ; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
; ARM32: cmp ; ARM32: cmp
; ARM32-NEXT: cmpeq ; ARM32: cmpeq
; ARM32: mov
; ARM32: mov
; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}} ; ARM32: strexdeq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
; ARM32: {{str|mov}}ne
; ARM32: {{str|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
...@@ -1265,7 +1265,6 @@ entry: ...@@ -1265,7 +1265,6 @@ entry:
; ARM32: ldrex ; ARM32: ldrex
; ARM32: cmp ; ARM32: cmp
; ARM32: strexeq ; ARM32: strexeq
; ARM32: {{str|mov}}ne
; ARM32: cmpeq ; ARM32: cmpeq
; ARM32: bne ; ARM32: bne
; ARM32: dmb ; ARM32: dmb
......
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