Add CMN instruction to ARM integrated assembler.

src/DartARM32/assembler_arm.cc

@@ -269,14 +269,12 @@ void Assembler::teq(Register rn, Operand o, Condition cond) {
 void Assembler::cmp(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
 }
-#endif
-
 
+// Moved to ARM32::AssemblerARM32::cmn()
 void Assembler::cmn(Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), CMN, 1, rn, R0, o);
 }
 
-#if 0
 // Moved to ARM32::AssemberARM32::orr()
 void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), ORR, 0, rn, rd, o);

src/DartARM32/assembler_arm.h

@@ -491,11 +491,10 @@ class Assembler : public ValueObject {
 #if 0
   // Moved to ARM32::AssemblerARM32::cmp()
   void cmp(Register rn, Operand o, Condition cond = AL);
-#endif
 
+  // Moved to ARM32::AssemblerARM32::cmn()
   void cmn(Register rn, Operand o, Condition cond = AL);
 
-#if 0
   // Moved to ARM32::IceAssemblerARM32::orr().
   void orr(Register rd, Register rn, Operand o, Condition cond = AL);
   void orrs(Register rd, Register rn, Operand o, Condition cond = AL);

src/IceAssemblerARM32.cpp

@@ -1041,6 +1041,24 @@ void AssemblerARM32::bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond) {
   emitInst(Encoding);
 }
 
+void AssemblerARM32::cmn(const Operand *OpRn, const Operand *OpSrc1,
+                         CondARM32::Cond Cond) {
+  // CMN (immediate) - ARM section A8.8.34, encoding A1:
+  //   cmn<c> <Rn>, #<RotatedImm8>
+  //
+  // cccc00110111nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+  //
+  // CMN (register) - ARM section A8.8.35, encodeing A1:
+  //   cmn<c> <Rn>, <Rm>{, <shift>}
+  //
+  // cccc00010111nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm,
+  // iiiii=Shift, and tt=ShiftKind.
+  constexpr const char *CmnName = "cmn";
+  constexpr IValueT CmnOpcode = B3 | B1 | B0; // ie. 1011
+  emitCompareOp(Cond, CmnOpcode, OpRn, OpSrc1, CmnName);
+}
+
 void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1,
                          CondARM32::Cond Cond) {
   // CMP (register) - ARM section A8.8.38, encoding A1:

src/IceAssemblerARM32.h

@@ -208,6 +208,8 @@ public:
 
   void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
 
+  void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
+
   void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,

src/IceInstARM32.cpp

@@ -653,6 +653,14 @@ void InstARM32CmpLike<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32Cmn::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 2);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  Asm->cmn(getSrc(0), getSrc(1), getPredicate());
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Cmp::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();

tests_lit/assembler/arm32/cmn.ll

+; Show that we know how to encode CMN in the ARM integrated assembler.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+define internal i32 @testCmn(i32 %a) {
+; ASM-LABEL:testCmn:
+; DIS-LABEL:00000000 <testCmn>:
+; IASM-LABEL:testCmn:
+
+entry:
+; ASM-NEXT:.LtestCmn$entry:
+; IASM-NEXT:.LtestCmn$entry:
+
+; ASM-NEXT:     sub     sp, sp, #12
+; DIS-NEXT:   0:        e24dd00c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     str     r0, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:   4:        e58d0008
+; IASM-NEXT:    .byte 0x8
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x8d
+; IASM-NEXT:    .byte 0xe5
+
+  %cmp = icmp sgt i32 %a, -1
+
+; ASM-NEXT:     mov     r0, #0
+; DIS-NEXT:   8:        e3a00000
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe3
+
+; ASM-NEXT:     ldr     r1, [sp, #8]
+; DIS-NEXT:   c:        e59d1008
+; IASM-NEXT:    .byte 0x8
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0x9d
+; IASM-NEXT:    .byte 0xe5
+
+; ASM-NEXT:     cmn     r1, #1
+; DIS-NEXT:  10:        e3710001
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x71
+; IASM-NEXT:    .byte 0xe3
+
+  %cmp.ret_ext = zext i1 %cmp to i32
+  ret i32 %cmp.ret_ext
+}