Commit 515e8c22 by Karl Schimpf

Fix nits from previous CLs.

parent 33436473
...@@ -367,17 +367,18 @@ size_t BlRelocatableFixup::emit(GlobalContext *Ctx, ...@@ -367,17 +367,18 @@ size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
return InstARM32::InstSize; return InstARM32::InstSize;
Ostream &Str = Ctx->getStrEmit(); Ostream &Str = Ctx->getStrEmit();
IValueT Inst = Asm.load<IValueT>(position()); IValueT Inst = Asm.load<IValueT>(position());
Str << "\tbl\t" << symbol(Ctx) << "\t@ .word " Str << "\t"
<< "bl\t" << symbol(Ctx) << "\t@ .word "
<< llvm::format_hex_no_prefix(Inst, 8) << "\n"; << llvm::format_hex_no_prefix(Inst, 8) << "\n";
return InstARM32::InstSize; return InstARM32::InstSize;
} }
BlRelocatableFixup * BlRelocatableFixup *
AssemblerARM32::createBlFixup(const ConstantRelocatable *Target) { AssemblerARM32::createBlFixup(const ConstantRelocatable *BlTarget) {
BlRelocatableFixup *F = BlRelocatableFixup *F =
new (allocate<BlRelocatableFixup>()) BlRelocatableFixup(); new (allocate<BlRelocatableFixup>()) BlRelocatableFixup();
F->set_kind(llvm::ELF::R_ARM_CALL); F->set_kind(llvm::ELF::R_ARM_CALL);
F->set_value(Target); F->set_value(BlTarget);
Buffer.installFixup(F); Buffer.installFixup(F);
return F; return F;
} }
...@@ -464,7 +465,7 @@ void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Type, ...@@ -464,7 +465,7 @@ void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Type,
case NoChecks: case NoChecks:
break; break;
case RdIsPcAndSetFlags: case RdIsPcAndSetFlags:
if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags)) if ((Rd == RegARM32::Encoded_Reg_pc) && SetFlags)
// Conditions of rule violated. // Conditions of rule violated.
return setNeedsTextFixup(); return setNeedsTextFixup();
break; break;
...@@ -778,8 +779,8 @@ void AssemblerARM32::blx(const Operand *Target) { ...@@ -778,8 +779,8 @@ void AssemblerARM32::blx(const Operand *Target) {
return setNeedsTextFixup(); return setNeedsTextFixup();
AssemblerBuffer::EnsureCapacity ensured(&Buffer); AssemblerBuffer::EnsureCapacity ensured(&Buffer);
constexpr CondARM32::Cond Cond = CondARM32::AL; constexpr CondARM32::Cond Cond = CondARM32::AL;
int32_t Encoding = (static_cast<int32_t>(Cond) << kConditionShift) | B24 | int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 |
B21 | (0xfff << 8) | B5 | B4 | (Rm << kRmShift); (0xfff << 8) | B5 | B4 | (Rm << kRmShift);
emitInst(Encoding); emitInst(Encoding);
} }
......
...@@ -109,7 +109,7 @@ public: ...@@ -109,7 +109,7 @@ public:
MoveRelocatableFixup *createMoveFixup(bool IsMovW, const Constant *Value); MoveRelocatableFixup *createMoveFixup(bool IsMovW, const Constant *Value);
BlRelocatableFixup *createBlFixup(const ConstantRelocatable *Target); BlRelocatableFixup *createBlFixup(const ConstantRelocatable *BlTarget);
void alignFunction() override { void alignFunction() override {
const SizeT Align = 1 << getBundleAlignLog2Bytes(); const SizeT Align = 1 << getBundleAlignLog2Bytes();
......
; Show that we know how to translate add. ; Show that we know how to translate blx.
; NOTE: We use -O2 to get rid of memory stores. ; NOTE: We use -O2 to get rid of memory stores.
......
...@@ -20,60 +20,40 @@ ...@@ -20,60 +20,40 @@
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS ; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
define internal i32 @_Z8testUdivhh(i32 %a, i32 %b) { define internal i32 @ShlAmt(i32 %a) {
; ASM-LABEL:ShlAmt:
; ASM-LABEL:_Z8testUdivhh: ; DIS-LABEL:00000000 <ShlAmt>:
; DIS-LABEL:00000000 <_Z8testUdivhh>: ; IASM-LABEL:ShlAmt:
; IASM-LABEL:_Z8testUdivhh:
entry: entry:
; ASM-NEXT:.LShlAmt$entry:
; IASM-NEXT:.LShlAmt$entry:
; ASM-NEXT:.L_Z8testUdivhh$entry: %shl = shl i32 %a, 23
; ASM-NEXT: push {lr}
; DIS-NEXT: 0: e52de004 ; ASM-NEXT: lsl r0, r0, #23
; IASM-NEXT:.L_Z8testUdivhh$entry: ; DIS-NEXT: 0: e1a00b80
; IASM-NEXT: .byte 0x4 ; IASM-NEXT: .byte 0x80
; IASM-NEXT: .byte 0xe0 ; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0x2d ; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xe5
%b.arg_trunc = trunc i32 %b to i8
%a.arg_trunc = trunc i32 %a to i8
%div3 = udiv i8 %a.arg_trunc, %b.arg_trunc
; ASM-NEXT: sub sp, sp, #12
; DIS-NEXT: 4: e24dd00c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0xd0
; IASM-NEXT: .byte 0x4d
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: lsls r2, r1, #24
; DIS-NEXT: 8: e1b02c01
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x2c
; IASM-NEXT: .byte 0xb0
; IASM-NEXT: .byte 0xe1 ; IASM-NEXT: .byte 0xe1
%div3.ret_ext = zext i8 %div3 to i32 ret i32 %shl
ret i32 %div3.ret_ext
} }
define internal i32 @_Z7testShljj(i32 %a, i32 %b) { define internal i32 @ShlReg(i32 %a, i32 %b) {
; ASM-LABEL:ShlReg:
; ASM-LABEL:_Z7testShljj: ; DIS-LABEL:00000010 <ShlReg>:
; DIS-LABEL:00000030 <_Z7testShljj>: ; IASM-LABEL:ShlReg:
; IASM-LABEL:_Z7testShljj:
entry: entry:
; ASM-NEXT:.LShlReg$entry:
; ASM-NEXT:.L_Z7testShljj$entry: ; IASM-NEXT:.LShlReg$entry:
; IASM-NEXT:.L_Z7testShljj$entry:
%shl = shl i32 %a, %b %shl = shl i32 %a, %b
; ASM-NEXT: lsl r0, r0, r1 ; ASM-NEXT: lsl r0, r0, r1
; DIS-NEXT: 30: e1a00110 ; DIS-NEXT: 10: e1a00110
; IASM-NEXT: .byte 0x10 ; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x1 ; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0xa0 ; IASM-NEXT: .byte 0xa0
......
...@@ -18,14 +18,14 @@ ...@@ -18,14 +18,14 @@
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS ; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
define internal void @mvmEx(i32 %a, i32 %b) { define internal void @mvnEx(i32 %a, i32 %b) {
; ASM-LABEL:mvmEx: ; ASM-LABEL:mvnEx:
; DIS-LABEL:00000000 <mvmEx>: ; DIS-LABEL:00000000 <mvnEx>:
; IASM-LABEL:mvmEx: ; IASM-LABEL:mvnEx:
entry: entry:
; ASM-NEXT:.LmvmEx$entry: ; ASM-NEXT:.LmvnEx$entry:
; IASM-NEXT:.LmvmEx$entry: ; IASM-NEXT:.LmvnEx$entry:
; ASM-NEXT: sub sp, sp, #24 ; ASM-NEXT: sub sp, sp, #24
; DIS-NEXT: 0: e24dd018 ; DIS-NEXT: 0: e24dd018
......
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