Subzero: Separate "\t" from "opcode" in asm emission.

src/IceAssemblerARM32.cpp

@@ -453,7 +453,8 @@ size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
-  Str << "\tmov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
+  Str << "\t"
+         "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
       << RegARM32::RegNames[(Inst >> kRdShift) & 0xF]
       << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
       << "16:" << symbol(Ctx) << "\t@ .word "
@@ -479,7 +480,7 @@ size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
-      << "bl\t" << symbol(Ctx) << "\t@ .word "
+         "bl\t" << symbol(Ctx) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }

src/IceInst.cpp

@@ -854,7 +854,8 @@ void InstBundleLock::emit(const Cfg *Func) const {
   case Opt_None:
     break;
   case Opt_AlignToEnd:
-    Str << "\talign_to_end";
+    Str << "\t"
+           "align_to_end";
     break;
   }
   Str << "\n";

src/IceInstARM32.cpp

@@ -818,7 +818,7 @@ void InstARM32Mov::emitMultiDestSingleSource(const Cfg *Func) const {
   assert(llvm::isa<Variable>(Src) && Src->hasReg());
 
   Str << "\t"
-      << "vmov" << getPredicate() << "\t";
+         "vmov" << getPredicate() << "\t";
   DestLo->emit(Func);
   Str << ", ";
   DestHi->emit(Func);
@@ -840,7 +840,7 @@ void InstARM32Mov::emitSingleDestMultiSource(const Cfg *Func) const {
   assert(getSrcSize() == 2);
 
   Str << "\t"
-      << "vmov" << getPredicate() << "\t";
+         "vmov" << getPredicate() << "\t";
   Dest->emit(Func);
   Str << ", ";
   SrcLo->emit(Func);
@@ -981,7 +981,7 @@ void InstARM32Br::emit(const Cfg *Func) const {
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
-      << "b" << getPredicate() << "\t";
+         "b" << getPredicate() << "\t";
   if (Label) {
     Str << Label->getName(Func);
   } else {
@@ -1052,13 +1052,13 @@ void InstARM32Call::emit(const Cfg *Func) const {
     // Calls only have 24-bits, but the linker should insert veneers to extend
     // the range if needed.
     Str << "\t"
-        << "bl"
-        << "\t";
+           "bl"
+           "\t";
     CallTarget->emitWithoutPrefix(Func->getTarget());
   } else {
     Str << "\t"
-        << "blx"
-        << "\t";
+           "blx"
+           "\t";
     getCallTarget()->emit(Func);
   }
 }
@@ -1496,8 +1496,8 @@ void InstARM32Ret::emit(const Cfg *Func) const {
   assert(LR->getRegNum() == RegARM32::Reg_lr);
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
-      << "bx"
-      << "\t";
+         "bx"
+         "\t";
   LR->emit(Func);
 }
 
@@ -1625,7 +1625,7 @@ void InstARM32Umull::emit(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   assert(getDest()->hasReg());
   Str << "\t"
-      << "umull" << getPredicate() << "\t";
+         "umull" << getPredicate() << "\t";
   getDest()->emit(Func);
   Str << ", ";
   DestHi->emit(Func);
@@ -1689,7 +1689,7 @@ void InstARM32Vcvt::emit(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
   Str << "\t"
-      << "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << "\t";
+         "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
@@ -1790,7 +1790,8 @@ void InstARM32Dmb::emitIAS(const Cfg *Func) const {
 void InstARM32Dmb::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  Func->getContext()->getStrDump() << "dmb\tsy";
+  Func->getContext()->getStrDump() << "dmb\t"
+                                      "sy";
 }
 
 void OperandARM32Mem::emit(const Cfg *Func) const {

src/IceInstMIPS32.cpp

@@ -139,8 +139,8 @@ void InstMIPS32Ret::emit(const Cfg *Func) const {
   assert(RA->getRegNum() == RegMIPS32::Reg_RA);
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\t"
-      << "jr"
-      << "\t";
+         "jr"
+         "\t";
   RA->emit(Func);
 }
 
@@ -258,8 +258,8 @@ void InstMIPS32Mov::emitSingleDestSingleSource(const Cfg *Func) const {
       Str << "lw";
   } else {
     if (S && S->hasReg()) {
-      Str << "sw";
-      Str << "\t";
+      Str << "sw"
+             "\t";
       getSrc(0)->emit(Func);
       Str << ", ";
       getDest()->emit(Func);

src/IceTargetLoweringMIPS32.cpp

@@ -1072,8 +1072,10 @@ TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx)
 void TargetHeaderMIPS32::lower() {
   OstreamLocker L(Ctx);
   Ostream &Str = Ctx->getStrEmit();
-  Str << "\t.set\tnomicromips\n";
-  Str << "\t.set\tnomips16\n";
+  Str << "\t.set\t"
+      << "nomicromips\n";
+  Str << "\t.set\t"
+      << "nomips16\n";
 }
 
 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];