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Commit 61593fb9 by Nicolas Capens Committed by Nicolas Capens
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Fix unit tests.

Change-Id: I70899be0455958aaad6af8d8218f1db50591beae Reviewed-on: https://chromium-review.googlesource.com/401385Tested-by: 's avatarNicolas Capens <nicolascapens@google.com> Reviewed-by: 's avatarJim Stichnoth <stichnot@chromium.org>
parent c9e91afc
Showing with 21 additions and 22 deletions
src/IceAssemblerX86BaseImpl.h
...@@ -1667,15 +1667,15 @@ void AssemblerX86Base<TraitsType>::punpckh(Type Ty, XmmRegister Dst, ...@@ -1667,15 +1667,15 @@ void AssemblerX86Base<TraitsType>::punpckh(Type Ty, XmmRegister Dst,
} }
template <typename TraitsType> template <typename TraitsType>
void AssemblerX86Base<TraitsType>::packss(Type DestTy, XmmRegister Dst, void AssemblerX86Base<TraitsType>::packss(Type Ty, XmmRegister Dst,
XmmRegister Src) { XmmRegister Src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer); AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66); emitUint8(0x66);
emitRexRB(RexTypeIrrelevant, Dst, Src); emitRexRB(RexTypeIrrelevant, Dst, Src);
emitUint8(0x0F); emitUint8(0x0F);
if (DestTy == IceType_v8i16) { if (Ty == IceType_v4i32 || Ty == IceType_v4f32) {
emitUint8(0x6B); emitUint8(0x6B);
} else if (DestTy == IceType_v16i8) { } else if (Ty == IceType_v8i16) {
emitUint8(0x63); emitUint8(0x63);
} else { } else {
assert(false && "Unexpected vector pack operand type"); assert(false && "Unexpected vector pack operand type");
...@@ -1684,16 +1684,16 @@ void AssemblerX86Base<TraitsType>::packss(Type DestTy, XmmRegister Dst, ...@@ -1684,16 +1684,16 @@ void AssemblerX86Base<TraitsType>::packss(Type DestTy, XmmRegister Dst,
} }
template <typename TraitsType> template <typename TraitsType>
void AssemblerX86Base<TraitsType>::packss(Type DestTy, XmmRegister Dst, void AssemblerX86Base<TraitsType>::packss(Type Ty, XmmRegister Dst,
const Address &Src) { const Address &Src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer); AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66); emitUint8(0x66);
emitAddrSizeOverridePrefix(); emitAddrSizeOverridePrefix();
emitRex(RexTypeIrrelevant, Src, Dst); emitRex(RexTypeIrrelevant, Src, Dst);
emitUint8(0x0F); emitUint8(0x0F);
if (DestTy == IceType_v8i16) { if (Ty == IceType_v4i32 || Ty == IceType_v4f32) {
emitUint8(0x6B); emitUint8(0x6B);
} else if (DestTy == IceType_v16i8) { } else if (Ty == IceType_v8i16) {
emitUint8(0x63); emitUint8(0x63);
} else { } else {
assert(false && "Unexpected vector pack operand type"); assert(false && "Unexpected vector pack operand type");
...@@ -1702,16 +1702,16 @@ void AssemblerX86Base<TraitsType>::packss(Type DestTy, XmmRegister Dst, ...@@ -1702,16 +1702,16 @@ void AssemblerX86Base<TraitsType>::packss(Type DestTy, XmmRegister Dst,
} }
template <typename TraitsType> template <typename TraitsType>
void AssemblerX86Base<TraitsType>::packus(Type DestTy, XmmRegister Dst, void AssemblerX86Base<TraitsType>::packus(Type Ty, XmmRegister Dst,
XmmRegister Src) { XmmRegister Src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer); AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66); emitUint8(0x66);
emitRexRB(RexTypeIrrelevant, Dst, Src); emitRexRB(RexTypeIrrelevant, Dst, Src);
emitUint8(0x0F); emitUint8(0x0F);
if (DestTy == IceType_v8i16) { if (Ty == IceType_v4i32 || Ty == IceType_v4f32) {
emitUint8(0x38); emitUint8(0x38);
emitUint8(0x2B); emitUint8(0x2B);
} else if (DestTy == IceType_v16i8) { } else if (Ty == IceType_v8i16) {
emitUint8(0x67); emitUint8(0x67);
} else { } else {
assert(false && "Unexpected vector pack operand type"); assert(false && "Unexpected vector pack operand type");
...@@ -1720,17 +1720,17 @@ void AssemblerX86Base<TraitsType>::packus(Type DestTy, XmmRegister Dst, ...@@ -1720,17 +1720,17 @@ void AssemblerX86Base<TraitsType>::packus(Type DestTy, XmmRegister Dst,
} }
template <typename TraitsType> template <typename TraitsType>
void AssemblerX86Base<TraitsType>::packus(Type DestTy, XmmRegister Dst, void AssemblerX86Base<TraitsType>::packus(Type Ty, XmmRegister Dst,
const Address &Src) { const Address &Src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer); AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66); emitUint8(0x66);
emitAddrSizeOverridePrefix(); emitAddrSizeOverridePrefix();
emitRex(RexTypeIrrelevant, Src, Dst); emitRex(RexTypeIrrelevant, Src, Dst);
emitUint8(0x0F); emitUint8(0x0F);
if (DestTy == IceType_v8i16) { if (Ty == IceType_v4i32 || Ty == IceType_v4f32) {
emitUint8(0x38); emitUint8(0x38);
emitUint8(0x2B); emitUint8(0x2B);
} else if (DestTy == IceType_v16i8) { } else if (Ty == IceType_v8i16) {
emitUint8(0x67); emitUint8(0x67);
} else { } else {
assert(false && "Unexpected vector pack operand type"); assert(false && "Unexpected vector pack operand type");
......
src/IceInstX86BaseImpl.h
...@@ -1059,6 +1059,7 @@ void InstImpl<TraitsType>::InstX86Movmsk::emitIAS(const Cfg *Func) const { ...@@ -1059,6 +1059,7 @@ void InstImpl<TraitsType>::InstX86Movmsk::emitIAS(const Cfg *Func) const {
const Variable *Dest = this->getDest(); const Variable *Dest = this->getDest();
const Variable *Src = llvm::cast<Variable>(this->getSrc(0)); const Variable *Src = llvm::cast<Variable>(this->getSrc(0));
const Type DestTy = Dest->getType(); const Type DestTy = Dest->getType();
(void)DestTy;
const Type SrcTy = Src->getType(); const Type SrcTy = Src->getType();
assert(isVectorType(SrcTy)); assert(isVectorType(SrcTy));
assert(isScalarIntegerType(DestTy)); assert(isScalarIntegerType(DestTy));
......
src/IceTargetLoweringX86BaseImpl.h
...@@ -435,9 +435,8 @@ template <typename TraitsType> ...@@ -435,9 +435,8 @@ template <typename TraitsType>
if (!Traits::Is64Bit || if (!Traits::Is64Bit ||
::Ice::getFlags().getApplicationBinaryInterface() == ::Ice::ABI_PNaCl) { ::Ice::getFlags().getApplicationBinaryInterface() == ::Ice::ABI_PNaCl) {
return ::Ice::IceType_i32; return ::Ice::IceType_i32;
} else {
return ::Ice::IceType_i64;
} }
return ::Ice::IceType_i64;
} }
template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() { template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() {
...@@ -4437,7 +4436,7 @@ void TargetX86Base<TraitsType>::lowerIntrinsicCall( ...@@ -4437,7 +4436,7 @@ void TargetX86Base<TraitsType>::lowerIntrinsicCall(
Operand *Src0 = Instr->getArg(0); Operand *Src0 = Instr->getArg(0);
Operand *Src1 = Instr->getArg(1); Operand *Src1 = Instr->getArg(1);
Variable *Dest = Instr->getDest(); Variable *Dest = Instr->getDest();
auto *T = makeReg(Dest->getType()); auto *T = makeReg(Src0->getType());
auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem); auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
auto *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem); auto *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
_movp(T, Src0RM); _movp(T, Src0RM);
...@@ -4449,7 +4448,7 @@ void TargetX86Base<TraitsType>::lowerIntrinsicCall( ...@@ -4449,7 +4448,7 @@ void TargetX86Base<TraitsType>::lowerIntrinsicCall(
Operand *Src0 = Instr->getArg(0); Operand *Src0 = Instr->getArg(0);
Operand *Src1 = Instr->getArg(1); Operand *Src1 = Instr->getArg(1);
Variable *Dest = Instr->getDest(); Variable *Dest = Instr->getDest();
auto *T = makeReg(Dest->getType()); auto *T = makeReg(Src0->getType());
auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem); auto *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
auto *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem); auto *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
_movp(T, Src0RM); _movp(T, Src0RM);
......
unittest/AssemblerX8632/DataMov.cpp
...@@ -973,7 +973,8 @@ TEST_F(AssemblerX8632Test, Movmsk) { ...@@ -973,7 +973,8 @@ TEST_F(AssemblerX8632Test, Movmsk) {
const Dqword V0 Value1; \ const Dqword V0 Value1; \
\ \
__ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \ __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \
__ Inst(GPRRegister::Encoded_Reg_##GPR, XmmRegister::Encoded_Reg_##Src); \ __ Inst(IceType_v4f32, GPRRegister::Encoded_Reg_##GPR, \
XmmRegister::Encoded_Reg_##Src); \
\ \
AssembledTest test = assemble(); \ AssembledTest test = assemble(); \
test.setDqwordTo(T0, V0); \ test.setDqwordTo(T0, V0); \
...@@ -985,8 +986,7 @@ TEST_F(AssemblerX8632Test, Movmsk) { ...@@ -985,8 +986,7 @@ TEST_F(AssemblerX8632Test, Movmsk) {
#define TestMovmsk(GPR, Src) \ #define TestMovmsk(GPR, Src) \
do { \ do { \
TestMovmskGPRXmm(GPR, Src, (-1.0, 1.0, -1.0, 1.0), 0x05ul, movmskps); \ TestMovmskGPRXmm(GPR, Src, (-1.0, 1.0, -1.0, 1.0), 0x05ul, movmsk); \
TestMovmskGPRXmm(GPR, Src, (1.0, -1.0), 0x02ul, movmskpd); \
} while (0) } while (0)
TestMovmsk(eax, xmm0); TestMovmsk(eax, xmm0);
......
unittest/AssemblerX8664/DataMov.cpp
...@@ -1361,7 +1361,7 @@ TEST_F(AssemblerX8664Test, Movmsk) { ...@@ -1361,7 +1361,7 @@ TEST_F(AssemblerX8664Test, Movmsk) {
const Dqword V0 Value1; \ const Dqword V0 Value1; \
\ \
__ movups(Encoded_Xmm_##Src(), dwordAddress(T0)); \ __ movups(Encoded_Xmm_##Src(), dwordAddress(T0)); \
__ Inst(Encoded_GPR_##GPR(), Encoded_Xmm_##Src()); \ __ Inst(IceType_v4f32, Encoded_GPR_##GPR(), Encoded_Xmm_##Src()); \
\ \
AssembledTest test = assemble(); \ AssembledTest test = assemble(); \
test.setDqwordTo(T0, V0); \ test.setDqwordTo(T0, V0); \
...@@ -1373,8 +1373,7 @@ TEST_F(AssemblerX8664Test, Movmsk) { ...@@ -1373,8 +1373,7 @@ TEST_F(AssemblerX8664Test, Movmsk) {
#define TestMovmsk(GPR, Src) \ #define TestMovmsk(GPR, Src) \
do { \ do { \
TestMovmskGPRXmm(GPR, Src, (-1.0, 1.0, -1.0, 1.0), 0x05ul, movmskps); \ TestMovmskGPRXmm(GPR, Src, (-1.0, 1.0, -1.0, 1.0), 0x05ul, movmsk); \
TestMovmskGPRXmm(GPR, Src, (1.0, -1.0), 0x02ul, movmskpd); \
} while (0) } while (0)
TestMovmsk(r1, xmm0); TestMovmsk(r1, xmm0);
......
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