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Commit 623f8ce3 by Srdjan Obucina Committed by Jim Stichnoth
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Subzero, MIPS32: Cross-testing enabled for MIPS32

Enables running crosstests for MIPS32 target. R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2085303002 . Patch from Srdjan Obucina <Srdjan.Obucina@imgtec.com>.
parent 98405d39
Showing with 280 additions and 43 deletions
Makefile.standalone
...@@ -523,6 +523,14 @@ RT_OBJ := build/runtime/szrt_native_x8632.o build/runtime/szrt_sb_x8632.o \ ...@@ -523,6 +523,14 @@ RT_OBJ := build/runtime/szrt_native_x8632.o build/runtime/szrt_sb_x8632.o \
build/runtime/szrt_asan_x8632.o build/runtime/szrt_asan_x8664.o \ build/runtime/szrt_asan_x8632.o build/runtime/szrt_asan_x8664.o \
build/runtime/szrt_asan_arm32.o build/runtime/szrt_asan_arm32.o
EXCLUDED_RT :=
ifdef MIPS
RT_SRC += runtime/szrt_asm_mips32.s
RT_OBJ += build/runtime/szrt_native_mips32.o build/runtime/szrt_sb_mips32.o
else
EXCLUDED_RT += --exclude-target=mips32
endif
runtime: $(RT_OBJ) runtime: $(RT_OBJ)
# Use runtime.is.built so that build-runtime.py is invoked only once # Use runtime.is.built so that build-runtime.py is invoked only once
...@@ -531,7 +539,8 @@ runtime: $(RT_OBJ) ...@@ -531,7 +539,8 @@ runtime: $(RT_OBJ)
$(RT_OBJ): runtime.is.built $(RT_OBJ): runtime.is.built
runtime.is.built: $(RT_SRC) pydir/build-runtime.py runtime.is.built: $(RT_SRC) pydir/build-runtime.py
@echo ================ Building Subzero runtime ================ @echo ================ Building Subzero runtime ================
./pydir/build-runtime.py -v --pnacl-root $(PNACL_TOOLCHAIN_ROOT) ./pydir/build-runtime.py -v --pnacl-root $(PNACL_TOOLCHAIN_ROOT) \
$(EXCLUDED_RT)
check-lit: $(OBJDIR)/pnacl-sz make_symlink runtime check-lit: $(OBJDIR)/pnacl-sz make_symlink runtime
PNACL_BIN_PATH=$(PNACL_BIN_PATH) \ PNACL_BIN_PATH=$(PNACL_BIN_PATH) \
...@@ -552,7 +561,8 @@ check-xtest check-xtest-lite: $(OBJDIR)/pnacl-sz make_symlink runtime \ ...@@ -552,7 +561,8 @@ check-xtest check-xtest-lite: $(OBJDIR)/pnacl-sz make_symlink runtime \
$(FORCEASM_FLAG) \ $(FORCEASM_FLAG) \
$(FORCEASM_XTEST_EXCLUDES) \ $(FORCEASM_XTEST_EXCLUDES) \
-i x8664,native,sse2 \ -i x8664,native,sse2 \
-i mips32,xxx -i mips32,native,Om1,simple_loop \
-i mips32,native,Om1,test_strengthreduce
PNACL_BIN_PATH=$(PNACL_BIN_PATH) \ PNACL_BIN_PATH=$(PNACL_BIN_PATH) \
$(LLVM_SRC_PATH)/utils/lit/lit.py -sv $(CHECK_XTEST_TESTS) $(LLVM_SRC_PATH)/utils/lit/lit.py -sv $(CHECK_XTEST_TESTS)
else else
...@@ -631,6 +641,14 @@ ifeq ($(TARGET),arm32) ...@@ -631,6 +641,14 @@ ifeq ($(TARGET),arm32)
SETUP=SetupGccArmOpt SETUP=SetupGccArmOpt
SPEC := --filetype=obj SPEC := --filetype=obj
endif endif
ifeq ($(TARGET),mips32)
# native_client/tests/spec2k/{Makefile.common,run_all.sh} do not currently
# have MIPS configs, so those would need to be added for proper Subzero
# testing.
TARGETFLAG=mips32
SETUP=SetupGccMipsOpt
SPEC := --filetype=asm
endif
SPECFLAGS := -O2 SPECFLAGS := -O2
SPECRUN := --run SPECRUN := --run
%.spec2k: % $(OBJDIR)/pnacl-sz make_symlink runtime %.spec2k: % $(OBJDIR)/pnacl-sz make_symlink runtime
......
pydir/build-runtime.py
...@@ -9,27 +9,25 @@ import targets ...@@ -9,27 +9,25 @@ import targets
from utils import FindBaseNaCl, GetObjcopyCmd, shellcmd from utils import FindBaseNaCl, GetObjcopyCmd, shellcmd
def Translate(ll_files, extra_args, obj, verbose): def Translate(ll_files, extra_args, obj, verbose, target):
"""Translate a set of input bitcode files into a single object file. """Translate a set of input bitcode files into a single object file.
Use pnacl-llc to translate textual bitcode input ll_files into object file Use pnacl-llc to translate textual bitcode input ll_files into object file
obj, using extra_args as the architectural flags. obj, using extra_args as the architectural flags.
""" """
externalize = [] if target == 'mips32' else ['-externalize']
shellcmd(['cat'] + ll_files + ['|', shellcmd(['cat'] + ll_files + ['|',
'pnacl-llc', 'pnacl-llc',
'-externalize',
'-function-sections', '-function-sections',
'-O2', '-O2',
'-filetype=obj', '-filetype=obj',
'-bitcode-format=llvm', '-bitcode-format=llvm',
'-arm-enable-dwarf-eh=1',
'-o', obj '-o', obj
] + extra_args, echo=verbose) ] + extra_args + externalize, echo=verbose)
shellcmd([GetObjcopyCmd(), strip_syms = [] if target == 'mips32' else ['nacl_tp_tdb_offset',
'--strip-symbol=nacl_tp_tdb_offset', 'nacl_tp_tls_offset']
'--strip-symbol=nacl_tp_tls_offset', shellcmd([GetObjcopyCmd(target), obj] +
obj [('--strip-symbol=' + sym) for sym in strip_syms])
], echo=verbose)
def PartialLink(obj_files, extra_args, lib, verbose): def PartialLink(obj_files, extra_args, lib, verbose):
...@@ -41,8 +39,10 @@ def PartialLink(obj_files, extra_args, lib, verbose): ...@@ -41,8 +39,10 @@ def PartialLink(obj_files, extra_args, lib, verbose):
def MakeRuntimesForTarget(target_info, ll_files, def MakeRuntimesForTarget(target_info, ll_files,
srcdir, tempdir, rtdir, verbose): srcdir, tempdir, rtdir, verbose, excluded_targets):
"""Builds native, sandboxed, and nonsfi runtimes for the given target.""" """Builds native, sandboxed, and nonsfi runtimes for the given target."""
if target_info.target in excluded_targets:
return
# File-mangling helper functions. # File-mangling helper functions.
def TmpFile(template): def TmpFile(template):
return template.format(dir=tempdir, target=target_info.target) return template.format(dir=tempdir, target=target_info.target)
...@@ -56,7 +56,7 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -56,7 +56,7 @@ def MakeRuntimesForTarget(target_info, ll_files,
Translate(ll_files, Translate(ll_files,
['-mtriple=' + target_info.triple] + target_info.llc_flags, ['-mtriple=' + target_info.triple] + target_info.llc_flags,
TmpFile('{dir}/szrt_native_{target}.tmp.o'), TmpFile('{dir}/szrt_native_{target}.tmp.o'),
verbose) verbose, target_info.target)
# Compile srcdir/szrt_profiler.c to # Compile srcdir/szrt_profiler.c to
# tempdir/szrt_profiler_native_{target}.o. # tempdir/szrt_profiler_native_{target}.o.
shellcmd(['clang', shellcmd(['clang',
...@@ -81,7 +81,7 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -81,7 +81,7 @@ def MakeRuntimesForTarget(target_info, ll_files,
['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)], ['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)],
OutFile('{rtdir}/szrt_native_{target}.o'), OutFile('{rtdir}/szrt_native_{target}.o'),
verbose) verbose)
shellcmd([GetObjcopyCmd(), shellcmd([GetObjcopyCmd(target_info.target),
'--strip-symbol=NATIVE', '--strip-symbol=NATIVE',
OutFile('{rtdir}/szrt_native_{target}.o')]) OutFile('{rtdir}/szrt_native_{target}.o')])
# Compile srcdir/szrt_asan.c to szrt_asan_{target}.o # Compile srcdir/szrt_asan.c to szrt_asan_{target}.o
...@@ -103,7 +103,7 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -103,7 +103,7 @@ def MakeRuntimesForTarget(target_info, ll_files,
['-mtriple=' + targets.ConvertTripleToNaCl(target_info.triple)] + ['-mtriple=' + targets.ConvertTripleToNaCl(target_info.triple)] +
target_info.llc_flags, target_info.llc_flags,
TmpFile('{dir}/szrt_sb_{target}.tmp.o'), TmpFile('{dir}/szrt_sb_{target}.tmp.o'),
verbose) verbose,target_info.target)
# Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o. # Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
shellcmd(['llvm-mc', shellcmd(['llvm-mc',
'-triple=' + targets.ConvertTripleToNaCl(target_info.triple), '-triple=' + targets.ConvertTripleToNaCl(target_info.triple),
...@@ -118,7 +118,7 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -118,7 +118,7 @@ def MakeRuntimesForTarget(target_info, ll_files,
['-m {ld_emu}'.format(ld_emu=target_info.sb_emu)], ['-m {ld_emu}'.format(ld_emu=target_info.sb_emu)],
OutFile('{rtdir}/szrt_sb_{target}.o'), OutFile('{rtdir}/szrt_sb_{target}.o'),
verbose) verbose)
shellcmd([GetObjcopyCmd(), shellcmd([GetObjcopyCmd(target_info.target),
'--strip-symbol=NACL', '--strip-symbol=NACL',
OutFile('{rtdir}/szrt_sb_{target}.o')]) OutFile('{rtdir}/szrt_sb_{target}.o')])
...@@ -131,7 +131,7 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -131,7 +131,7 @@ def MakeRuntimesForTarget(target_info, ll_files,
['-mtriple=' + target_info.triple] + target_info.llc_flags + ['-mtriple=' + target_info.triple] + target_info.llc_flags +
['-relocation-model=pic', '-force-tls-non-pic', '-malign-double'], ['-relocation-model=pic', '-force-tls-non-pic', '-malign-double'],
TmpFile('{dir}/szrt_nonsfi_{target}.tmp.o'), TmpFile('{dir}/szrt_nonsfi_{target}.tmp.o'),
verbose) verbose, target_info.target)
# Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o. # Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
shellcmd(['llvm-mc', shellcmd(['llvm-mc',
'-triple=' + target_info.triple, '--defsym NONSFI=1', '-triple=' + target_info.triple, '--defsym NONSFI=1',
...@@ -146,7 +146,7 @@ def MakeRuntimesForTarget(target_info, ll_files, ...@@ -146,7 +146,7 @@ def MakeRuntimesForTarget(target_info, ll_files,
['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)], ['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)],
OutFile('{rtdir}/szrt_nonsfi_{target}.o'), OutFile('{rtdir}/szrt_nonsfi_{target}.o'),
verbose) verbose)
shellcmd([GetObjcopyCmd(), shellcmd([GetObjcopyCmd(target_info.target),
'--strip-symbol=NONSFI', '--strip-symbol=NONSFI',
OutFile('{rtdir}/szrt_nonsfi_{target}.o')]) OutFile('{rtdir}/szrt_nonsfi_{target}.o')])
...@@ -172,6 +172,9 @@ def main(): ...@@ -172,6 +172,9 @@ def main():
'{root}/toolchain/linux_x86/pnacl_newlib_raw' '{root}/toolchain/linux_x86/pnacl_newlib_raw'
).format(root=nacl_root), ).format(root=nacl_root),
help='Path to PNaCl toolchain binaries.') help='Path to PNaCl toolchain binaries.')
argparser.add_argument('--exclude-target', dest='excluded_targets',
default=[], action='append',
help='Target whose runtime should not be built')
args = argparser.parse_args() args = argparser.parse_args()
os.environ['PATH'] = ('{root}/bin{sep}{path}' os.environ['PATH'] = ('{root}/bin{sep}{path}'
).format(root=args.pnacl_root, sep=os.pathsep, path=os.environ['PATH']) ).format(root=args.pnacl_root, sep=os.pathsep, path=os.environ['PATH'])
...@@ -206,11 +209,17 @@ def main(): ...@@ -206,11 +209,17 @@ def main():
'{srcdir}/szrt_ll.ll'.format(srcdir=srcdir)] '{srcdir}/szrt_ll.ll'.format(srcdir=srcdir)]
MakeRuntimesForTarget(targets.X8632Target, ll_files, MakeRuntimesForTarget(targets.X8632Target, ll_files,
srcdir, tempdir, rtdir, args.verbose) srcdir, tempdir, rtdir, args.verbose,
args.excluded_targets)
MakeRuntimesForTarget(targets.X8664Target, ll_files, MakeRuntimesForTarget(targets.X8664Target, ll_files,
srcdir, tempdir, rtdir, args.verbose) srcdir, tempdir, rtdir, args.verbose,
args.excluded_targets)
MakeRuntimesForTarget(targets.ARM32Target, ll_files, MakeRuntimesForTarget(targets.ARM32Target, ll_files,
srcdir, tempdir, rtdir, args.verbose) srcdir, tempdir, rtdir, args.verbose,
args.excluded_targets)
MakeRuntimesForTarget(targets.MIPS32Target, ll_files,
srcdir, tempdir, rtdir, args.verbose,
args.excluded_targets)
finally: finally:
try: try:
......
pydir/crosstest.py
...@@ -26,12 +26,14 @@ def main(): ...@@ -26,12 +26,14 @@ def main():
# arch_map maps a Subzero target string to TargetInfo (e.g., triple). # arch_map maps a Subzero target string to TargetInfo (e.g., triple).
arch_map = { 'x8632': targets.X8632Target, arch_map = { 'x8632': targets.X8632Target,
'x8664': targets.X8664Target, 'x8664': targets.X8664Target,
'arm32': targets.ARM32Target } 'arm32': targets.ARM32Target,
'mips32': targets.MIPS32Target}
arch_sz_flags = { 'x8632': [], arch_sz_flags = { 'x8632': [],
'x8664': [], 'x8664': [],
# For ARM, test a large stack offset as well. +/- 4095 is # For ARM, test a large stack offset as well. +/- 4095 is
# the limit, so test somewhere near that boundary. # the limit, so test somewhere near that boundary.
'arm32': ['--test-stack-extra', '4084'] 'arm32': ['--test-stack-extra', '4084'],
'mips32': ['--test-stack-extra', '4084']
} }
arch_llc_flags_extra = { arch_llc_flags_extra = {
# Use sse2 instructions regardless of input -mattr # Use sse2 instructions regardless of input -mattr
...@@ -40,6 +42,7 @@ def main(): ...@@ -40,6 +42,7 @@ def main():
'x8632': ['-mattr=sse2'], 'x8632': ['-mattr=sse2'],
'x8664': ['-mattr=sse2'], 'x8664': ['-mattr=sse2'],
'arm32': [], 'arm32': [],
'mips32':[],
} }
desc = 'Build a cross-test that compares Subzero and llc translation.' desc = 'Build a cross-test that compares Subzero and llc translation.'
argparser = argparse.ArgumentParser(description=desc) argparser = argparse.ArgumentParser(description=desc)
...@@ -64,7 +67,8 @@ def main(): ...@@ -64,7 +67,8 @@ def main():
dest='clang_opt') dest='clang_opt')
argparser.add_argument('--mattr', required=False, default='sse2', argparser.add_argument('--mattr', required=False, default='sse2',
dest='attr', choices=['sse2', 'sse4.1', dest='attr', choices=['sse2', 'sse4.1',
'neon', 'hwdiv-arm'], 'neon', 'hwdiv-arm',
'base'],
metavar='ATTRIBUTE', metavar='ATTRIBUTE',
help='Target attribute. Default %(default)s.') help='Target attribute. Default %(default)s.')
argparser.add_argument('--sandbox', required=False, default=0, type=int, argparser.add_argument('--sandbox', required=False, default=0, type=int,
...@@ -167,7 +171,8 @@ def main(): ...@@ -167,7 +171,8 @@ def main():
# linked into the executable, but when PNaCl supports shared nexe # linked into the executable, but when PNaCl supports shared nexe
# libraries, this would need to change. (Note: the same issue applies # libraries, this would need to change. (Note: the same issue applies
# to the __Sz_revision symbol.) # to the __Sz_revision symbol.)
shellcmd(['{bin}/{objcopy}'.format(bin=bindir, objcopy=GetObjcopyCmd()), shellcmd(['{bin}/{objcopy}'.format(bin=bindir,
objcopy=GetObjcopyCmd(args.target)),
'--weaken-symbol=__Sz_block_profile_info', '--weaken-symbol=__Sz_block_profile_info',
'--weaken-symbol=__Sz_revision', '--weaken-symbol=__Sz_revision',
'--strip-symbol=nacl_tp_tdb_offset', '--strip-symbol=nacl_tp_tdb_offset',
...@@ -175,17 +180,18 @@ def main(): ...@@ -175,17 +180,18 @@ def main():
obj_sz]) obj_sz])
objs.append(obj_sz) objs.append(obj_sz)
shellcmd(['{bin}/pnacl-llc'.format(bin=bindir), shellcmd(['{bin}/pnacl-llc'.format(bin=bindir),
'-arm-enable-dwarf-eh=1',
'-mtriple=' + triple, '-mtriple=' + triple,
'-externalize', '-externalize',
'-filetype=obj', '-filetype=obj',
'-bitcode-format=llvm', '-bitcode-format=llvm',
'-o=' + obj_llc, '-o=' + obj_llc,
bitcode] + llc_flags) bitcode] + llc_flags)
shellcmd(['{bin}/{objcopy}'.format(bin=bindir, objcopy=GetObjcopyCmd()), strip_syms = [] if args.target == 'mips32' else ['nacl_tp_tdb_offset',
'--strip-symbol=nacl_tp_tdb_offset', 'nacl_tp_tls_offset']
'--strip-symbol=nacl_tp_tls_offset', shellcmd(['{bin}/{objcopy}'.format(bin=bindir,
obj_llc]) objcopy=GetObjcopyCmd(args.target)),
obj_llc] +
[('--strip-symbol=' + sym) for sym in strip_syms])
objs.append(obj_llc) objs.append(obj_llc)
# Add szrt_sb_${target}.o or szrt_native_${target}.o. # Add szrt_sb_${target}.o or szrt_native_${target}.o.
...@@ -244,7 +250,6 @@ def main(): ...@@ -244,7 +250,6 @@ def main():
'-disable-opt', '-disable-opt',
bitcode_nonfinal, '-S', '-o', bitcode]) bitcode_nonfinal, '-S', '-o', bitcode])
shellcmd(['{bin}/pnacl-llc'.format(bin=bindir), shellcmd(['{bin}/pnacl-llc'.format(bin=bindir),
'-arm-enable-dwarf-eh=1',
'-mtriple=' + triple, '-mtriple=' + triple,
'-externalize', '-externalize',
'-filetype=obj', '-filetype=obj',
...@@ -253,7 +258,8 @@ def main(): ...@@ -253,7 +258,8 @@ def main():
'-o', obj_llc, '-o', obj_llc,
bitcode] + llc_flags) bitcode] + llc_flags)
if not args.sandbox and not args.nonsfi: if not args.sandbox and not args.nonsfi:
shellcmd(['{bin}/{objcopy}'.format(bin=bindir, objcopy=GetObjcopyCmd()), shellcmd(['{bin}/{objcopy}'.format(bin=bindir,
objcopy=GetObjcopyCmd(args.target)),
'--redefine-sym', '_start=_user_start', '--redefine-sym', '_start=_user_start',
obj_llc obj_llc
]) ])
......
pydir/crosstest_generator.py
...@@ -39,10 +39,13 @@ def RunNativePrefix(toolchain_root, target, attr, run_cmd): ...@@ -39,10 +39,13 @@ def RunNativePrefix(toolchain_root, target, attr, run_cmd):
'x8664' : '', 'x8664' : '',
'arm32' : os.path.join(toolchain_root, 'arm_trusted', 'arm32' : os.path.join(toolchain_root, 'arm_trusted',
'run_under_qemu_arm'), 'run_under_qemu_arm'),
'mips32': os.path.join(toolchain_root, 'mips_trusted',
'run_under_qemu_mips32'),
} }
attr_map = collections.defaultdict(str, { attr_map = collections.defaultdict(str, {
'arm32-neon': ' -cpu cortex-a9', 'arm32-neon': ' -cpu cortex-a9',
'arm32-hwdiv-arm': ' -cpu cortex-a15' }) 'arm32-hwdiv-arm': ' -cpu cortex-a15',
'mips32-base': ' -cpu mips32r5-generic'})
prefix = arch_map[target] + attr_map[target + '-' + attr] prefix = arch_map[target] + attr_map[target + '-' + attr]
return (prefix + ' ' + run_cmd) if prefix else run_cmd return (prefix + ' ' + run_cmd) if prefix else run_cmd
...@@ -50,6 +53,7 @@ def NonsfiLoaderArch(target): ...@@ -50,6 +53,7 @@ def NonsfiLoaderArch(target):
"""Returns the arch for the nonsfi_loader""" """Returns the arch for the nonsfi_loader"""
arch_map = { 'arm32' : 'arm', arch_map = { 'arm32' : 'arm',
'x8632' : 'x86-32', 'x8632' : 'x86-32',
'mips32' : 'mips32',
} }
return arch_map[target] return arch_map[target]
...@@ -66,18 +70,22 @@ def main(): ...@@ -66,18 +70,22 @@ def main():
root = FindBaseNaCl() root = FindBaseNaCl()
# The rest of the attribute sets. # The rest of the attribute sets.
targets = [ 'x8632', 'x8664', 'arm32' ] targets = [ 'x8632', 'x8664', 'arm32', 'mips32' ]
sandboxing = [ 'native', 'sandbox', 'nonsfi' ] sandboxing = [ 'native', 'sandbox', 'nonsfi' ]
opt_levels = [ 'Om1', 'O2' ] opt_levels = [ 'Om1', 'O2' ]
arch_attrs = { 'x8632': [ 'sse2', 'sse4.1' ], arch_attrs = { 'x8632': [ 'sse2', 'sse4.1' ],
'x8664': [ 'sse2', 'sse4.1' ], 'x8664': [ 'sse2', 'sse4.1' ],
'arm32': [ 'neon', 'hwdiv-arm' ] } 'arm32': [ 'neon', 'hwdiv-arm' ],
'mips32': [ 'base' ]
}
flat_attrs = [] flat_attrs = []
for v in arch_attrs.values(): for v in arch_attrs.values():
flat_attrs += v flat_attrs += v
arch_flags = { 'x8632': [], arch_flags = { 'x8632': [],
'x8664': [], 'x8664': [],
'arm32': [] } 'arm32': [],
'mips32': []
}
# all_keys is only used in the help text. # all_keys is only used in the help text.
all_keys = '; '.join([' '.join(targets), ' '.join(sandboxing), all_keys = '; '.join([' '.join(targets), ' '.join(sandboxing),
' '.join(opt_levels), ' '.join(flat_attrs)]) ' '.join(opt_levels), ' '.join(flat_attrs)])
......
pydir/run-pnacl-sz.py
...@@ -20,7 +20,9 @@ def TargetAssemblerFlags(target, sandboxed): ...@@ -20,7 +20,9 @@ def TargetAssemblerFlags(target, sandboxed):
'arm32': ['-triple=%s' % ( 'arm32': ['-triple=%s' % (
'armv7a-nacl' if sandboxed else 'armv7a'), 'armv7a-nacl' if sandboxed else 'armv7a'),
'-mcpu=cortex-a9', '-mattr=+neon'], '-mcpu=cortex-a9', '-mattr=+neon'],
'mips32': ['-triple=mipsel' ] } 'mips32': ['-triple=%s' % (
'mipsel-nacl' if sandboxed else 'mipsel'),
'-mcpu=mips32'] }
return flags[target] return flags[target]
...@@ -204,7 +206,7 @@ def main(): ...@@ -204,7 +206,7 @@ def main():
if args.disassemble: if args.disassemble:
# Show wide instruction encodings, diassemble, show relocs and # Show wide instruction encodings, diassemble, show relocs and
# dissasemble zeros. # dissasemble zeros.
cmd += (['&&', os.path.join(pnacl_bin_path, GetObjdumpCmd())] + cmd += (['&&', os.path.join(pnacl_bin_path, GetObjdumpCmd(args.target))] +
args.dis_flags + args.dis_flags +
['-w', '-d', '-r', '-z'] + TargetDisassemblerFlags(args.target) + ['-w', '-d', '-r', '-z'] + TargetDisassemblerFlags(args.target) +
[output_file_name]) [output_file_name])
......
pydir/szbuild.py
...@@ -186,6 +186,7 @@ def LinkNative(objs, exe, target, verbose=True): ...@@ -186,6 +186,7 @@ def LinkNative(objs, exe, target, verbose=True):
nacl_root = FindBaseNaCl() nacl_root = FindBaseNaCl()
linker = { linker = {
'arm32': '/usr/bin/arm-linux-gnueabihf-g++', 'arm32': '/usr/bin/arm-linux-gnueabihf-g++',
'mips32': '/usr/bin/mipsel-linux-gnu-g++',
'x8632': ('{root}/../third_party/llvm-build/Release+Asserts/bin/clang' 'x8632': ('{root}/../third_party/llvm-build/Release+Asserts/bin/clang'
).format(root=nacl_root), ).format(root=nacl_root),
'x8664': ('{root}/../third_party/llvm-build/Release+Asserts/bin/clang' 'x8664': ('{root}/../third_party/llvm-build/Release+Asserts/bin/clang'
...@@ -297,7 +298,7 @@ def ProcessPexe(args, pexe, exe): ...@@ -297,7 +298,7 @@ def ProcessPexe(args, pexe, exe):
llcbin = '{base}/pnacl-llc'.format(base=path_addition) llcbin = '{base}/pnacl-llc'.format(base=path_addition)
gold = '{base}/le32-nacl-ld.gold'.format(base=path_addition) gold = '{base}/le32-nacl-ld.gold'.format(base=path_addition)
objcopy = '{base}/{objcopy}'.format(base=path_addition, objcopy = '{base}/{objcopy}'.format(base=path_addition,
objcopy=GetObjcopyCmd()) objcopy=GetObjcopyCmd(args.target))
opt_level = args.optlevel opt_level = args.optlevel
opt_level_map = { 'm1':'0', '-1':'0', '0':'0', '1':'1', '2':'2' } opt_level_map = { 'm1':'0', '-1':'0', '0':'0', '1':'1', '2':'2' }
hybrid = args.include or args.exclude hybrid = args.include or args.exclude
......
pydir/targets.py
...@@ -15,6 +15,9 @@ def FindARMCrossInclude(): ...@@ -15,6 +15,9 @@ def FindARMCrossInclude():
return glob.glob( return glob.glob(
'/usr/arm-linux-gnueabihf/include/c++/*/arm-linux-gnueabihf')[-1] '/usr/arm-linux-gnueabihf/include/c++/*/arm-linux-gnueabihf')[-1]
def FindMIPSCrossInclude():
globs = glob.glob('/usr/mipsel-linux-gnu/include/c++/*/mipsel-linux-gnu')
return globs[-1] if globs else '/invalid/mips/include/path'
TargetInfo = namedtuple('TargetInfo', TargetInfo = namedtuple('TargetInfo',
['target', 'compiler_arch', 'triple', 'llc_flags', ['target', 'compiler_arch', 'triple', 'llc_flags',
...@@ -41,10 +44,21 @@ ARM32Target = TargetInfo(target='arm32', ...@@ -41,10 +44,21 @@ ARM32Target = TargetInfo(target='arm32',
triple='armv7a-none-linux-gnueabihf', triple='armv7a-none-linux-gnueabihf',
llc_flags=['-mcpu=cortex-a9', llc_flags=['-mcpu=cortex-a9',
'-float-abi=hard', '-float-abi=hard',
'-mattr=+neon'], '-mattr=+neon',
'-arm-enable-dwarf-eh=1'],
ld_emu='armelf_nacl', ld_emu='armelf_nacl',
sb_emu='armelf_nacl', sb_emu='armelf_nacl',
cross_headers=['-isystem', FindARMCrossInclude()]) cross_headers=['-isystem', FindARMCrossInclude()])
# Investigate:
# ld_emu script mips_nacl is not present in binutils. How to get it?
MIPS32Target = TargetInfo(target='mips32',
compiler_arch='mips32',
triple='mipsel-linux-gnu',
llc_flags=[],
ld_emu='mips_nacl',
sb_emu='mips_nacl',
cross_headers=['-isystem', FindMIPSCrossInclude()])
def ConvertTripleToNaCl(nonsfi_triple): def ConvertTripleToNaCl(nonsfi_triple):
return nonsfi_triple[:nonsfi_triple.find('-linux')] + '-nacl' return nonsfi_triple[:nonsfi_triple.find('-linux')] + '-nacl'
pydir/utils.py
...@@ -2,12 +2,16 @@ import os ...@@ -2,12 +2,16 @@ import os
import subprocess import subprocess
import sys import sys
def GetObjcopyCmd(): def GetObjcopyCmd(target):
"""Return a suitable objcopy command.""" """Return a suitable objcopy command."""
if target == 'mips32':
return 'mipsel-nacl-objcopy'
return 'arm-nacl-objcopy' return 'arm-nacl-objcopy'
def GetObjdumpCmd(): def GetObjdumpCmd(target):
"""Return a suitable objdump command.""" """Return a suitable objdump command."""
if target == 'mips32':
return 'mipsel-nacl-objdump'
return 'arm-nacl-objdump' return 'arm-nacl-objdump'
def shellcmd(command, echo=True): def shellcmd(command, echo=True):
......
runtime/szrt_asm_mips32.s 0 → 100644
##===- subzero/runtime/szrt_asm_mips32.s - Subzero runtime asm helpers-----===##
##
## The Subzero Code Generator
##
## This file is distributed under the University of Illinois Open Source
## License. See LICENSE.TXT for details.
##
##===----------------------------------------------------------------------===##
##
## This file provides an assembly implementation of various helpers needed by
## the Subzero mips32 runtime.
##
##===----------------------------------------------------------------------===##
.text
.p2alignl 4,0x00000034
src/IceAssemblerMIPS32.cpp
...@@ -201,6 +201,17 @@ void AssemblerMIPS32::bind(Label *L) { ...@@ -201,6 +201,17 @@ void AssemblerMIPS32::bind(Label *L) {
L->bindTo(BoundPc); L->bindTo(BoundPc);
} }
void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs,
const Operand *OpRt, const char *InsnName) {
const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
Opcode |= Rs << 21;
Opcode |= Rt << 16;
emitInst(Opcode);
}
void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt,
const Operand *OpRs, const uint32_t Imm, const Operand *OpRs, const uint32_t Imm,
const char *InsnName) { const char *InsnName) {
...@@ -509,6 +520,11 @@ void AssemblerMIPS32::cvt_s_w(const Operand *OpFd, const Operand *OpFs) { ...@@ -509,6 +520,11 @@ void AssemblerMIPS32::cvt_s_w(const Operand *OpFd, const Operand *OpFs) {
emitCOP1FmtFsFd(Opcode, Word, OpFd, OpFs, "cvt.s.w"); emitCOP1FmtFsFd(Opcode, Word, OpFd, OpFs, "cvt.s.w");
} }
void AssemblerMIPS32::div(const Operand *OpRs, const Operand *OpRt) {
static constexpr IValueT Opcode = 0x0000001A;
emitRsRt(Opcode, OpRs, OpRt, "div");
}
void AssemblerMIPS32::div_d(const Operand *OpFd, const Operand *OpFs, void AssemblerMIPS32::div_d(const Operand *OpFd, const Operand *OpFs,
const Operand *OpFt) { const Operand *OpFt) {
static constexpr IValueT Opcode = 0x44000003; static constexpr IValueT Opcode = 0x44000003;
...@@ -521,6 +537,14 @@ void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs, ...@@ -521,6 +537,14 @@ void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs,
emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s"); emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
} }
void AssemblerMIPS32::lui(const Operand *OpRt, const uint16_t Imm) {
IValueT Opcode = 0x3C000000;
const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui");
Opcode |= Rt << 16;
Opcode |= Imm;
emitInst(Opcode);
}
void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase, void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
const uint32_t Offset) { const uint32_t Offset) {
switch (OpRt->getType()) { switch (OpRt->getType()) {
...@@ -559,6 +583,20 @@ void AssemblerMIPS32::mfc1(const Operand *OpRt, const Operand *OpFs) { ...@@ -559,6 +583,20 @@ void AssemblerMIPS32::mfc1(const Operand *OpRt, const Operand *OpFs) {
emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mfc1"); emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mfc1");
} }
void AssemblerMIPS32::mfhi(const Operand *OpRd) {
IValueT Opcode = 0x000000010;
IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi");
Opcode |= Rd << 11;
emitInst(Opcode);
}
void AssemblerMIPS32::mflo(const Operand *OpRd) {
IValueT Opcode = 0x000000012;
IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo");
Opcode |= Rd << 11;
emitInst(Opcode);
}
void AssemblerMIPS32::mov_d(const Operand *OpFd, const Operand *OpFs) { void AssemblerMIPS32::mov_d(const Operand *OpFd, const Operand *OpFs) {
static constexpr IValueT Opcode = 0x44000006; static constexpr IValueT Opcode = 0x44000006;
emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "mov.d"); emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "mov.d");
...@@ -677,6 +715,26 @@ void AssemblerMIPS32::mtc1(const Operand *OpRt, const Operand *OpFs) { ...@@ -677,6 +715,26 @@ void AssemblerMIPS32::mtc1(const Operand *OpRt, const Operand *OpFs) {
emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mtc1"); emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mtc1");
} }
void AssemblerMIPS32::mthi(const Operand *OpRs) {
IValueT Opcode = 0x000000011;
IValueT Rs = encodeGPRegister(OpRs, "Rs", "mthi");
Opcode |= Rs << 21;
emitInst(Opcode);
}
void AssemblerMIPS32::mtlo(const Operand *OpRs) {
IValueT Opcode = 0x000000013;
IValueT Rs = encodeGPRegister(OpRs, "Rs", "mtlo");
Opcode |= Rs << 21;
emitInst(Opcode);
}
void AssemblerMIPS32::mul(const Operand *OpRd, const Operand *OpRs,
const Operand *OpRt) {
static constexpr IValueT Opcode = 0x70000002;
emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "mul");
}
void AssemblerMIPS32::mul_d(const Operand *OpFd, const Operand *OpFs, void AssemblerMIPS32::mul_d(const Operand *OpFd, const Operand *OpFs,
const Operand *OpFt) { const Operand *OpFt) {
static constexpr IValueT Opcode = 0x44000002; static constexpr IValueT Opcode = 0x44000002;
...@@ -689,6 +747,11 @@ void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs, ...@@ -689,6 +747,11 @@ void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs,
emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s"); emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s");
} }
void AssemblerMIPS32::multu(const Operand *OpRs, const Operand *OpRt) {
static constexpr IValueT Opcode = 0x00000019;
emitRsRt(Opcode, OpRs, OpRt, "multu");
}
void AssemblerMIPS32::nor(const Operand *OpRd, const Operand *OpRs, void AssemblerMIPS32::nor(const Operand *OpRd, const Operand *OpRs,
const Operand *OpRt) { const Operand *OpRt) {
static constexpr IValueT Opcode = 0x00000027; static constexpr IValueT Opcode = 0x00000027;
...@@ -719,6 +782,12 @@ void AssemblerMIPS32::sll(const Operand *OpRd, const Operand *OpRt, ...@@ -719,6 +782,12 @@ void AssemblerMIPS32::sll(const Operand *OpRd, const Operand *OpRt,
emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sll"); emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sll");
} }
void AssemblerMIPS32::sllv(const Operand *OpRd, const Operand *OpRt,
const Operand *OpRs) {
static constexpr IValueT Opcode = 0x00000004;
emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sllv");
}
void AssemblerMIPS32::slt(const Operand *OpRd, const Operand *OpRs, void AssemblerMIPS32::slt(const Operand *OpRd, const Operand *OpRs,
const Operand *OpRt) { const Operand *OpRt) {
static constexpr IValueT Opcode = 0x0000002A; static constexpr IValueT Opcode = 0x0000002A;
...@@ -765,6 +834,12 @@ void AssemblerMIPS32::srl(const Operand *OpRd, const Operand *OpRt, ...@@ -765,6 +834,12 @@ void AssemblerMIPS32::srl(const Operand *OpRd, const Operand *OpRt,
emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl"); emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl");
} }
void AssemblerMIPS32::srlv(const Operand *OpRd, const Operand *OpRt,
const Operand *OpRs) {
static constexpr IValueT Opcode = 0x00000006;
emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srlv");
}
void AssemblerMIPS32::sub_d(const Operand *OpFd, const Operand *OpFs, void AssemblerMIPS32::sub_d(const Operand *OpFd, const Operand *OpFs,
const Operand *OpFt) { const Operand *OpFt) {
static constexpr IValueT Opcode = 0x44000001; static constexpr IValueT Opcode = 0x44000001;
......
src/IceAssemblerMIPS32.h
...@@ -60,6 +60,9 @@ public: ...@@ -60,6 +60,9 @@ public:
void nop(); void nop();
void emitRsRt(IValueT Opcode, const Operand *OpRs, const Operand *OpRt,
const char *InsnName);
void emitRtRsImm16(IValueT Opcode, const Operand *OpRt, const Operand *OpRs, void emitRtRsImm16(IValueT Opcode, const Operand *OpRt, const Operand *OpRs,
uint32_t Imm, const char *InsnName); uint32_t Imm, const char *InsnName);
...@@ -154,14 +157,22 @@ public: ...@@ -154,14 +157,22 @@ public:
void cvt_s_w(const Operand *OpFd, const Operand *OpFs); void cvt_s_w(const Operand *OpFd, const Operand *OpFs);
void div(const Operand *OpRs, const Operand *OpRt);
void div_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt); void div_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
void div_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt); void div_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
void lui(const Operand *OpRt, const uint16_t Imm);
void lw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset); void lw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
void mfc1(const Operand *OpRt, const Operand *OpFs); void mfc1(const Operand *OpRt, const Operand *OpFs);
void mfhi(const Operand *OpRd);
void mflo(const Operand *OpRd);
void mov_d(const Operand *OpFd, const Operand *OpFs); void mov_d(const Operand *OpFd, const Operand *OpFs);
void mov_s(const Operand *OpFd, const Operand *OpFs); void mov_s(const Operand *OpFd, const Operand *OpFs);
...@@ -184,10 +195,18 @@ public: ...@@ -184,10 +195,18 @@ public:
void mtc1(const Operand *OpRt, const Operand *OpFs); void mtc1(const Operand *OpRt, const Operand *OpFs);
void mthi(const Operand *OpRs);
void mtlo(const Operand *OpRs);
void mul(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
void mul_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt); void mul_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
void mul_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt); void mul_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
void multu(const Operand *OpRs, const Operand *OpRt);
void nor(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt); void nor(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
void or_(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt); void or_(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
...@@ -198,6 +217,8 @@ public: ...@@ -198,6 +217,8 @@ public:
void sll(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa); void sll(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
void sllv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
void slt(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt); void slt(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm); void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
...@@ -214,6 +235,8 @@ public: ...@@ -214,6 +235,8 @@ public:
void srl(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa); void srl(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
void srlv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
void sub_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt); void sub_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
void sub_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt); void sub_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
......
src/IceInstMIPS32.cpp
...@@ -890,6 +890,11 @@ template <> void InstMIPS32Cvt_s_w::emitIAS(const Cfg *Func) const { ...@@ -890,6 +890,11 @@ template <> void InstMIPS32Cvt_s_w::emitIAS(const Cfg *Func) const {
Asm->cvt_s_w(getDest(), getSrc(0)); Asm->cvt_s_w(getDest(), getSrc(0));
} }
template <> void InstMIPS32Div::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->div(getDest(), getSrc(0));
}
template <> void InstMIPS32Div_d::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Div_d::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->div_d(getDest(), getSrc(0), getSrc(1)); Asm->div_d(getDest(), getSrc(0), getSrc(1));
...@@ -900,6 +905,13 @@ template <> void InstMIPS32Div_s::emitIAS(const Cfg *Func) const { ...@@ -900,6 +905,13 @@ template <> void InstMIPS32Div_s::emitIAS(const Cfg *Func) const {
Asm->div_s(getDest(), getSrc(0), getSrc(1)); Asm->div_s(getDest(), getSrc(0), getSrc(1));
} }
template <> void InstMIPS32Lui::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
auto *C32 = llvm::dyn_cast<ConstantInteger32>(getSrc(0));
uint16_t Imm = static_cast<uint16_t>(C32->getValue());
Asm->lui(getDest(), Imm);
}
template <> void InstMIPS32Lw::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Lw::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
auto *Mem = llvm::dyn_cast<OperandMIPS32Mem>(getSrc(0)); auto *Mem = llvm::dyn_cast<OperandMIPS32Mem>(getSrc(0));
...@@ -919,12 +931,22 @@ template <> void InstMIPS32Mflo::emit(const Cfg *Func) const { ...@@ -919,12 +931,22 @@ template <> void InstMIPS32Mflo::emit(const Cfg *Func) const {
emitUnaryopGPRFLoHi(Opcode, this, Func); emitUnaryopGPRFLoHi(Opcode, this, Func);
} }
template <> void InstMIPS32Mflo::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mflo(getDest());
}
template <> void InstMIPS32Mfhi::emit(const Cfg *Func) const { template <> void InstMIPS32Mfhi::emit(const Cfg *Func) const {
if (!BuildDefs::dump()) if (!BuildDefs::dump())
return; return;
emitUnaryopGPRFLoHi(Opcode, this, Func); emitUnaryopGPRFLoHi(Opcode, this, Func);
} }
template <> void InstMIPS32Mfhi::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mfhi(getDest());
}
template <> void InstMIPS32Mov_d::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Mov_d::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mov_d(getDest(), getSrc(0)); Asm->mov_d(getDest(), getSrc(0));
...@@ -981,12 +1003,27 @@ template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const { ...@@ -981,12 +1003,27 @@ template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const {
emitUnaryopGPRTLoHi(Opcode, this, Func); emitUnaryopGPRTLoHi(Opcode, this, Func);
} }
template <> void InstMIPS32Mtlo::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mtlo(getDest());
}
template <> void InstMIPS32Mthi::emit(const Cfg *Func) const { template <> void InstMIPS32Mthi::emit(const Cfg *Func) const {
if (!BuildDefs::dump()) if (!BuildDefs::dump())
return; return;
emitUnaryopGPRTLoHi(Opcode, this, Func); emitUnaryopGPRTLoHi(Opcode, this, Func);
} }
template <> void InstMIPS32Mthi::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mthi(getDest());
}
template <> void InstMIPS32Mul::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mul(getDest(), getSrc(0), getSrc(1));
}
template <> void InstMIPS32Mul_d::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Mul_d::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->mul_d(getDest(), getSrc(0), getSrc(1)); Asm->mul_d(getDest(), getSrc(0), getSrc(1));
...@@ -1009,6 +1046,11 @@ template <> void InstMIPS32Multu::emit(const Cfg *Func) const { ...@@ -1009,6 +1046,11 @@ template <> void InstMIPS32Multu::emit(const Cfg *Func) const {
emitThreeAddrLoHi(Opcode, this, Func); emitThreeAddrLoHi(Opcode, this, Func);
} }
template <> void InstMIPS32Multu::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->multu(getDest(), getSrc(0));
}
template <> void InstMIPS32Nor::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Nor::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->nor(getDest(), getSrc(0), getSrc(1)); Asm->nor(getDest(), getSrc(0), getSrc(1));
...@@ -1029,6 +1071,11 @@ template <> void InstMIPS32Sll::emitIAS(const Cfg *Func) const { ...@@ -1029,6 +1071,11 @@ template <> void InstMIPS32Sll::emitIAS(const Cfg *Func) const {
Asm->sll(getDest(), getSrc(0), Imm); Asm->sll(getDest(), getSrc(0), Imm);
} }
template <> void InstMIPS32Sllv::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->sllv(getDest(), getSrc(0), getSrc(1));
}
template <> void InstMIPS32Slt::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Slt::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->slt(getDest(), getSrc(0), getSrc(1)); Asm->slt(getDest(), getSrc(0), getSrc(1));
...@@ -1069,6 +1116,11 @@ template <> void InstMIPS32Srl::emitIAS(const Cfg *Func) const { ...@@ -1069,6 +1116,11 @@ template <> void InstMIPS32Srl::emitIAS(const Cfg *Func) const {
Asm->srl(getDest(), getSrc(0), Imm); Asm->srl(getDest(), getSrc(0), Imm);
} }
template <> void InstMIPS32Srlv::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->srlv(getDest(), getSrc(0), getSrc(1));
}
template <> void InstMIPS32Sub_d::emitIAS(const Cfg *Func) const { template <> void InstMIPS32Sub_d::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
Asm->sub_d(getDest(), getSrc(0), getSrc(1)); Asm->sub_d(getDest(), getSrc(0), getSrc(1));
......
src/IceInstMIPS32.h
...@@ -1267,13 +1267,16 @@ template <> void InstMIPS32Cvt_d_w::emitIAS(const Cfg *Func) const; ...@@ -1267,13 +1267,16 @@ template <> void InstMIPS32Cvt_d_w::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Cvt_s_d::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Cvt_s_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Cvt_s_l::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Cvt_s_l::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Cvt_s_w::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Cvt_s_w::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Div::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Div_d::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Div_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Div_s::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Div_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Lui::emit(const Cfg *Func) const; template <> void InstMIPS32Lui::emit(const Cfg *Func) const;
template <> void InstMIPS32Lw::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Lw::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mfc1::emit(const Cfg *Func) const; template <> void InstMIPS32Mfc1::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mflo::emit(const Cfg *Func) const; template <> void InstMIPS32Mflo::emit(const Cfg *Func) const;
template <> void InstMIPS32Mflo::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mfhi::emit(const Cfg *Func) const; template <> void InstMIPS32Mfhi::emit(const Cfg *Func) const;
template <> void InstMIPS32Mfhi::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mov_d::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Mov_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mov_s::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Mov_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Movf::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Movf::emitIAS(const Cfg *Func) const;
...@@ -1285,15 +1288,20 @@ template <> void InstMIPS32Movz_d::emitIAS(const Cfg *Func) const; ...@@ -1285,15 +1288,20 @@ template <> void InstMIPS32Movz_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Movz_s::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Movz_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mtc1::emit(const Cfg *Func) const; template <> void InstMIPS32Mtc1::emit(const Cfg *Func) const;
template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const; template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const;
template <> void InstMIPS32Mtlo::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mthi::emit(const Cfg *Func) const; template <> void InstMIPS32Mthi::emit(const Cfg *Func) const;
template <> void InstMIPS32Mthi::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mul::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mul_d::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Mul_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mul_s::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Mul_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Mult::emit(const Cfg *Func) const; template <> void InstMIPS32Mult::emit(const Cfg *Func) const;
template <> void InstMIPS32Multu::emit(const Cfg *Func) const; template <> void InstMIPS32Multu::emit(const Cfg *Func) const;
template <> void InstMIPS32Multu::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Nor::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Nor::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Or::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Or::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Ori::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Ori::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sll::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Sll::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sllv::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Slt::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Slt::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Slti::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Slti::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sltiu::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Sltiu::emitIAS(const Cfg *Func) const;
...@@ -1303,6 +1311,7 @@ template <> void InstMIPS32Sqrt_s::emitIAS(const Cfg *Func) const; ...@@ -1303,6 +1311,7 @@ template <> void InstMIPS32Sqrt_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sw::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Sw::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sra::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Sra::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Srl::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Srl::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Srlv::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sub_d::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Sub_d::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Sub_s::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Sub_s::emitIAS(const Cfg *Func) const;
template <> void InstMIPS32Subu::emitIAS(const Cfg *Func) const; template <> void InstMIPS32Subu::emitIAS(const Cfg *Func) const;
......
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