Add instruction 'adc (register)' to ARM integrated assembler.

src/IceAssemblerARM32.cpp

@@ -362,8 +362,22 @@ void AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
   switch (decodeOperand(OpSrc1, Src1Value)) {
   default:
     return setNeedsTextFixup();
+  case DecodedAsRegister: {
+    // ADC (register) - ARM section 18.8.2, encoding A1:
+    //   adc{s}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+    //
+    // cccc0000101snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
+    constexpr IValueT Imm5 = 0;
+    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
+    if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataRegister, Adc, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
   case DecodedAsRotatedImm8: {
-    // ADC (Immediated) = ARM section A8.8.1, encoding A1:
+    // ADC (Immediate) - ARM section A8.8.1, encoding A1:
     //   adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
     // cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
@@ -399,8 +413,9 @@ void AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
     //   add{s}<c> sp, <Rn>, <Rm>{, <shiff>}
     //
     // cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags
-    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, 0);
+    // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
+    constexpr IValueT Imm5 = 0;
+    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
     if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
       // Conditions of rule violated.
       return setNeedsTextFixup();

tests_lit/assembler/arm32/add.ll

@@ -96,3 +96,28 @@ define internal i64 @addI64ToR0R1(i64 %p) {
 ; IASM-NEXT:    .byte 0x10
 ; IASM-NEXT:    .byte 0xa1
 ; IASM-NEXT:    .byte 0xe2
+
+define internal i64 @AddI64Regs(i64 %p1, i64 %p2) {
+  %v = add i64 %p1, %p2
+  ret i64 %v
+}
+
+; ASM-LABEL:AddI64Regs:
+; ASM-NEXT:.LAddI64Regs$__0:
+; ASM-NEXT:     adds    r0, r0, r2
+; ASM-NEXT:     adc     r1, r1, r3
+
+; DIS-LABEL:00000030 <AddI64Regs>:
+; DIS-NEXT:  30:	e0900002
+; DIS-NEXT:  34:	e0a11003
+
+; IASM-LABEL:AddI64Regs:
+; IASM-NEXT:.LAddI64Regs$__0:
+; IASM-NEXT:    .byte 0x2
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0x90
+; IASM-NEXT:    .byte 0xe0
+; IASM-NEXT:    .byte 0x3
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0xa1
+; IASM-NEXT:    .byte 0xe0