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Commit 8072bae1 by Andrew Scull
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Refactor all instances of `typedef y x` to the C++11 `using x = y` syntax.

The C++11 syntax is more powerful as it also allows templating. This commit converts all type aliasing to the same syntax for consistency. BUG= R=jpp@chromium.org Review URL: https://codereview.chromium.org/1343843003 .
parent c31e2ed7
Showing with 174 additions and 173 deletions
src/IceAssemblerX86Base.h
......@@ -163,20 +163,20 @@ public:
}
// Operations to emit GPR instructions (and dispatch on operand type).
typedef void (AssemblerX86Base::*TypedEmitGPR)(Type,
typename Traits::GPRRegister);
typedef void (AssemblerX86Base::*TypedEmitAddr)(
Type, const typename Traits::Address &);
using TypedEmitGPR = void (AssemblerX86Base::*)(Type,
typename Traits::GPRRegister);
using TypedEmitAddr =
void (AssemblerX86Base::*)(Type, const typename Traits::Address &);
struct GPREmitterOneOp {
TypedEmitGPR Reg;
TypedEmitAddr Addr;
};
typedef void (AssemblerX86Base::*TypedEmitGPRGPR)(
using TypedEmitGPRGPR = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, typename Traits::GPRRegister);
typedef void (AssemblerX86Base::*TypedEmitGPRAddr)(
using TypedEmitGPRAddr = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, const typename Traits::Address &);
typedef void (AssemblerX86Base::*TypedEmitGPRImm)(
using TypedEmitGPRImm = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, const Immediate &);
struct GPREmitterRegOp {
TypedEmitGPRGPR GPRGPR;
......@@ -191,7 +191,7 @@ public:
TypedEmitGPRImm GPRImm;
};
typedef void (AssemblerX86Base::*TypedEmitGPRGPRImm)(
using TypedEmitGPRGPRImm = void (AssemblerX86Base::*)(
Type, typename Traits::GPRRegister, typename Traits::GPRRegister,
const Immediate &);
struct GPREmitterShiftD {
......@@ -201,9 +201,9 @@ public:
TypedEmitGPRGPRImm GPRGPRImm;
};
typedef void (AssemblerX86Base::*TypedEmitAddrGPR)(
using TypedEmitAddrGPR = void (AssemblerX86Base::*)(
Type, const typename Traits::Address &, typename Traits::GPRRegister);
typedef void (AssemblerX86Base::*TypedEmitAddrImm)(
using TypedEmitAddrImm = void (AssemblerX86Base::*)(
Type, const typename Traits::Address &, const Immediate &);
struct GPREmitterAddrOp {
TypedEmitAddrGPR AddrGPR;
......@@ -211,20 +211,20 @@ public:
};
// Operations to emit XMM instructions (and dispatch on operand type).
typedef void (AssemblerX86Base::*TypedEmitXmmXmm)(
using TypedEmitXmmXmm = void (AssemblerX86Base::*)(
Type, typename Traits::XmmRegister, typename Traits::XmmRegister);
typedef void (AssemblerX86Base::*TypedEmitXmmAddr)(
using TypedEmitXmmAddr = void (AssemblerX86Base::*)(
Type, typename Traits::XmmRegister, const typename Traits::Address &);
struct XmmEmitterRegOp {
TypedEmitXmmXmm XmmXmm;
TypedEmitXmmAddr XmmAddr;
};
typedef void (AssemblerX86Base::*EmitXmmXmm)(typename Traits::XmmRegister,
typename Traits::XmmRegister);
typedef void (AssemblerX86Base::*EmitXmmAddr)(
using EmitXmmXmm = void (AssemblerX86Base::*)(typename Traits::XmmRegister,
typename Traits::XmmRegister);
using EmitXmmAddr = void (AssemblerX86Base::*)(
typename Traits::XmmRegister, const typename Traits::Address &);
typedef void (AssemblerX86Base::*EmitAddrXmm)(
using EmitAddrXmm = void (AssemblerX86Base::*)(
const typename Traits::Address &, typename Traits::XmmRegister);
struct XmmEmitterMovOps {
EmitXmmXmm XmmXmm;
......@@ -232,7 +232,7 @@ public:
EmitAddrXmm AddrXmm;
};
typedef void (AssemblerX86Base::*TypedEmitXmmImm)(
using TypedEmitXmmImm = void (AssemblerX86Base::*)(
Type, typename Traits::XmmRegister, const Immediate &);
struct XmmEmitterShiftOp {
......@@ -243,8 +243,9 @@ public:
// Cross Xmm/GPR cast instructions.
template <typename DReg_t, typename SReg_t> struct CastEmitterRegOp {
typedef void (AssemblerX86Base::*TypedEmitRegs)(Type, DReg_t, Type, SReg_t);
typedef void (AssemblerX86Base::*TypedEmitAddr)(
using TypedEmitRegs = void (AssemblerX86Base::*)(Type, DReg_t, Type,
SReg_t);
using TypedEmitAddr = void (AssemblerX86Base::*)(
Type, DReg_t, Type, const typename Traits::Address &);
TypedEmitRegs RegReg;
......@@ -254,9 +255,9 @@ public:
// Three operand (potentially) cross Xmm/GPR instructions.
// The last operand must be an immediate.
template <typename DReg_t, typename SReg_t> struct ThreeOpImmEmitter {
typedef void (AssemblerX86Base::*TypedEmitRegRegImm)(Type, DReg_t, SReg_t,
const Immediate &);
typedef void (AssemblerX86Base::*TypedEmitRegAddrImm)(
using TypedEmitRegRegImm = void (AssemblerX86Base::*)(Type, DReg_t, SReg_t,
const Immediate &);
using TypedEmitRegAddrImm = void (AssemblerX86Base::*)(
Type, DReg_t, const typename Traits::Address &, const Immediate &);
TypedEmitRegRegImm RegRegImm;
......@@ -897,7 +898,7 @@ private:
const typename Traits::Operand &operand,
typename Traits::GPRRegister shifter);
typedef std::vector<Label *> LabelVector;
using LabelVector = std::vector<Label *>;
// A vector of pool-allocated x86 labels for CFG nodes.
LabelVector CfgNodeLabels;
// A vector of pool-allocated x86 labels for Local labels.
......
src/IceCfg.cpp
......@@ -311,7 +311,7 @@ void Cfg::advancedPhiLowering() {
void Cfg::reorderNodes() {
// TODO(ascull): it would be nice if the switch tests were always followed
// by the default case to allow for fall through.
typedef std::list<CfgNode *> PlacedList;
using PlacedList = std::list<CfgNode *>;
PlacedList Placed; // Nodes with relative placement locked down
PlacedList Unreachable; // Unreachable nodes
PlacedList::iterator NoPlace = Placed.end();
......
src/IceCfg.h
......@@ -96,7 +96,7 @@ public:
void swapNodes(NodeList &NewNodes);
/// @}
typedef int32_t IdentifierIndexType;
using IdentifierIndexType = int32_t;
/// Adds a name to the list and returns its index, suitable for the
/// argument to getIdentifierName(). No checking for duplicates is
/// done. This is generally used for node names and variable names
......
src/IceConverter.h
......@@ -48,8 +48,8 @@ public:
private:
llvm::Module *Mod;
typedef std::map<const llvm::GlobalValue *, GlobalDeclaration *>
GlobalDeclarationMapType;
using GlobalDeclarationMapType =
std::map<const llvm::GlobalValue *, GlobalDeclaration *>;
GlobalDeclarationMapType GlobalDeclarationMap;
/// Walks module and generates names for unnamed globals using prefix
......
src/IceDefs.h
......@@ -138,42 +138,42 @@ static std::unique_ptr<T> makeUnique(Args &&... TheArgs) {
#define ENABLE_MAKE_UNIQUE friend struct ::Ice::Internal::MakeUniqueEnabler
typedef std::string IceString;
typedef llvm::ilist<Inst> InstList;
using IceString = std::string;
using InstList = llvm::ilist<Inst>;
// Ideally PhiList would be llvm::ilist<InstPhi>, and similar for
// AssignList, but this runs into issues with SFINAE.
typedef InstList PhiList;
typedef InstList AssignList;
using PhiList = InstList;
using AssignList = InstList;
// Containers that are arena-allocated from the Cfg's allocator.
typedef std::vector<Operand *, CfgLocalAllocator<Operand *>> OperandList;
typedef std::vector<Variable *, CfgLocalAllocator<Variable *>> VarList;
typedef std::vector<CfgNode *, CfgLocalAllocator<CfgNode *>> NodeList;
using OperandList = std::vector<Operand *, CfgLocalAllocator<Operand *>>;
using VarList = std::vector<Variable *, CfgLocalAllocator<Variable *>>;
using NodeList = std::vector<CfgNode *, CfgLocalAllocator<CfgNode *>>;
// Contains that use the default (global) allocator.
typedef std::vector<Constant *> ConstantList;
typedef std::vector<FunctionDeclaration *> FunctionDeclarationList;
typedef std::vector<VariableDeclaration *> VariableDeclarationList;
using ConstantList = std::vector<Constant *>;
using FunctionDeclarationList = std::vector<FunctionDeclaration *>;
using VariableDeclarationList = std::vector<VariableDeclaration *>;
/// SizeT is for holding small-ish limits like number of source
/// operands in an instruction. It is used instead of size_t (which
/// may be 64-bits wide) when we want to save space.
typedef uint32_t SizeT;
using SizeT = uint32_t;
/// InstNumberT is for holding an instruction number. Instruction
/// numbers are used for representing Variable live ranges.
typedef int32_t InstNumberT;
using InstNumberT = int32_t;
/// A LiveBeginEndMapEntry maps a Variable::Number value to an
/// Inst::Number value, giving the instruction number that begins or
/// ends a variable's live range.
typedef std::pair<SizeT, InstNumberT> LiveBeginEndMapEntry;
typedef std::vector<LiveBeginEndMapEntry,
CfgLocalAllocator<LiveBeginEndMapEntry>> LiveBeginEndMap;
typedef llvm::BitVector LivenessBV;
using LiveBeginEndMapEntry = std::pair<SizeT, InstNumberT>;
using LiveBeginEndMap =
std::vector<LiveBeginEndMapEntry, CfgLocalAllocator<LiveBeginEndMapEntry>>;
using LivenessBV = llvm::BitVector;
typedef uint32_t TimerStackIdT;
typedef uint32_t TimerIdT;
using TimerStackIdT = uint32_t;
using TimerIdT = uint32_t;
/// Use alignas(MaxCacheLineSize) to isolate variables/fields that
/// might be contended while multithreading. Assumes the maximum cache
......@@ -187,7 +187,7 @@ enum { MaxCacheLineSize = 64 };
__attribute__((aligned(MaxCacheLineSize + 0))) int : 0
/// PNaCl is ILP32, so theoretically we should only need 32-bit offsets.
typedef int32_t RelocOffsetT;
using RelocOffsetT = int32_t;
enum { RelocAddrSize = 4 };
enum LivenessMode {
......@@ -229,7 +229,7 @@ enum VerboseItem {
IceV_All = ~IceV_None,
IceV_Most = IceV_All & ~IceV_LinearScan
};
typedef uint32_t VerboseMask;
using VerboseMask = uint32_t;
enum FileType {
FT_Elf, /// ELF .o file
......@@ -237,10 +237,10 @@ enum FileType {
FT_Iasm /// "Integrated assembler" .byte-style .s file
};
typedef llvm::raw_ostream Ostream;
typedef llvm::raw_fd_ostream Fdstream;
using Ostream = llvm::raw_ostream;
using Fdstream = llvm::raw_fd_ostream;
typedef std::mutex GlobalLockType;
using GlobalLockType = std::mutex;
enum ErrorCodes { EC_None = 0, EC_Args, EC_Bitcode, EC_Translation };
......
src/IceELFObjectWriter.h
......@@ -97,10 +97,10 @@ private:
bool ELF64;
// All created sections, separated into different pools.
typedef std::vector<ELFSection *> SectionList;
typedef std::vector<ELFTextSection *> TextSectionList;
typedef std::vector<ELFDataSection *> DataSectionList;
typedef std::vector<ELFRelocationSection *> RelSectionList;
using SectionList = std::vector<ELFSection *>;
using TextSectionList = std::vector<ELFTextSection *>;
using DataSectionList = std::vector<ELFDataSection *>;
using RelSectionList = std::vector<ELFRelocationSection *>;
TextSectionList TextSections;
RelSectionList RelTextSections;
DataSectionList DataSections;
......
src/IceELFSection.h
......@@ -200,8 +200,8 @@ public:
private:
// Map from symbol name to its symbol information.
// This assumes symbols are unique across all sections.
typedef IceString SymtabKey;
typedef std::map<SymtabKey, ELFSym> SymMap;
using SymtabKey = IceString;
using SymMap = std::map<SymtabKey, ELFSym>;
template <bool IsELF64>
void writeSymbolMap(ELFStreamer &Str, const SymMap &Map);
......@@ -299,13 +299,13 @@ private:
bool operator()(const IceString &StrA, const IceString &StrB) const;
};
typedef std::map<IceString, size_t, SuffixComparator> StringToIndexType;
using StringToIndexType = std::map<IceString, size_t, SuffixComparator>;
/// Track strings to their index. Index will be UnknownIndex if not
/// yet laid out.
StringToIndexType StringToIndexMap;
typedef std::vector<uint8_t> RawDataType;
using RawDataType = std::vector<uint8_t>;
RawDataType StringData;
};
......
src/IceFixups.h
......@@ -21,7 +21,7 @@ namespace Ice {
/// Each target and container format has a different namespace of relocations.
/// This holds the specific target+container format's relocation number.
typedef uint32_t FixupKind;
using FixupKind = uint32_t;
/// Assembler fixups are positions in generated code/data that hold relocation
/// information that needs to be processed before finalizing the code/data.
......@@ -53,8 +53,8 @@ private:
const Constant *value_ = nullptr;
};
typedef std::vector<AssemblerFixup> FixupList;
typedef std::vector<AssemblerFixup *> FixupRefList;
using FixupList = std::vector<AssemblerFixup>;
using FixupRefList = std::vector<AssemblerFixup *>;
} // end of namespace Ice
......
src/IceGlobalContext.cpp
......@@ -80,7 +80,7 @@ struct KeyCompareLess<ValueType,
typename std::enable_if<std::is_floating_point<
typename ValueType::PrimType>::value>::type> {
bool operator()(const Constant *Const1, const Constant *Const2) const {
typedef uint64_t CompareType;
using CompareType = uint64_t;
static_assert(sizeof(typename ValueType::PrimType) <= sizeof(CompareType),
"Expected floating-point type of width 64-bit or less");
typename ValueType::PrimType V1 = llvm::cast<ValueType>(Const1)->getValue();
......@@ -139,23 +139,23 @@ public:
Constants.reserve(Pool.size());
for (auto &I : Pool)
Constants.push_back(I.second);
// The sort (and its KeyCompareLess machinery) is not strictly
// necessary, but is desirable for producing output that is
// deterministic across unordered_map::iterator implementations.
// The sort (and its KeyCompareLess machinery) is not strictly necessary,
// but is desirable for producing output that is deterministic across
// unordered_map::iterator implementations.
std::sort(Constants.begin(), Constants.end(), KeyCompareLess<ValueType>());
return Constants;
}
private:
// Use the default hash function, and a custom key comparison
// function. The key comparison function for floating point
// variables can't use the default == based implementation because
// of special C++ semantics regarding +0.0, -0.0, and NaN
// comparison. However, it's OK to use the default hash for
// floating point values because KeyCompare is the final source of
// truth - in the worst case a "false" collision must be resolved.
typedef std::unordered_map<KeyType, ValueType *, std::hash<KeyType>,
KeyCompare<KeyType>> ContainerType;
// Use the default hash function, and a custom key comparison function. The
// key comparison function for floating point variables can't use the default
// == based implementation because of special C++ semantics regarding +0.0,
// -0.0, and NaN comparison. However, it's OK to use the default hash for
// floating point values because KeyCompare is the final source of truth - in
// the worst case a "false" collision must be resolved.
using ContainerType =
std::unordered_map<KeyType, ValueType *, std::hash<KeyType>,
KeyCompare<KeyType>>;
ContainerType Pool;
uint32_t NextPoolID = 0;
};
......
src/IceGlobalContext.h
......@@ -447,7 +447,7 @@ private:
ICE_CACHELINE_BOUNDARY;
// Managed by getDestructors()
typedef std::vector<std::function<void()>> DestructorArray;
using DestructorArray = std::vector<std::function<void()>>;
GlobalLockType DestructorsLock;
DestructorArray Destructors;
......@@ -478,7 +478,7 @@ private:
ICE_CACHELINE_BOUNDARY;
/// StrLock is a global lock on the dump and emit output streams.
typedef std::mutex StrLockType;
using StrLockType = std::mutex;
StrLockType StrLock;
Ostream *StrDump; /// Stream for dumping / diagnostics
Ostream *StrEmit; /// Stream for code emission
......@@ -545,7 +545,7 @@ private:
ICE_TLS_DECLARE_FIELD(ThreadContext *, TLS);
// Private helpers for mangleName()
typedef llvm::SmallVector<char, 32> ManglerVector;
using ManglerVector = llvm::SmallVector<char, 32>;
void incrementSubstitutions(ManglerVector &OldName) const;
public:
......
src/IceGlobalInits.h
......@@ -172,7 +172,7 @@ public:
};
/// Models the data in a data initializer.
typedef std::vector<char> DataVecType;
using DataVecType = std::vector<char>;
/// Defines a sequence of byte values as a data initializer.
class DataInitializer : public Initializer {
......@@ -269,7 +269,7 @@ public:
};
/// Models the list of initializers.
typedef std::vector<std::unique_ptr<Initializer>> InitializerListType;
using InitializerListType = std::vector<std::unique_ptr<Initializer>>;
static VariableDeclaration *create(GlobalContext *Context) {
return new (Context->allocate<VariableDeclaration>()) VariableDeclaration();
......
src/IceInst.h
......@@ -215,7 +215,7 @@ protected:
/// mapped to one bit position of the LiveRangesEnded bit vector.
/// Only the first CHAR_BIT * sizeof(LREndedBits) variables are
/// tracked this way.
typedef uint32_t LREndedBits; // only first 32 src operands tracked, sorry
using LREndedBits = uint32_t; // only first 32 src operands tracked, sorry
LREndedBits LiveRangesEnded;
};
......
src/IceInstARM32.h
......@@ -759,52 +759,52 @@ private:
static const char *Opcode;
};
typedef InstARM32ThreeAddrGPR<InstARM32::Adc> InstARM32Adc;
typedef InstARM32ThreeAddrGPR<InstARM32::Add> InstARM32Add;
typedef InstARM32ThreeAddrGPR<InstARM32::And> InstARM32And;
typedef InstARM32ThreeAddrGPR<InstARM32::Asr> InstARM32Asr;
typedef InstARM32ThreeAddrGPR<InstARM32::Bic> InstARM32Bic;
typedef InstARM32ThreeAddrGPR<InstARM32::Eor> InstARM32Eor;
typedef InstARM32ThreeAddrGPR<InstARM32::Lsl> InstARM32Lsl;
typedef InstARM32ThreeAddrGPR<InstARM32::Lsr> InstARM32Lsr;
typedef InstARM32ThreeAddrGPR<InstARM32::Mul> InstARM32Mul;
typedef InstARM32ThreeAddrGPR<InstARM32::Orr> InstARM32Orr;
typedef InstARM32ThreeAddrGPR<InstARM32::Rsb> InstARM32Rsb;
typedef InstARM32ThreeAddrGPR<InstARM32::Sbc> InstARM32Sbc;
typedef InstARM32ThreeAddrGPR<InstARM32::Sdiv> InstARM32Sdiv;
typedef InstARM32ThreeAddrGPR<InstARM32::Sub> InstARM32Sub;
typedef InstARM32ThreeAddrGPR<InstARM32::Udiv> InstARM32Udiv;
typedef InstARM32ThreeAddrFP<InstARM32::Vadd> InstARM32Vadd;
typedef InstARM32ThreeAddrFP<InstARM32::Vdiv> InstARM32Vdiv;
typedef InstARM32ThreeAddrFP<InstARM32::Vmul> InstARM32Vmul;
typedef InstARM32ThreeAddrFP<InstARM32::Vsub> InstARM32Vsub;
typedef InstARM32Movlike<InstARM32::Ldr> InstARM32Ldr;
using InstARM32Adc = InstARM32ThreeAddrGPR<InstARM32::Adc>;
using InstARM32Add = InstARM32ThreeAddrGPR<InstARM32::Add>;
using InstARM32And = InstARM32ThreeAddrGPR<InstARM32::And>;
using InstARM32Asr = InstARM32ThreeAddrGPR<InstARM32::Asr>;
using InstARM32Bic = InstARM32ThreeAddrGPR<InstARM32::Bic>;
using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
using InstARM32Lsl = InstARM32ThreeAddrGPR<InstARM32::Lsl>;
using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
using InstARM32Mul = InstARM32ThreeAddrGPR<InstARM32::Mul>;
using InstARM32Orr = InstARM32ThreeAddrGPR<InstARM32::Orr>;
using InstARM32Rsb = InstARM32ThreeAddrGPR<InstARM32::Rsb>;
using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
using InstARM32Sdiv = InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
using InstARM32Sub = InstARM32ThreeAddrGPR<InstARM32::Sub>;
using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
using InstARM32Ldr = InstARM32Movlike<InstARM32::Ldr>;
/// Move instruction (variable <- flex). This is more of a pseudo-inst.
/// If var is a register, then we use "mov". If var is stack, then we use
/// "str" to store to the stack.
typedef InstARM32Movlike<InstARM32::Mov> InstARM32Mov;
using InstARM32Mov = InstARM32Movlike<InstARM32::Mov>;
/// Represents various vector mov instruction forms (simple single source,
/// single dest forms only, not the 2 GPR <-> 1 D reg forms, etc.).
typedef InstARM32Movlike<InstARM32::Vmov> InstARM32Vmov;
typedef InstARM32Movlike<InstARM32::Vldr> InstARM32Vldr;
using InstARM32Vmov = InstARM32Movlike<InstARM32::Vmov>;
using InstARM32Vldr = InstARM32Movlike<InstARM32::Vldr>;
/// MovT leaves the bottom bits alone so dest is also a source.
/// This helps indicate that a previous MovW setting dest is not dead code.
typedef InstARM32TwoAddrGPR<InstARM32::Movt> InstARM32Movt;
typedef InstARM32UnaryopGPR<InstARM32::Movw, false> InstARM32Movw;
typedef InstARM32UnaryopGPR<InstARM32::Clz, false> InstARM32Clz;
typedef InstARM32UnaryopGPR<InstARM32::Mvn, false> InstARM32Mvn;
typedef InstARM32UnaryopGPR<InstARM32::Rbit, false> InstARM32Rbit;
typedef InstARM32UnaryopGPR<InstARM32::Rev, false> InstARM32Rev;
using InstARM32Movt = InstARM32TwoAddrGPR<InstARM32::Movt>;
using InstARM32Movw = InstARM32UnaryopGPR<InstARM32::Movw, false>;
using InstARM32Clz = InstARM32UnaryopGPR<InstARM32::Clz, false>;
using InstARM32Mvn = InstARM32UnaryopGPR<InstARM32::Mvn, false>;
using InstARM32Rbit = InstARM32UnaryopGPR<InstARM32::Rbit, false>;
using InstARM32Rev = InstARM32UnaryopGPR<InstARM32::Rev, false>;
// Technically, the uxt{b,h} and sxt{b,h} instructions have a rotation
// operand as well (rotate source by 8, 16, 24 bits prior to extending),
// but we aren't using that for now, so just model as a Unaryop.
typedef InstARM32UnaryopGPR<InstARM32::Sxt, true> InstARM32Sxt;
typedef InstARM32UnaryopGPR<InstARM32::Uxt, true> InstARM32Uxt;
typedef InstARM32UnaryopFP<InstARM32::Vsqrt> InstARM32Vsqrt;
typedef InstARM32FourAddrGPR<InstARM32::Mla> InstARM32Mla;
typedef InstARM32FourAddrGPR<InstARM32::Mls> InstARM32Mls;
typedef InstARM32CmpLike<InstARM32::Cmp> InstARM32Cmp;
typedef InstARM32CmpLike<InstARM32::Tst> InstARM32Tst;
using InstARM32Sxt = InstARM32UnaryopGPR<InstARM32::Sxt, true>;
using InstARM32Uxt = InstARM32UnaryopGPR<InstARM32::Uxt, true>;
using InstARM32Vsqrt = InstARM32UnaryopFP<InstARM32::Vsqrt>;
using InstARM32Mla = InstARM32FourAddrGPR<InstARM32::Mla>;
using InstARM32Mls = InstARM32FourAddrGPR<InstARM32::Mls>;
using InstARM32Cmp = InstARM32CmpLike<InstARM32::Cmp>;
using InstARM32Tst = InstARM32CmpLike<InstARM32::Tst>;
// InstARM32Label represents an intra-block label that is the target
// of an intra-block branch. The offset between the label and the
......
src/IceInstX86Base.h
......@@ -2496,7 +2496,7 @@ template <class Machine> class InstX86Nop final : public InstX86Base<Machine> {
public:
// TODO: Replace with enum.
typedef unsigned NopVariant;
using NopVariant = unsigned;
static InstX86Nop *create(Cfg *Func, NopVariant Variant) {
return new (Func->allocate<InstX86Nop>()) InstX86Nop(Func, Variant);
......
src/IceIntrinsics.h
......@@ -165,7 +165,7 @@ public:
private:
// TODO(jvoung): May want to switch to something like LLVM's StringMap.
typedef std::map<IceString, FullIntrinsicInfo> IntrinsicMap;
using IntrinsicMap = std::map<IceString, FullIntrinsicInfo>;
IntrinsicMap Map;
};
......
src/IceOperand.h
......@@ -159,7 +159,7 @@ class ConstantPrimitive : public Constant {
ConstantPrimitive &operator=(const ConstantPrimitive &) = delete;
public:
typedef T PrimType;
using PrimType = T;
static ConstantPrimitive *create(GlobalContext *Ctx, Type Ty, PrimType Value,
uint32_t PoolEntryID) {
......@@ -192,10 +192,10 @@ private:
const PrimType Value;
};
typedef ConstantPrimitive<int32_t, Operand::kConstInteger32> ConstantInteger32;
typedef ConstantPrimitive<int64_t, Operand::kConstInteger64> ConstantInteger64;
typedef ConstantPrimitive<float, Operand::kConstFloat> ConstantFloat;
typedef ConstantPrimitive<double, Operand::kConstDouble> ConstantDouble;
using ConstantInteger32 = ConstantPrimitive<int32_t, Operand::kConstInteger32>;
using ConstantInteger64 = ConstantPrimitive<int64_t, Operand::kConstInteger64>;
using ConstantFloat = ConstantPrimitive<float, Operand::kConstFloat>;
using ConstantDouble = ConstantPrimitive<double, Operand::kConstDouble>;
template <>
inline void ConstantInteger32::dump(const Cfg *, Ostream &Str) const {
......@@ -387,10 +387,10 @@ public:
void dump(Ostream &Str) const;
private:
typedef std::pair<InstNumberT, InstNumberT> RangeElementType;
using RangeElementType = std::pair<InstNumberT, InstNumberT>;
/// RangeType is arena-allocated from the Cfg's allocator.
typedef std::vector<RangeElementType, CfgLocalAllocator<RangeElementType>>
RangeType;
using RangeType =
std::vector<RangeElementType, CfgLocalAllocator<RangeElementType>>;
RangeType Range;
/// TrimmedBegin is an optimization for the overlaps() computation.
/// Since the linear-scan algorithm always calls it as overlaps(Cur)
......@@ -560,7 +560,7 @@ enum MetadataKind {
VMK_SingleDefs, /// Track uses+defs, but only record single def
VMK_All /// Track uses+defs, including full def list
};
typedef std::vector<const Inst *, CfgLocalAllocator<const Inst *>> InstDefList;
using InstDefList = std::vector<const Inst *, CfgLocalAllocator<const Inst *>>;
/// VariableTracking tracks the metadata for a single variable. It is
/// only meant to be used internally by VariablesMetadata.
......
src/IceRegAlloc.h
......@@ -39,8 +39,8 @@ public:
static constexpr size_t REGS_SIZE = 32;
private:
typedef std::vector<Variable *> OrderedRanges;
typedef std::vector<Variable *> UnorderedRanges;
using OrderedRanges = std::vector<Variable *>;
using UnorderedRanges = std::vector<Variable *>;
class IterationState {
IterationState(const IterationState &) = delete;
......
src/IceSwitchLowering.h
......@@ -20,8 +20,8 @@ namespace Ice {
class CaseCluster;
typedef std::vector<CaseCluster, CfgLocalAllocator<CaseCluster>>
CaseClusterArray;
using CaseClusterArray =
std::vector<CaseCluster, CfgLocalAllocator<CaseCluster>>;
/// A cluster of cases can be tested by a common method during switch lowering.
class CaseCluster {
......
src/IceTLS.h
......@@ -67,7 +67,7 @@
#include <pthread.h>
#define ICE_TLS_DECLARE_FIELD(Type, FieldName) \
typedef Type FieldName##__type; \
using FieldName##__type = Type; \
static pthread_key_t FieldName##__key; \
static int FieldName##__initStatus
#define ICE_TLS_DEFINE_FIELD(Type, ClassName, FieldName) \
......
src/IceTargetLowering.h
......@@ -206,7 +206,7 @@ public:
RegSet_FramePointer = 1 << 3,
RegSet_All = ~RegSet_None
};
typedef uint32_t RegSetMask;
using RegSetMask = uint32_t;
virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
RegSetMask Exclude) const = 0;
......
src/IceTargetLoweringARM32.h
......@@ -152,7 +152,7 @@ protected:
Legal_Mem = 1 << 2, /// includes [r0, r1 lsl #2] as well as [sp, #12]
Legal_All = ~Legal_None
};
typedef uint32_t LegalMask;
using LegalMask = uint32_t;
Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
int32_t RegNum = Variable::NoRegister);
Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
......@@ -175,10 +175,10 @@ protected:
// test; branch .LSKIP; trap; .LSKIP: <continuation>.
// If no check is needed nothing is inserted.
void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
typedef void (TargetARM32::*ExtInstr)(Variable *, Variable *,
CondARM32::Cond);
typedef void (TargetARM32::*DivInstr)(Variable *, Variable *, Variable *,
CondARM32::Cond);
using ExtInstr = void (TargetARM32::*)(Variable *, Variable *,
CondARM32::Cond);
using DivInstr = void (TargetARM32::*)(Variable *, Variable *, Variable *,
CondARM32::Cond);
void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1,
ExtInstr ExtFunc, DivInstr DivFunc,
const char *DivHelperName, bool IsRemainder);
......
src/IceTargetLoweringX8632.cpp
......@@ -120,7 +120,7 @@ void TargetX8632::lowerCall(const InstCall *Instr) {
// Apple.
NeedsStackAlignment = true;
typedef std::vector<Operand *> OperandList;
using OperandList = std::vector<Operand *>;
OperandList XmmArgs;
OperandList StackArgs, StackArgLocations;
uint32_t ParameterAreaSizeBytes = 0;
......@@ -653,8 +653,8 @@ namespace {
template <typename T> struct PoolTypeConverter {};
template <> struct PoolTypeConverter<float> {
typedef uint32_t PrimitiveIntType;
typedef ConstantFloat IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantFloat;
static const Type Ty = IceType_f32;
static const char *TypeName;
static const char *AsmTag;
......@@ -665,8 +665,8 @@ const char *PoolTypeConverter<float>::AsmTag = ".long";
const char *PoolTypeConverter<float>::PrintfString = "0x%x";
template <> struct PoolTypeConverter<double> {
typedef uint64_t PrimitiveIntType;
typedef ConstantDouble IceType;
using PrimitiveIntType = uint64_t;
using IceType = ConstantDouble;
static const Type Ty = IceType_f64;
static const char *TypeName;
static const char *AsmTag;
......@@ -678,8 +678,8 @@ const char *PoolTypeConverter<double>::PrintfString = "0x%llx";
// Add converter for int type constant pooling
template <> struct PoolTypeConverter<uint32_t> {
typedef uint32_t PrimitiveIntType;
typedef ConstantInteger32 IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantInteger32;
static const Type Ty = IceType_i32;
static const char *TypeName;
static const char *AsmTag;
......@@ -691,8 +691,8 @@ const char *PoolTypeConverter<uint32_t>::PrintfString = "0x%x";
// Add converter for int type constant pooling
template <> struct PoolTypeConverter<uint16_t> {
typedef uint32_t PrimitiveIntType;
typedef ConstantInteger32 IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantInteger32;
static const Type Ty = IceType_i16;
static const char *TypeName;
static const char *AsmTag;
......@@ -704,8 +704,8 @@ const char *PoolTypeConverter<uint16_t>::PrintfString = "0x%x";
// Add converter for int type constant pooling
template <> struct PoolTypeConverter<uint8_t> {
typedef uint32_t PrimitiveIntType;
typedef ConstantInteger32 IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantInteger32;
static const Type Ty = IceType_i8;
static const char *TypeName;
static const char *AsmTag;
......
src/IceTargetLoweringX8632Traits.h
......@@ -396,8 +396,8 @@ template <> struct MachineTraits<TargetX8632> {
// class. For x86-32, this would comprise the 8 XMM registers. This is for
// performance, not correctness.
static const unsigned MaxEquivalenceClassSize = 8;
typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
typedef std::map<uint32_t, RegisterList> EquivalenceClassMap;
using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>;
using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
EquivalenceClassMap EquivalenceClasses;
SizeT NumShuffled = 0, NumPreserved = 0;
......
src/IceTargetLoweringX8664.cpp
......@@ -665,8 +665,8 @@ namespace {
template <typename T> struct PoolTypeConverter {};
template <> struct PoolTypeConverter<float> {
typedef uint32_t PrimitiveIntType;
typedef ConstantFloat IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantFloat;
static const Type Ty = IceType_f32;
static const char *TypeName;
static const char *AsmTag;
......@@ -677,8 +677,8 @@ const char *PoolTypeConverter<float>::AsmTag = ".long";
const char *PoolTypeConverter<float>::PrintfString = "0x%x";
template <> struct PoolTypeConverter<double> {
typedef uint64_t PrimitiveIntType;
typedef ConstantDouble IceType;
using PrimitiveIntType = uint64_t;
using IceType = ConstantDouble;
static const Type Ty = IceType_f64;
static const char *TypeName;
static const char *AsmTag;
......@@ -690,8 +690,8 @@ const char *PoolTypeConverter<double>::PrintfString = "0x%llx";
// Add converter for int type constant pooling
template <> struct PoolTypeConverter<uint32_t> {
typedef uint32_t PrimitiveIntType;
typedef ConstantInteger32 IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantInteger32;
static const Type Ty = IceType_i32;
static const char *TypeName;
static const char *AsmTag;
......@@ -703,8 +703,8 @@ const char *PoolTypeConverter<uint32_t>::PrintfString = "0x%x";
// Add converter for int type constant pooling
template <> struct PoolTypeConverter<uint16_t> {
typedef uint32_t PrimitiveIntType;
typedef ConstantInteger32 IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantInteger32;
static const Type Ty = IceType_i16;
static const char *TypeName;
static const char *AsmTag;
......@@ -716,8 +716,8 @@ const char *PoolTypeConverter<uint16_t>::PrintfString = "0x%x";
// Add converter for int type constant pooling
template <> struct PoolTypeConverter<uint8_t> {
typedef uint32_t PrimitiveIntType;
typedef ConstantInteger32 IceType;
using PrimitiveIntType = uint32_t;
using IceType = ConstantInteger32;
static const Type Ty = IceType_i8;
static const char *TypeName;
static const char *AsmTag;
......
src/IceTargetLoweringX8664Traits.h
......@@ -410,8 +410,8 @@ template <> struct MachineTraits<TargetX8664> {
// class. For x86-64, this would comprise the 16 XMM registers. This is
// for performance, not correctness.
static const unsigned MaxEquivalenceClassSize = 8;
typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
typedef std::map<uint32_t, RegisterList> EquivalenceClassMap;
using RegisterList = llvm::SmallVector<int32_t, MaxEquivalenceClassSize>;
using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
EquivalenceClassMap EquivalenceClasses;
SizeT NumShuffled = 0, NumPreserved = 0;
......
src/IceTargetLoweringX86Base.h
......@@ -229,7 +229,7 @@ protected:
void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp,
CfgNode *DefaultLabel = nullptr);
typedef void (TargetX86Base::*LowerBinOp)(Variable *, Operand *);
using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *);
void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi,
Variable *Dest, Operand *Ptr, Operand *Val);
......@@ -252,7 +252,7 @@ protected:
Legal_Mem = 1 << 2, // includes [eax+4*ecx] as well as [esp+12]
Legal_All = ~Legal_None
};
typedef uint32_t LegalMask;
using LegalMask = uint32_t;
Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
int32_t RegNum = Variable::NoRegister);
Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
......
src/IceTimerTree.cpp
......@@ -220,7 +220,7 @@ void TimerStack::reset() {
namespace {
typedef std::multimap<double, IceString> DumpMapType;
using DumpMapType = std::multimap<double, IceString>;
// Dump the Map items in reverse order of their time contribution.
void dumpHelper(Ostream &Str, const DumpMapType &Map, double TotalTime) {
......
src/IceTimerTree.h
......@@ -28,14 +28,14 @@ class TimerStack {
/// Timer tree index type. A variable of this type is used to access
/// an interior, not-necessarily-leaf node of the tree.
typedef std::vector<class TimerTreeNode>::size_type TTindex;
using TTindex = std::vector<class TimerTreeNode>::size_type;
/// Representation of a path of leaf values leading to a particular
/// node. The representation happens to be in "reverse" order,
/// i.e. from leaf/interior to root, for implementation efficiency.
typedef llvm::SmallVector<TTindex, 8> PathType;
using PathType = llvm::SmallVector<TTindex, 8>;
/// Representation of a mapping of leaf node indexes from one timer
/// stack to another.
typedef std::vector<TimerIdT> TranslationType;
using TranslationType = std::vector<TimerIdT>;
/// TimerTreeNode represents an interior or leaf node in the call tree.
/// It contains a list of children, a pointer to its parent, and the
......
src/IceTypes.h
......@@ -129,7 +129,7 @@ class FuncSigType {
FuncSigType &operator=(const FuncSigType &Ty) = delete;
public:
typedef std::vector<Type> ArgListType;
using ArgListType = std::vector<Type>;
/// Creates a function signature type with the given return type.
/// Parameter types should be added using calls to appendArgType.
......
src/PNaClTranslator.cpp
......@@ -945,8 +945,8 @@ public:
const char *getBlockName() const override { return "globals"; }
private:
typedef std::unordered_map<NaClBcIndexSize_t, Ice::VariableDeclaration *>
GlobalVarsMapType;
using GlobalVarsMapType =
std::unordered_map<NaClBcIndexSize_t, Ice::VariableDeclaration *>;
Ice::TimerMarker Timer;
......@@ -1158,7 +1158,7 @@ public:
const char *getBlockName() const override { return "valuesymtab"; }
protected:
typedef SmallString<128> StringType;
using StringType = SmallString<128>;
// Associates Name with the value defined by the given Index.
virtual void setValueName(NaClBcIndexSize_t Index, StringType &Name) = 0;
......
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