Subzero, MIPS32: Changes for improving sandbox crosstest results

crosstest/test_calling_conv_main.cpp

@@ -69,6 +69,16 @@ void testCaller(size_t &TotalTests, size_t &Passes, size_t &Failures) {
     void (*Subzero_Caller)(void);
     CalleePtrTy Callee;
   } Funcs[] = {
+#ifdef MIPS32
+#define X(caller, callee, argc)                                                \
+  {                                                                            \
+    STR(caller), STR(callee), argc, &caller, &Subzero_::caller,                \
+        reinterpret_cast<CalleePtrTy>(&Subzero_::callee),                      \
+  }                                                                            \
+  ,
+      TEST_FUNC_TABLE
+#undef X
+#else
 #define X(caller, callee, argc)                                                \
   {                                                                            \
     STR(caller), STR(callee), argc, &caller, &Subzero_::caller,                \
@@ -77,6 +87,7 @@ void testCaller(size_t &TotalTests, size_t &Passes, size_t &Failures) {
   ,
       TEST_FUNC_TABLE
 #undef X
+#endif
   };
 
   const static size_t NumFuncs = sizeof(Funcs) / sizeof(*Funcs);

pydir/crosstest.py

@@ -158,7 +158,9 @@ def main():
                   bitcode] + arch_sz_flags[args.target])
         if args.filetype != 'obj':
             shellcmd(['{bin}/llvm-mc'.format(bin=bindir),
-                      '-triple=' + triple,
+                      '-triple=' + ('mipsel-linux-gnu'
+                                    if args.target == 'mips32' and args.sandbox
+                                    else triple),
                       '-filetype=obj',
                       '-o=' + obj_sz,
                       asm_sz])

pydir/crosstest_generator.py

@@ -47,6 +47,8 @@ def RunNativePrefix(toolchain_root, target, attr, run_cmd):
       'arm32-hwdiv-arm': ' -cpu cortex-a15',
       'mips32-base': ' -cpu mips32r5-generic'})
   prefix = arch_map[target] + attr_map[target + '-' + attr]
+  if target == 'mips32':
+    prefix = 'QEMU_SET_ENV=LD_LIBRARY_PATH=/usr/mipsel-linux-gnu/lib/ ' + prefix
   return (prefix + ' ' + run_cmd) if prefix else run_cmd
 
 def NonsfiLoaderArch(target):

src/IceAssemblerMIPS32.cpp

@@ -650,7 +650,7 @@ void AssemblerMIPS32::jalr(const Operand *OpRs, const Operand *OpRd) {
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr");
   const IValueT Rd =
       (OpRd == nullptr) ? 31 : encodeGPRegister(OpRd, "Rd", "jalr");
-  Opcode |= Rd << 16;
+  Opcode |= Rd << 11;
   Opcode |= Rs << 21;
   emitInst(Opcode);
   nop();

src/IceTargetLoweringMIPS32.cpp

@@ -5844,6 +5844,8 @@ TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx)
     : TargetHeaderLowering(Ctx) {}
 
 void TargetHeaderMIPS32::lower() {
+  if (!BuildDefs::dump())
+    return;
   OstreamLocker L(Ctx);
   Ostream &Str = Ctx->getStrEmit();
   Str << "\t.set\t"
@@ -5852,6 +5854,8 @@ void TargetHeaderMIPS32::lower() {
       << "nomips16\n";
   Str << "\t.set\t"
       << "noat\n";
+  if (getFlags().getUseSandboxing())
+    Str << "\t.bundle_align_mode 4\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
@@ -5888,6 +5892,8 @@ void TargetMIPS32::Sandboxer::lw(Variable *Dest, OperandMIPS32Mem *Mem) {
     Target->_and(Base, Base, T7);
   }
   Target->_lw(Dest, Mem);
+  if (Target->NeedSandboxing && (Dest->getRegNum() == Target->getStackReg()))
+    Target->_and(Dest, Dest, T7);
 }
 
 void TargetMIPS32::Sandboxer::sw(Variable *Dest, OperandMIPS32Mem *Mem) {
@@ -5946,12 +5952,18 @@ void TargetMIPS32::Sandboxer::reset_sp(Variable *Src) {
   createAutoBundle();
   Target->_mov(SP, Src);
   Target->_and(SP, SP, T7);
+  Target->getContext().insert<InstFakeUse>(SP);
 }
 
 InstMIPS32Call *TargetMIPS32::Sandboxer::jal(Variable *ReturnReg,
                                              Operand *CallTarget) {
-  if (Target->NeedSandboxing)
+  if (Target->NeedSandboxing) {
     createAutoBundle();
+    if (auto *CallTargetR = llvm::dyn_cast<Variable>(CallTarget)) {
+      Variable *T6 = Target->getPhysicalRegister(RegMIPS32::Reg_T6);
+      Target->_and(CallTargetR, CallTargetR, T6);
+    }
+  }
   return Target->Context.insert<InstMIPS32Call>(ReturnReg, CallTarget);
 }