[SubZero] Fix size of arguments on stack

src/IceTargetLoweringMIPS32.cpp

@@ -225,18 +225,32 @@ uint32_t TargetMIPS32::getCallStackArgumentsSizeBytes(const InstCall *Call) {
   TargetMIPS32::CallingConv CC;
   RegNumT DummyReg;
   size_t OutArgsSizeBytes = 0;
+  Variable *Dest = Call->getDest();
+  bool PartialOnStack = false;
+  if (Dest != nullptr && isVectorFloatingType(Dest->getType())) {
+    CC.discardReg(RegMIPS32::Reg_A0);
+    // Next vector is partially on stack
+    PartialOnStack = true;
+  }
   for (SizeT i = 0, NumArgs = Call->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Call->getArg(i));
     const Type Ty = Arg->getType();
     RegNumT RegNum;
     if (CC.argInReg(Ty, i, &RegNum)) {
+      // If PartialOnStack is true and if this is a vector type then last two
+      // elements are on stack
+      if (PartialOnStack && isVectorType(Ty)) {
+        OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, IceType_i32);
+        OutArgsSizeBytes += typeWidthInBytesOnStack(IceType_i32) * 2;
+      }
       continue;
     }
-
     OutArgsSizeBytes = applyStackAlignmentTy(OutArgsSizeBytes, Ty);
     OutArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   }
-
+  // Add size of argument save area
+  constexpr int BytesPerStackArg = 4;
+  OutArgsSizeBytes += MIPS32_MAX_GPR_ARG * BytesPerStackArg;
   return applyStackAlignment(OutArgsSizeBytes);
 }
 

tests_lit/llvm2ice_tests/fused-alloca-arg.ll

@@ -43,11 +43,11 @@ entry:
 ; MIPS32: 	sw	ra,{{.*}}(sp)
 ; MIPS32: 	move	v0,a0
 ; MIPS32: 	sw	v0,{{.*}}(sp)
-; MIPS32: 	addiu	v0,sp,16
+; MIPS32: 	addiu	v0,sp,32
 ; MIPS32: 	sw	v0,{{.*}}(sp)
-; MIPS32: 	addiu	a1,sp,16
-; MIPS32: 	addiu	a2,sp,16
-; MIPS32: 	addiu	a3,sp,16
+; MIPS32: 	addiu	a1,sp,32
+; MIPS32: 	addiu	a2,sp,32
+; MIPS32: 	addiu	a3,sp,32
 ; MIPS32: 	jal
 ; MIPS32: 	nop
 ; MIPS32: 	lw	ra,{{.*}}(sp)
@@ -91,11 +91,11 @@ entry:
 ; MIPS32: 	sw	v0,{{.*}}(sp)
 ; MIPS32: 	move	v0,a0
 ; MIPS32: 	sw	v0,{{.*}}(sp)
-; MIPS32: 	addiu	v0,sp,48
+; MIPS32: 	addiu	v0,sp,64
 ; MIPS32: 	sw	v0,{{.*}}(sp)
-; MIPS32: 	addiu	a1,sp,16
-; MIPS32: 	addiu	a2,sp,48
-; MIPS32: 	addiu	a3,sp,16
+; MIPS32: 	addiu	a1,sp,32
+; MIPS32: 	addiu	a2,sp,64
+; MIPS32: 	addiu	a3,sp,32
 ; MIPS32: 	jal
 ; MIPS32: 	nop
 ; MIPS32: 	lw	ra,{{.*}}(sp)

tests_lit/llvm2ice_tests/vector-arg.ll

@@ -553,7 +553,7 @@ entry:
 ; MIPS32: 	sw	s0,{{.*}}(sp)
 ; MIPS32: 	move	s8,sp
 ; MIPS32: 	move	v0,a0
-; MIPS32: 	addiu	v1,sp,16
+; MIPS32: 	addiu	v1,sp,32
 ; MIPS32: 	move	s0,v1
 ; MIPS32: 	move	a0,s0
 ; MIPS32: 	sw	a2,{{.*}}(sp)
@@ -567,7 +567,7 @@ entry:
 ; MIPS32: 	lw	a0,8(s0)
 ; MIPS32: 	move	a1,a0
 ; MIPS32: 	lw	s0,12(s0)
-; MIPS32: 	addiu	a0,sp,32
+; MIPS32: 	addiu	a0,sp,48
 ; MIPS32: 	sw	a1,{{.*}}(sp)
 ; MIPS32: 	sw	s0,{{.*}}(sp)
 ; MIPS32: 	move	a2,v0