Subzero: Remove trailing whitespace.

Doxyfile

@@ -1947,7 +1947,7 @@ PREDEFINED             =
 EXPAND_AS_DEFINED      =
 
 # If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
-# remove all references to function-like macros that are alone on a line, have 
+# remove all references to function-like macros that are alone on a line, have
 # an all uppercase name, and do not end with a semicolon. Such function macros
 # are typically used for boiler-plate code, and will confuse the parser if not
 # removed.

pydir/crosstest.py

@@ -196,7 +196,7 @@ def main():
     if args.target == 'arm32':
       target_params.append('-DARM32')
       target_params.append('-static')
-    
+
     # Set compiler to clang, clang++, pnacl-clang, or pnacl-clang++.
     compiler = '{bin}/{prefix}{cc}'.format(
         bin=bindir, prefix='pnacl-' if args.sandbox else '',

pydir/szbuild_spec2k.py

@@ -23,7 +23,7 @@ def main():
                    '175.vpr', '176.gcc', '181.mcf', '186.crafty', '197.parser',
                    '253.perlbmk', '254.gap', '255.vortex', '256.bzip2',
                    '300.twolf', '252.eon' ]
-    
+
     argparser = argparse.ArgumentParser(description=main.__doc__)
     szbuild.AddOptionalArgs(argparser)
     argparser.add_argument('comps', nargs='*', default=components)

src/IceInstARM32.def

@@ -114,7 +114,7 @@
 //     is_preserved = 1 if i >= 16 else 0
 //     print ('  X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
 //            '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' +
-//            'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' + 
+//            'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' +
 //            'Reg_q{regnum_q:<2}))    \\').format(
 //            regnum=i, regnum_d=i>>1,
 //            regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
@@ -187,7 +187,7 @@
   X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
     ALIASES3(Reg_s30, Reg_d15, Reg_q7))                                        \
   X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
-    ALIASES3(Reg_s31, Reg_d15, Reg_q7)) 
+    ALIASES3(Reg_s31, Reg_d15, Reg_q7))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32,isFP64, isVec128, aliases_init)
 
@@ -286,7 +286,7 @@
   X(Reg_d1 , 1 ,  "d1", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
     ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0))                               \
   X(Reg_d0 , 0 ,  "d0", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
-    ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0)) 
+    ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init)
 
@@ -354,7 +354,7 @@
   X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1,                              \
     ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1))    \
   X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1,                              \
-    ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0)) 
+    ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 #undef ALIASES

src/IceInstX8632.def

@@ -26,7 +26,7 @@
   X(Reg_esp, 4, "esp", "sp", ""  , 0, 0, 1, 0, 0, 0, 0)                 \
   X(Reg_ebp, 5, "ebp", "bp", ""  , 0, 1, 0, 1, 0, 1, 0)                 \
   X(Reg_esi, 6, "esi", "si", ""  , 0, 1, 0, 0, 0, 1, 0)                 \
-  X(Reg_edi, 7, "edi", "di", ""  , 0, 1, 0, 0, 0, 1, 0)      
+  X(Reg_edi, 7, "edi", "di", ""  , 0, 1, 0, 0, 0, 1, 0)
 
 #define REGX8632_XMM_TABLE                                              \
   X(Reg_xmm0, 0, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \

tests_lit/llvm2ice_tests/64bit.pnacl.ll

@@ -517,7 +517,7 @@ entry:
 ; ARM32: orr     r0, [[T0]], r1, lsl [[T1]]
 ; ARM32: sub     [[T2:r[0-9]+]], r2, #32
 ; ARM32: cmp     [[T2]], #0
-; ARM32: asrge   r0, r1, [[T2]] 
+; ARM32: asrge   r0, r1, [[T2]]
 ; ARM32: asr     r{{[0-9]+}}, r1, r2
 
 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {

tests_lit/llvm2ice_tests/fp.arm.call.ll

@@ -47,7 +47,7 @@ declare void @float15(float %p0, float %p1, float %p2, float %p3, float %p4,
                       float %p5, float %p6, float %p7, float %p8, float %p9,
                       float %p10, float %p11, float %p12, float %p13,
                       float %p14)
-declare void @float16(float %p0, float %p1, float %p2, float %p3, float %p4, 
+declare void @float16(float %p0, float %p1, float %p2, float %p3, float %p4,
                       float %p5, float %p6, float %p7, float %p8, float %p9,
                       float %p10, float %p11, float %p12, float %p13,
                       float %p14, float %p15)