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swiftshader
Commit a054f0ac by John Porto
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Adds X8664 Condition codes.

Also fixes the X8664 Registers file. BUG= https://code.google.com/p/nativeclient/issues/detail?id=4077 R=kschimpf@google.com Review URL: https://codereview.chromium.org/1212393005.
parent 2b18687b
Showing with 85 additions and 39 deletions
src/IceConditionCodesX8664.h 0 → 100644
//===- subzero/src/IceConditionCodesX8664.h - Condition Codes ---*- C++ -*-===//
//
// The Subzero Code Generator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the condition codes for x86-64.
//
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICECONDITIONCODESX8664_H
#define SUBZERO_SRC_ICECONDITIONCODESX8664_H
#include "IceDefs.h"
#include "IceInstX8664.def"
namespace Ice {
namespace CondX8664 {
// An enum of condition codes used for branches and cmov. The enum value
// should match the value used to encode operands in binary instructions.
enum BrCond {
#define X(tag, encode, opp, dump, emit) tag encode,
ICEINSTX8664BR_TABLE
#undef X
Br_None
};
// An enum of condition codes relevant to the CMPPS instruction. The enum
// value should match the value used to encode operands in binary
// instructions.
enum CmppsCond {
#define X(tag, emit) tag,
ICEINSTX8664CMPPS_TABLE
#undef X
Cmpps_Invalid
};
} // end of namespace CondX8664
} // end of namespace Ice
#endif // SUBZERO_SRC_ICECONDITIONCODESX8664_H
src/IceInstX8664.def
...@@ -39,22 +39,22 @@ ...@@ -39,22 +39,22 @@
#define REGX8664_XMM_TABLE \ #define REGX8664_XMM_TABLE \
/* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isInt, isFP */ \ frameptr, isInt, isFP */ \
X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm8, = Reg_xmm0 + 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm8, = Reg_xmm0 + 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm9, = Reg_xmm0 + 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm9, = Reg_xmm0 + 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm10, = Reg_xmm0 + 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm10, = Reg_xmm0 + 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm11, = Reg_xmm0 + 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm11, = Reg_xmm0 + 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm12, = Reg_xmm0 + 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm12, = Reg_xmm0 + 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm13, = Reg_xmm0 + 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm13, = Reg_xmm0 + 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm14, = Reg_xmm0 + 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ X(Reg_xmm14, = Reg_xmm0 + 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \
X(Reg_xmm15, = Reg_xmm0 + 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 0, 1) X(Reg_xmm15, = Reg_xmm0 + 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1)
//#define X(val, encode, name, name32, name16, name8, scratch, preserved, //#define X(val, encode, name, name32, name16, name8, scratch, preserved,
// stackptr, frameptr, isI8, isInt, isFP) // stackptr, frameptr, isI8, isInt, isFP)
...@@ -88,22 +88,22 @@ ...@@ -88,22 +88,22 @@
// bh registers to keep register selection simple. // bh registers to keep register selection simple.
#define REGX8664_BYTEREG_TABLE \ #define REGX8664_BYTEREG_TABLE \
/* val , encode */ \ /* val , encode */ \
X(Reg_al , = 0) \ X(Reg_al , = 0) \
X(Reg_cl , = Reg_al + 1) \ X(Reg_cl , = 1) \
X(Reg_dl , = Reg_al + 2) \ X(Reg_dl , = 2) \
X(Reg_bl , = Reg_al + 3) \ X(Reg_bl , = 3) \
X(Reg_spl , = Reg_al + 4) \ X(Reg_spl , = 4) \
X(Reg_bpl , = Reg_al + 5) \ X(Reg_bpl , = 5) \
X(Reg_sil , = Reg_al + 6) \ X(Reg_sil , = 6) \
X(Reg_dil , = Reg_al + 7) \ X(Reg_dil , = 7) \
X(Reg_r8l , = Reg_al + 8) \ X(Reg_r8l , = 8) \
X(Reg_r9l , = Reg_al + 9) \ X(Reg_r9l , = 9) \
X(Reg_r10l, = Reg_al + 10) \ X(Reg_r10l, = 10) \
X(Reg_r11l, = Reg_al + 11) \ X(Reg_r11l, = 11) \
X(Reg_r12l, = Reg_al + 12) \ X(Reg_r12l, = 12) \
X(Reg_r13l, = Reg_al + 13) \ X(Reg_r13l, = 13) \
X(Reg_r14l, = Reg_al + 14) \ X(Reg_r14l, = 14) \
X(Reg_r15l, = Reg_al + 15) X(Reg_r15l, = 15)
//#define X(val, encode) //#define X(val, encode)
#define ICEINSTX8664BR_TABLE \ #define ICEINSTX8664BR_TABLE \
...@@ -123,7 +123,7 @@ ...@@ -123,7 +123,7 @@
X(Br_l , = 12, Br_ge , "l" , "jl" ) \ X(Br_l , = 12, Br_ge , "l" , "jl" ) \
X(Br_ge , = 13, Br_l , "ge", "jge") \ X(Br_ge , = 13, Br_l , "ge", "jge") \
X(Br_le , = 14, Br_g , "le", "jle") \ X(Br_le , = 14, Br_g , "le", "jle") \
X(Br_g , = 15, Br_le , "g" , "jg"): X(Br_g , = 15, Br_le , "g" , "jg")
//#define X(tag, encode, opp, dump, emit) //#define X(tag, encode, opp, dump, emit)
#define ICEINSTX8664CMPPS_TABLE \ #define ICEINSTX8664CMPPS_TABLE \
......
src/IceRegistersX8664.h
...@@ -25,8 +25,8 @@ namespace RegX8664 { ...@@ -25,8 +25,8 @@ namespace RegX8664 {
// An enum of every register. The enum value may not match the encoding // An enum of every register. The enum value may not match the encoding
// used to binary encode register operands in instructions. // used to binary encode register operands in instructions.
enum AllRegisters { enum AllRegisters {
#define X(val, encode, name, name32, name16, name8, scratch, preserved, \ #define X(val, encode, name64, name, name16, name8, scratch, preserved, \
stackptr, frameptr, isI8, isInt, isFP) \ stackptr, frameptr, isInt, isFP) \
val, val,
REGX8664_TABLE REGX8664_TABLE
#undef X #undef X
...@@ -39,8 +39,8 @@ enum AllRegisters { ...@@ -39,8 +39,8 @@ enum AllRegisters {
// An enum of GPR Registers. The enum value does match the encoding used // An enum of GPR Registers. The enum value does match the encoding used
// to binary encode register operands in instructions. // to binary encode register operands in instructions.
enum GPRRegister { enum GPRRegister {
#define X(val, encode, name, name32, name16, name8, scratch, preserved, \ #define X(val, encode, name64, name, name16, name8, scratch, preserved, \
stackptr, frameptr, isI8, isInt, isFP) \ stackptr, frameptr, isInt, isFP) \
Encoded_##val encode, Encoded_##val encode,
REGX8664_GPR_TABLE REGX8664_GPR_TABLE
#undef X #undef X
...@@ -50,8 +50,8 @@ enum GPRRegister { ...@@ -50,8 +50,8 @@ enum GPRRegister {
// An enum of XMM Registers. The enum value does match the encoding used // An enum of XMM Registers. The enum value does match the encoding used
// to binary encode register operands in instructions. // to binary encode register operands in instructions.
enum XmmRegister { enum XmmRegister {
#define X(val, encode, name, name32, name16, name8, scratch, preserved, \ #define X(val, encode, name64, name, name16, name8, scratch, preserved, \
stackptr, frameptr, isI8, isInt, isFP) \ stackptr, frameptr, isInt, isFP) \
Encoded_##val encode, Encoded_##val encode,
REGX8664_XMM_TABLE REGX8664_XMM_TABLE
#undef X #undef X
......
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