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swiftshader
Commit a1410df9 by Jim Stichnoth
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Subzero: Build a better bitcast.

The x86 lowering of bitcast between integers and floats forced the transfer through a stack slot (the original implementer *cough* *cough* wasn't aware of the movd instruction). This requires excess instructions, but also a store to memory followed immediately by a load from that location is very slow. This fixes the problem by using the movd instruction instead. BUG= none R=jpp@chromium.org Review URL: https://codereview.chromium.org/2077503002 .
parent 4e81fe0a
Showing with 5 additions and 19 deletions
src/IceTargetLoweringX86BaseImpl.h
...@@ -3059,24 +3059,10 @@ void TargetX86Base<TraitsType>::lowerCast(const InstCast *Instr) { ...@@ -3059,24 +3059,10 @@ void TargetX86Base<TraitsType>::lowerCast(const InstCast *Instr) {
} break; } break;
case IceType_i32: case IceType_i32:
case IceType_f32: { case IceType_f32: {
Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem); Variable *Src0R = legalizeToReg(Src0);
Type SrcType = Src0RM->getType(); Variable *T = makeReg(DestTy);
assert((DestTy == IceType_i32 && SrcType == IceType_f32) || _movd(T, Src0R);
(DestTy == IceType_f32 && SrcType == IceType_i32)); _mov(Dest, T);
// a.i32 = bitcast b.f32 ==>
// t.f32 = b.f32
// s.f32 = spill t.f32
// a.i32 = s.f32
Variable *T = nullptr;
// TODO: Should be able to force a spill setup by calling legalize() with
// Legal_Mem and not Legal_Reg or Legal_Imm.
SpillVariable *SpillVar = Func->makeVariable<SpillVariable>(SrcType);
SpillVar->setLinkedTo(Dest);
Variable *Spill = SpillVar;
Spill->setMustNotHaveReg();
_mov(T, Src0RM);
_mov(Spill, T);
_mov(Dest, Spill);
} break; } break;
case IceType_i64: { case IceType_i64: {
assert(Src0->getType() == IceType_f64); assert(Src0->getType() == IceType_f64);
......
tests_lit/llvm2ice_tests/bitcast.ll
...@@ -19,7 +19,7 @@ entry: ...@@ -19,7 +19,7 @@ entry:
ret i32 %v0 ret i32 %v0
} }
; CHECK-LABEL: cast_f2i ; CHECK-LABEL: cast_f2i
; CHECK: mov eax ; CHECK: movd eax
; ARM32-LABEL: cast_f2i ; ARM32-LABEL: cast_f2i
; ARM32: vmov r{{[0-9]+}}, s{{[0-9]+}} ; ARM32: vmov r{{[0-9]+}}, s{{[0-9]+}}
......
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