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Commit a2703ae4 by Jan Voung
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Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge)

After the next LLVM merge, llvm-objdump is going to lose the "--symbolize" flag. It also sounds like llvm-objdump may at some point converge to the objdump-style of output. So, rather than keep updating test expectations, switch to objdump, assuming objdump will be more stable than llvm-objdump. Also stash the assembler/disassembler commandlines in the run-llvm2ice.py script. In theory this will let us tweak the commandlines more easily (one place). In practice the test expectatations will probably need to be adjusted if the base commandlines change though. Bulk edit the test expectations to match objdump now. Some of this is assisted by a python script. Example script: https://codereview.chromium.org/928663002/ BUG= https://code.google.com/p/nativeclient/issues/detail?id=4026 R=kschimpf@google.com, stichnot@chromium.org Review URL: https://codereview.chromium.org/914263005
parent 029986c8
Showing with 960 additions and 1069 deletions
Makefile.standalone
......@@ -28,6 +28,10 @@ LIBCXX_INSTALL_PATH ?= $(shell readlink -e \
CLANG_PATH ?= $(shell readlink -e \
../../../../third_party/llvm-build/Release+Asserts/bin)
# The location of binutils tools (e.g., objdump).
BINUTILS_BIN_PATH ?= $(shell readlink -e \
../../out/binutils_pnacl_x86_64_linux_work/binutils)
HOST_ARCH ?= x86_64
ifeq ($(HOST_ARCH),x86_64)
HOST_FLAGS = -m64 -stdlib=libc++
......@@ -80,6 +84,7 @@ $(info Using LLVM_SRC_PATH = $(LLVM_SRC_PATH))
$(info Using LLVM_BIN_PATH = $(LLVM_BIN_PATH))
$(info Using LIBCXX_INSTALL_PATH = $(LIBCXX_INSTALL_PATH))
$(info Using CLANG_PATH = $(CLANG_PATH))
$(info Using BINUTILS_BIN_PATH = $(BINUTILS_BIN_PATH))
$(info Using HOST_ARCH = $(HOST_ARCH))
$(info -----------------------------------------------)
......@@ -188,6 +193,7 @@ $(OBJDIR)/unittest: $(OBJDIR)
check-lit: $(OBJDIR)/llvm2ice make_symlink
LLVM_BIN_PATH=$(LLVM_BIN_PATH) \
BINUTILS_BIN_PATH=$(BINUTILS_BIN_PATH) \
$(LLVM_SRC_PATH)/utils/lit/lit.py -sv tests_lit
check-unit: $(OBJDIR)/run_unittests
......
pydir/run-llvm2ice.py
......@@ -6,6 +6,7 @@ import os
import re
import subprocess
import sys
import tempfile
from utils import shellcmd
......@@ -43,6 +44,18 @@ def main():
default=None, metavar='LLVM_BIN_PATH',
help='Path to LLVM executables ' +
'(for building PEXE files)')
argparser.add_argument('--binutils-bin-path', required=False,
default=None, metavar='BINUTILS_BIN_PATH',
help='Path to Binutils executables')
argparser.add_argument('--assemble', required=False,
action='store_true',
help='Assemble the output')
argparser.add_argument('--disassemble', required=False,
action='store_true',
help='Disassemble the assembled output')
argparser.add_argument('--dis-flags', required=False,
action='append', default=[],
help='Add a disassembler flag')
argparser.add_argument('--echo-cmd', required=False,
action='store_true',
help='Trace command that generates ICE instructions')
......@@ -52,6 +65,7 @@ def main():
args = argparser.parse_args()
llvm_bin_path = args.llvm_bin_path
binutils_bin_path = args.binutils_bin_path
llfile = args.input
if args.llvm and args.llvm_source:
......@@ -85,10 +99,28 @@ def main():
cmd += args.args
if args.llvm_source:
cmd += [llfile]
asm_temp = None
if args.assemble or args.disassemble:
# On windows we may need to close the file first before it can be
# re-opened by the other tools, so don't do delete-on-close,
# and instead manually delete.
asm_temp = tempfile.NamedTemporaryFile(delete=False)
asm_temp.close()
if args.assemble:
cmd += ['|', os.path.join(llvm_bin_path, 'llvm-mc'),
'-triple=i686-none-nacl',
'-filetype=obj', '-o', asm_temp.name]
if args.disassemble:
# Show wide instruction encodings, diassemble, and show relocs.
cmd += (['&&', os.path.join(binutils_bin_path, 'objdump')] +
args.dis_flags +
['-w', '-d', '-r', '-Mintel', asm_temp.name])
stdout_result = shellcmd(cmd, echo=args.echo_cmd)
if not args.echo_cmd:
sys.stdout.write(stdout_result)
if asm_temp:
os.remove(asm_temp.name)
if __name__ == '__main__':
main()
tests_lit/assembler/x86/immediate_encodings.ll
......@@ -2,9 +2,8 @@
; For example, the encoding is shorter for 8-bit immediates or when using EAX.
; This assumes that EAX is chosen as the first free register in O2 mode.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
define internal i32 @testXor8Imm8(i32 %arg) {
entry:
......@@ -14,7 +13,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor8Imm8
; CHECK: 34 7f xor al, 127
; CHECK: 34 7f xor al
define internal i32 @testXor8Imm8Neg(i32 %arg) {
entry:
......@@ -24,7 +23,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor8Imm8Neg
; CHECK: 34 80 xor al, -128
; CHECK: 34 80 xor al
define internal i32 @testXor8Imm8NotEAX(i32 %arg, i32 %arg2, i32 %arg3) {
entry:
......@@ -40,7 +39,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor8Imm8NotEAX
; CHECK: 80 f{{[1-3]}} 7f xor {{[^a]}}l, 127
; CHECK: 80 f{{[1-3]}} 7f xor {{[^a]}}l
define internal i32 @testXor16Imm8(i32 %arg) {
entry:
......@@ -50,7 +49,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor16Imm8
; CHECK: 66 83 f0 7f xor ax, 127
; CHECK: 66 83 f0 7f xor ax
define internal i32 @testXor16Imm8Neg(i32 %arg) {
entry:
......@@ -60,7 +59,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor16Imm8Neg
; CHECK: 66 83 f0 80 xor ax, -128
; CHECK: 66 83 f0 80 xor ax
define internal i32 @testXor16Imm16Eax(i32 %arg) {
entry:
......@@ -71,8 +70,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor16Imm16Eax
; CHECK: 66 35 00 04 xor ax, 1024
; CHECK-NEXT: add ax, 1
; CHECK: 66 35 00 04 xor ax
; CHECK-NEXT: add ax,0x1
define internal i32 @testXor16Imm16NegEax(i32 %arg) {
entry:
......@@ -83,8 +82,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor16Imm16NegEax
; CHECK: 66 35 00 ff xor ax, 65280
; CHECK-NEXT: add ax, 1
; CHECK: 66 35 00 ff xor ax
; CHECK-NEXT: add ax,0x1
define internal i32 @testXor16Imm16NotEAX(i32 %arg_i32, i32 %arg2_i32, i32 %arg3_i32) {
entry:
......@@ -100,8 +99,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor16Imm16NotEAX
; CHECK: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x, 32767
; CHECK-NEXT: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x, 32767
; CHECK: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x
; CHECK-NEXT: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x
define internal i32 @testXor32Imm8(i32 %arg) {
entry:
......@@ -109,7 +108,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor32Imm8
; CHECK: 83 f0 7f xor eax, 127
; CHECK: 83 f0 7f xor eax
define internal i32 @testXor32Imm8Neg(i32 %arg) {
entry:
......@@ -117,7 +116,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor32Imm8Neg
; CHECK: 83 f0 80 xor eax, -128
; CHECK: 83 f0 80 xor eax
define internal i32 @testXor32Imm32Eax(i32 %arg) {
entry:
......@@ -125,7 +124,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor32Imm32Eax
; CHECK: 35 00 00 00 01 xor eax, 16777216
; CHECK: 35 00 00 00 01 xor eax
define internal i32 @testXor32Imm32NegEax(i32 %arg) {
entry:
......@@ -133,7 +132,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXor32Imm32NegEax
; CHECK: 35 00 ff ff ff xor eax, 4294967040
; CHECK: 35 00 ff ff ff xor eax
define internal i32 @testXor32Imm32NotEAX(i32 %arg, i32 %arg2, i32 %arg3) {
entry:
......@@ -145,7 +144,7 @@ entry:
ret i32 %add2
}
; CHECK-LABEL: testXor32Imm32NotEAX
; CHECK: 81 f{{[1-3]}} ff 7f 00 00 xor e{{[^a]}}x, 32767
; CHECK: 81 f{{[1-3]}} ff 7f 00 00 xor e{{[^a]}}x,
; Should be similar for add, sub, etc., so sample a few.
......@@ -157,7 +156,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testAdd8Imm8
; CHECK: 04 7e add al, 126
; CHECK: 04 7e add al
define internal i32 @testSub8Imm8(i32 %arg) {
entry:
......@@ -167,7 +166,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testSub8Imm8
; CHECK: 2c 7d sub al, 125
; CHECK: 2c 7d sub al
; imul has some shorter 8-bit immediate encodings.
; It also has a shorter encoding for eax, but we don't do that yet.
......@@ -181,8 +180,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul16Imm8
; CHECK: 66 6b c0 63 imul ax, ax, 99
; CHECK-NEXT: add ax, 1
; CHECK: 66 6b c0 63 imul ax,ax
; CHECK-NEXT: add ax,0x1
define internal i32 @testMul16Imm8Neg(i32 %arg) {
entry:
......@@ -193,8 +192,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul16Imm8Neg
; CHECK: 66 6b c0 91 imul ax, ax, -111
; CHECK-NEXT: add ax, 1
; CHECK: 66 6b c0 91 imul ax,ax
; CHECK-NEXT: add ax,0x1
define internal i32 @testMul16Imm16(i32 %arg) {
entry:
......@@ -205,8 +204,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul16Imm16
; CHECK: 66 69 c0 00 04 imul ax, ax, 1024
; CHECK-NEXT: add ax, 1
; CHECK: 66 69 c0 00 04 imul ax,ax
; CHECK-NEXT: add ax,0x1
define internal i32 @testMul16Imm16Neg(i32 %arg) {
entry:
......@@ -217,8 +216,8 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul16Imm16Neg
; CHECK: 66 69 c0 00 ff imul ax, ax, 65280
; CHECK-NEXT: add ax, 1
; CHECK: 66 69 c0 00 ff imul ax,ax
; CHECK-NEXT: add ax,0x1
define internal i32 @testMul32Imm8(i32 %arg) {
entry:
......@@ -226,7 +225,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul32Imm8
; CHECK: 6b c0 63 imul eax, eax, 99
; CHECK: 6b c0 63 imul eax,eax
define internal i32 @testMul32Imm8Neg(i32 %arg) {
entry:
......@@ -234,7 +233,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul32Imm8Neg
; CHECK: 6b c0 91 imul eax, eax, -111
; CHECK: 6b c0 91 imul eax,eax
define internal i32 @testMul32Imm16(i32 %arg) {
entry:
......@@ -242,7 +241,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul32Imm16
; CHECK: 69 c0 00 04 00 00 imul eax, eax, 1024
; CHECK: 69 c0 00 04 00 00 imul eax,eax
define internal i32 @testMul32Imm16Neg(i32 %arg) {
entry:
......@@ -250,7 +249,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testMul32Imm16Neg
; CHECK: 69 c0 00 ff ff ff imul eax, eax, 4294967040
; CHECK: 69 c0 00 ff ff ff imul eax,eax
; The GPR shift instructions either allow an 8-bit immediate or
; have a special encoding for "1".
......@@ -262,7 +261,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testShl16Imm8
; CHECK: 66 c1 e0 0d shl ax, 13
; CHECK: 66 c1 e0 0d shl ax,0xd
define internal i32 @testShl16Imm1(i32 %arg) {
entry:
......@@ -286,9 +285,9 @@ entry:
ret i64 %shl
}
; CHECK-LABEL: test_via_shl64Bit
; CHECK: 0f a5 c2 shld edx, eax, cl
; CHECK: d3 e0 shl eax, cl
; CHECK: f6 c1 20 test cl, 32
; CHECK: 0f a5 c2 shld edx,eax,cl
; CHECK: d3 e0 shl eax,cl
; CHECK: f6 c1 20 test cl,0x20
; Test a few register encodings of "test".
declare i64 @llvm.ctlz.i64(i64, i1)
......@@ -305,6 +304,6 @@ entry:
ret i64 %res
}
; CHECK-LABEL: test_via_ctlz_64
; CHECK-DAG: 85 c0 test eax, eax
; CHECK-DAG: 85 db test ebx, ebx
; CHECK-DAG: 85 f6 test esi, esi
; CHECK-DAG: 85 c0 test eax,eax
; CHECK-DAG: 85 db test ebx,ebx
; CHECK-DAG: 85 f6 test esi,esi
tests_lit/assembler/x86/jump_encodings.ll
......@@ -2,9 +2,8 @@
; forward vs backward, using CFG labels, or local labels).
; Use -ffunction-sections so that the offsets reset for each function.
; RUN: %p2i -i %s --args -O2 --verbose none -ffunction-sections \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: -ffunction-sections | FileCheck %s
; Use atomic ops as filler, which shouldn't get optimized out.
declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
......@@ -25,15 +24,13 @@ next2:
}
; CHECK-LABEL: test_near_backward
; CHECK: 8: {{.*}} mov dword ptr
; CHECK: 8: {{.*}} mov DWORD PTR
; CHECK-NEXT: a: {{.*}} mfence
; CHECK-NEXT: d: {{.*}} mov dword ptr
; CHECK-NEXT: d: {{.*}} mov DWORD PTR
; CHECK-NEXT: f: {{.*}} mfence
; CHECK-NEXT: 12: {{.*}} cmp
; (0x15 + 2) - 10 == 0xd
; CHECK-NEXT: 15: 72 f6 jb -10
; (0x17 + 2) - 17 == 0x8
; CHECK-NEXT: 17: eb ef jmp -17
; CHECK-NEXT: 15: 72 f6 jb d
; CHECK-NEXT: 17: eb ef jmp 8
; Test one of the backward branches being too large for 8 bits
; and one being just okay.
......@@ -74,13 +71,11 @@ next2:
}
; CHECK-LABEL: test_far_backward1
; CHECK: 8: {{.*}} mov {{.*}}, dword ptr [e{{[^s]}}
; CHECK-NEXT: a: {{.*}} mov dword ptr
; CHECK: 8: {{.*}} mov {{.*}},DWORD PTR [e{{[^s]}}
; CHECK-NEXT: a: {{.*}} mov DWORD PTR
; CHECK-NEXT: c: {{.*}} mfence
; (0x85 + 2) - 125 == 0xa
; CHECK: 85: 77 83 ja -125
; (0x87 + 5) - 132 == 0x8
; CHECK-NEXT: 87: e9 7c ff ff ff jmp -132
; CHECK: 85: 77 83 ja a
; CHECK-NEXT: 87: e9 7c ff ff ff jmp 8
; Same as test_far_backward1, but with the conditional branch being
; the one that is too far.
......@@ -124,14 +119,12 @@ next2:
}
; CHECK-LABEL: test_far_backward2
; CHECK: c: {{.*}} mov {{.*}}, dword ptr [e{{[^s]}}
; CHECK: 14: {{.*}} mov {{.*}}, dword ptr
; CHECK-NEXT: 16: {{.*}} mov dword ptr
; CHECK: c: {{.*}} mov {{.*}},DWORD PTR [e{{[^s]}}
; CHECK: 14: {{.*}} mov {{.*}},DWORD PTR
; CHECK-NEXT: 16: {{.*}} mov DWORD PTR
; CHECK-NEXT: 18: {{.*}} mfence
; (0x8c + 6) - 134 == 0xc
; CHECK: 8c: 0f 8e 7a ff ff ff jle -134
; (0x92 + 2) - 126 == 0x16
; CHECK-NEXT: 92: eb 82 jmp -126
; CHECK: 8c: 0f 8e 7a ff ff ff jle c
; CHECK-NEXT: 92: eb 82 jmp 16
define void @test_near_forward(i32 %iptr, i32 %val) {
entry:
......@@ -151,14 +144,11 @@ next3:
; form to avoid needing a relaxation pass.
; CHECK-LABEL: test_near_forward
; CHECK: 8: {{.*}} cmp
; CHECK-NEXT: b: 0f 82 05 00 00 00 jb 5
; CHECK-NEXT: 11: {{.*}} mov dword ptr
; CHECK-NEXT: b: 0f 82 05 00 00 00 jb 16
; CHECK-NEXT: 11: {{.*}} mov DWORD PTR
; CHECK-NEXT: 13: {{.*}} mfence
; Forward branch is 5 bytes ahead to here.
; CHECK-NEXT: 16: {{.*}} mov dword ptr
; Jumps back to (0x1b + 2) - 21 == 0x8 (to before the forward branch,
; therefore knowing that the forward branch was indeed 6 bytes).
; CHECK: 1b: eb eb jmp -21
; CHECK-NEXT: 16: {{.*}} mov DWORD PTR
; CHECK: 1b: eb eb jmp 8
; Unlike forward branches to cfg nodes, "local" forward branches
......@@ -179,15 +169,13 @@ next2:
br i1 %cmp, label %next, label %next2
}
; CHECK-LABEL: test_local_forward_then_back
; CHECK: 14: {{.*}} mov dword ptr
; CHECK: 14: {{.*}} mov DWORD PTR
; CHECK-NEXT: 16: {{.*}} mfence
; CHECK-NEXT: 19: {{.*}} mov dword ptr {{.*}}, 1
; CHECK-NEXT: 19: {{.*}} mov DWORD PTR {{.*}},0x1
; CHECK-NEXT: 20: {{.*}} cmp
; CHECK-NEXT: 23: {{.*}} jb 14
; (0x37 + 2) - 37 == 0x14
; CHECK: 37: {{.*}} jne -37
; (0x39 + 2) - 34 == 0x19
; CHECK: 39: {{.*}} jmp -34
; CHECK-NEXT: 23: {{.*}} jb 33
; CHECK: 37: {{.*}} jne 14
; CHECK: 39: {{.*}} jmp 19
; Test that backward local branches also work and are small.
......@@ -204,12 +192,9 @@ next2:
br i1 %success, label %next, label %next2
}
; CHECK-LABEL: test_local_backward
; CHECK: 9: {{.*}} mov {{.*}}, dword
; CHECK: 9: {{.*}} mov {{.*}},DWORD
; CHECK: b: {{.*}} mov
; CHECK-NEXT: d: {{.*}} xor
; CHECK-NEXT: f: {{.*}} lock
; CHECK-NEXT: 10: {{.*}} cmpxchg
; (0x13 + 2) - 10 == 0xb
; CHECK-NEXT: 13: 75 f6 jne -10
; (0x1c + 2) - 21 == 0x9
; CHECK: 1c: 74 eb je -21
; CHECK-NEXT: f: {{.*}} lock cmpxchg
; CHECK-NEXT: 13: 75 f6 jne b
; CHECK: 1c: 74 eb je 9
tests_lit/assembler/x86/opcode_register_encodings.ll
......@@ -2,16 +2,15 @@
; those for pmull vary more wildly depending on operand size (rather than
; follow a usual pattern).
; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 -sandbox --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 -mattr=sse4.1 -sandbox \
; RUN: --verbose none | FileCheck %s
define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
entry:
%res = mul <8 x i16> %arg0, %arg1
ret <8 x i16> %res
; CHECK-LABEL: test_mul_v8i16
; CHECK: 66 0f d5 c1 pmullw xmm0, xmm1
; CHECK: 66 0f d5 c1 pmullw xmm0,xmm1
}
; Test register and address mode encoding.
......@@ -34,14 +33,14 @@ entry:
%res = select <8 x i1> %cond, <8 x i16> %res_acc1_3, <8 x i16> %res_acc2_4
ret <8 x i16> %res
; CHECK-LABEL: test_mul_v8i16_more_regs
; CHECK-DAG: 66 0f d5 c2 pmullw xmm0, xmm2
; CHECK-DAG: 66 0f d5 c3 pmullw xmm0, xmm3
; CHECK-DAG: 66 0f d5 c4 pmullw xmm0, xmm4
; CHECK-DAG: 66 0f d5 c5 pmullw xmm0, xmm5
; CHECK-DAG: 66 0f d5 c6 pmullw xmm0, xmm6
; CHECK-DAG: 66 0f d5 c7 pmullw xmm0, xmm7
; CHECK-DAG: 66 0f d5 44 24 70 pmullw xmm0, xmmword ptr [esp + 112]
; CHECK-DAG: 66 0f d5 8c 24 80 00 00 00 pmullw xmm1, xmmword ptr [esp + 128]
; CHECK-DAG: 66 0f d5 c2 pmullw xmm0,xmm2
; CHECK-DAG: 66 0f d5 c3 pmullw xmm0,xmm3
; CHECK-DAG: 66 0f d5 c4 pmullw xmm0,xmm4
; CHECK-DAG: 66 0f d5 c5 pmullw xmm0,xmm5
; CHECK-DAG: 66 0f d5 c6 pmullw xmm0,xmm6
; CHECK-DAG: 66 0f d5 c7 pmullw xmm0,xmm7
; CHECK-DAG: 66 0f d5 44 24 70 pmullw xmm0,XMMWORD PTR [esp
; CHECK-DAG: 66 0f d5 8c 24 80 00 00 00 pmullw xmm1,XMMWORD PTR [esp
}
define <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
......@@ -49,7 +48,7 @@ entry:
%res = mul <4 x i32> %arg0, %arg1
ret <4 x i32> %res
; CHECK-LABEL: test_mul_v4i32
; CHECK: 66 0f 38 40 c1 pmulld xmm0, xmm1
; CHECK: 66 0f 38 40 c1 pmulld xmm0,xmm1
}
define <4 x i32> @test_mul_v4i32_more_regs(<4 x i1> %cond, <4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, <4 x i32> %arg4, <4 x i32> %arg5, <4 x i32> %arg6, <4 x i32> %arg7, <4 x i32> %arg8) {
......@@ -71,14 +70,14 @@ entry:
%res = select <4 x i1> %cond, <4 x i32> %res_acc1_3, <4 x i32> %res_acc2_4
ret <4 x i32> %res
; CHECK-LABEL: test_mul_v4i32_more_regs
; CHECK-DAG: 66 0f 38 40 c2 pmulld xmm0, xmm2
; CHECK-DAG: 66 0f 38 40 c3 pmulld xmm0, xmm3
; CHECK-DAG: 66 0f 38 40 c4 pmulld xmm0, xmm4
; CHECK-DAG: 66 0f 38 40 c5 pmulld xmm0, xmm5
; CHECK-DAG: 66 0f 38 40 c6 pmulld xmm0, xmm6
; CHECK-DAG: 66 0f 38 40 c7 pmulld xmm0, xmm7
; CHECK-DAG: 66 0f 38 40 44 24 70 pmulld xmm0, xmmword ptr [esp + 112]
; CHECK-DAG: 66 0f 38 40 8c 24 80 00 00 00 pmulld xmm1, xmmword ptr [esp + 128]
; CHECK-DAG: 66 0f 38 40 c2 pmulld xmm0,xmm2
; CHECK-DAG: 66 0f 38 40 c3 pmulld xmm0,xmm3
; CHECK-DAG: 66 0f 38 40 c4 pmulld xmm0,xmm4
; CHECK-DAG: 66 0f 38 40 c5 pmulld xmm0,xmm5
; CHECK-DAG: 66 0f 38 40 c6 pmulld xmm0,xmm6
; CHECK-DAG: 66 0f 38 40 c7 pmulld xmm0,xmm7
; CHECK-DAG: 66 0f 38 40 44 24 70 pmulld xmm0,XMMWORD PTR [esp
; CHECK-DAG: 66 0f 38 40 8c 24 80 00 00 00 pmulld xmm1,XMMWORD PTR [esp
}
; Test movq, which is used by atomic stores.
......@@ -95,9 +94,9 @@ entry:
ret void
}
; CHECK-LABEL: test_atomic_store_64
; CHECK-DAG: f3 0f 7e 04 24 movq xmm0, qword ptr [esp]
; CHECK-DAG: f3 0f 7e 44 24 08 movq xmm0, qword ptr [esp + 8]
; CHECK-DAG: 66 0f d6 0{{.*}} movq qword ptr [e{{.*}}], xmm0
; CHECK-DAG: f3 0f 7e 04 24 movq xmm0,QWORD PTR [esp]
; CHECK-DAG: f3 0f 7e 44 24 08 movq xmm0,QWORD PTR [esp
; CHECK-DAG: 66 0f d6 0{{.*}} movq QWORD PTR [e{{.*}}],xmm0
; Test "movups" via vector stores and loads.
define void @store_v16xI8(i32 %addr, i32 %addr2, i32 %addr3, <16 x i8> %v) {
......@@ -110,7 +109,7 @@ define void @store_v16xI8(i32 %addr, i32 %addr2, i32 %addr3, <16 x i8> %v) {
ret void
}
; CHECK-LABEL: store_v16xI8
; CHECK: 0f 11 0{{.*}} movups xmmword ptr [e{{.*}}], xmm0
; CHECK: 0f 11 0{{.*}} movups XMMWORD PTR [e{{.*}}],xmm0
define <16 x i8> @load_v16xI8(i32 %addr, i32 %addr2, i32 %addr3) {
%addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
......@@ -124,7 +123,7 @@ define <16 x i8> @load_v16xI8(i32 %addr, i32 %addr2, i32 %addr3) {
ret <16 x i8> %res123
}
; CHECK-LABEL: load_v16xI8
; CHECK: 0f 10 0{{.*}} movups xmm0, xmmword ptr [e{{.*}}]
; CHECK: 0f 10 0{{.*}} movups xmm0,XMMWORD PTR [e{{.*}}]
; Test segment override prefix. This happens w/ nacl.read.tp.
declare i8* @llvm.nacl.read.tp()
......@@ -154,11 +153,11 @@ entry:
ret i32 %v
}
; CHECK-LABEL: test_nacl_read_tp_more_addressing
; CHECK: 65 8b 05 00 00 00 00 mov eax, dword ptr gs:[0]
; CHECK: 8b 04 00 mov eax, dword ptr [eax + eax]
; CHECK: 65 8b 0d 00 00 00 00 mov ecx, dword ptr gs:[0]
; CHECK: 89 51 80 mov dword ptr [ecx - 128], edx
; CHECK: 89 91 00 01 00 00 mov dword ptr [ecx + 256], edx
; CHECK: 65 8b 05 00 00 00 00 mov eax,DWORD PTR gs:0x0
; CHECK: 8b 04 00 mov eax,DWORD PTR [eax+eax*1]
; CHECK: 65 8b 0d 00 00 00 00 mov ecx,DWORD PTR gs:0x0
; CHECK: 89 51 80 mov DWORD PTR [ecx-0x80],edx
; CHECK: 89 91 00 01 00 00 mov DWORD PTR [ecx+0x100],edx
; The 16-bit pinsrw/pextrw (SSE2) are quite different from
; the pinsr{b,d}/pextr{b,d} (SSE4.1).
......@@ -172,10 +171,10 @@ entry:
%res3 = insertelement <4 x i32> %res2, i32 %elt1, i32 3
ret <4 x i32> %res3
}
; CHECK-LABEL: test_pinsrd:
; CHECK-DAG: 66 0f 3a 22 c{{.*}} 01 pinsrd xmm0, e{{.*}}, 1
; CHECK-DAG: 66 0f 3a 22 c{{.*}} 02 pinsrd xmm0, e{{.*}}, 2
; CHECK-DAG: 66 0f 3a 22 c{{.*}} 03 pinsrd xmm0, e{{.*}}, 3
; CHECK-LABEL: test_pinsrd
; CHECK-DAG: 66 0f 3a 22 c{{.*}} 01 pinsrd xmm0,e{{.*}}
; CHECK-DAG: 66 0f 3a 22 c{{.*}} 02 pinsrd xmm0,e{{.*}}
; CHECK-DAG: 66 0f 3a 22 c{{.*}} 03 pinsrd xmm0,e{{.*}}
define <16 x i8> @test_pinsrb(<16 x i8> %vec, i32 %elt1_w, i32 %elt2_w, i32 %elt3_w, i32 %elt4_w) {
entry:
......@@ -190,10 +189,10 @@ entry:
%res3 = insertelement <16 x i8> %res2, i8 %elt1, i32 15
ret <16 x i8> %res3
}
; CHECK-LABEL: test_pinsrb:
; CHECK-DAG: 66 0f 3a 20 c{{.*}} 01 pinsrb xmm0, e{{.*}}, 1
; CHECK-DAG: 66 0f 3a 20 c{{.*}} 07 pinsrb xmm0, e{{.*}}, 7
; CHECK-DAG: 66 0f 3a 20 {{.*}} 0f pinsrb xmm0, byte ptr {{.*}}, 15
; CHECK-LABEL: test_pinsrb
; CHECK-DAG: 66 0f 3a 20 c{{.*}} 01 pinsrb xmm0,e{{.*}}
; CHECK-DAG: 66 0f 3a 20 c{{.*}} 07 pinsrb xmm0,e{{.*}}
; CHECK-DAG: 66 0f 3a 20 {{.*}} 0f pinsrb xmm0,BYTE PTR {{.*}}
define <8 x i16> @test_pinsrw(<8 x i16> %vec, i32 %elt1_w, i32 %elt2_w, i32 %elt3_w, i32 %elt4_w) {
entry:
......@@ -208,10 +207,10 @@ entry:
%res3 = insertelement <8 x i16> %res2, i16 %elt1, i32 7
ret <8 x i16> %res3
}
; CHECK-LABEL: test_pinsrw:
; CHECK-DAG: 66 0f c4 c{{.*}} 01 pinsrw xmm0, e{{.*}}, 1
; CHECK-DAG: 66 0f c4 c{{.*}} 04 pinsrw xmm0, e{{.*}}, 4
; CHECK-DAG: 66 0f c4 c{{.*}} 07 pinsrw xmm0, e{{.*}}, 7
; CHECK-LABEL: test_pinsrw
; CHECK-DAG: 66 0f c4 c{{.*}} 01 pinsrw xmm0,e{{.*}}
; CHECK-DAG: 66 0f c4 c{{.*}} 04 pinsrw xmm0,e{{.*}}
; CHECK-DAG: 66 0f c4 c{{.*}} 07 pinsrw xmm0,e{{.*}}
define i32 @test_pextrd(i32 %c, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4) {
entry:
......@@ -232,10 +231,10 @@ three:
ret i32 %res3
}
; CHECK-LABEL: test_pextrd
; CHECK-DAG: 66 0f 3a 16 c0 00 pextrd eax, xmm0, 0
; CHECK-DAG: 66 0f 3a 16 c8 01 pextrd eax, xmm1, 1
; CHECK-DAG: 66 0f 3a 16 d0 02 pextrd eax, xmm2, 2
; CHECK-DAG: 66 0f 3a 16 d8 03 pextrd eax, xmm3, 3
; CHECK-DAG: 66 0f 3a 16 c0 00 pextrd eax,xmm0
; CHECK-DAG: 66 0f 3a 16 c8 01 pextrd eax,xmm1
; CHECK-DAG: 66 0f 3a 16 d0 02 pextrd eax,xmm2
; CHECK-DAG: 66 0f 3a 16 d8 03 pextrd eax,xmm3
define i32 @test_pextrb(i32 %c, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4) {
entry:
......@@ -260,10 +259,10 @@ three:
ret i32 %res3_ext
}
; CHECK-LABEL: test_pextrb
; CHECK-DAG: 66 0f 3a 14 c0 00 pextrb eax, xmm0, 0
; CHECK-DAG: 66 0f 3a 14 c8 06 pextrb eax, xmm1, 6
; CHECK-DAG: 66 0f 3a 14 d0 0c pextrb eax, xmm2, 12
; CHECK-DAG: 66 0f 3a 14 d8 0f pextrb eax, xmm3, 15
; CHECK-DAG: 66 0f 3a 14 c0 00 pextrb eax,xmm0
; CHECK-DAG: 66 0f 3a 14 c8 06 pextrb eax,xmm1
; CHECK-DAG: 66 0f 3a 14 d0 0c pextrb eax,xmm2
; CHECK-DAG: 66 0f 3a 14 d8 0f pextrb eax,xmm3
define i32 @test_pextrw(i32 %c, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4) {
entry:
......@@ -288,7 +287,7 @@ three:
ret i32 %res3_ext
}
; CHECK-LABEL: test_pextrw
; CHECK-DAG: 66 0f c5 c0 00 pextrw eax, xmm0, 0
; CHECK-DAG: 66 0f c5 c1 02 pextrw eax, xmm1, 2
; CHECK-DAG: 66 0f c5 c2 05 pextrw eax, xmm2, 5
; CHECK-DAG: 66 0f c5 c3 07 pextrw eax, xmm3, 7
; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0
; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1
; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2
; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3
tests_lit/lit.cfg
......@@ -62,10 +62,13 @@ config.substitutions.append(('%{python}', sys.executable))
pydir = os.path.join(bin_root, 'pydir')
# Finding LLVM binary tools. All tools used in the tests must be listed in
# the llvmbintools list.
# Finding LLVM binary tools. Tools used in the tests must be listed in
# the llvmbintools list or binutilsbintools.
llvmbinpath = os.path.abspath(os.environ.get('LLVM_BIN_PATH'))
# Find binutils tools. This is used for objdump.
binutilsbinpath = os.path.abspath(os.environ.get('BINUTILS_BIN_PATH'))
# Define the location of the llvm2ice tool.
llvm2icetool = os.path.join(bin_root, 'llvm2ice')
llvm2iceatts = shellcmd(' '.join([llvm2icetool, '--build-atts']),
......@@ -88,7 +91,8 @@ iflc2i_atts_cmd = if_atts + [if_cond_flag('allow_llvm_ir_as_input'
# Base command for running llvm2ice
llvm2ice_cmd = [os.path.join(pydir, 'run-llvm2ice.py'),
'--llvm2ice', llvm2icetool,
'--llvm-bin-path', llvmbinpath]
'--llvm-bin-path', llvmbinpath,
'--binutils-bin-path', binutilsbinpath]
# Run commands only if corresponding build attributes apply, including
# for each compiler setup.
......@@ -109,7 +113,6 @@ config.substitutions.append(('%llvm2ice', llvm2icetool))
llvmbintools = [r"\bFileCheck\b",
r"\bllvm-as\b",
r"\bllvm-mc\b",
r"\bllvm-objdump\b",
r"\bllvm-readobj\b",
r"\bnot\b",
r"\bpnacl-freeze\b",
......@@ -126,6 +129,16 @@ for tool in llvmbintools:
tool)
config.substitutions.append((tool, substitution))
binutilsbintools = [r"\bobjdump\b",]
for tool in binutilsbintools:
# The re.sub() line is adapted from one of LLVM's lit.cfg files.
# Similar to the llvmbintools.
substitution = re.sub(r"^(\\)?((\| )?)\W+b([0-9A-Za-z-_]+)\\b\W*$",
r"\2" + binutilsbinpath + "/" + r"\4",
tool)
config.substitutions.append((tool, substitution))
# Add a feature to detect the Python version.
config.available_features.add("python%d.%d" % (sys.version_info[0],
sys.version_info[1]))
......@@ -136,4 +149,5 @@ def dbg(s):
dbg('bin_root = %s' % bin_root)
dbg('llvmbinpath = %s' % llvmbinpath)
dbg('binutilsbinpath = %s' % binutilsbinpath)
dbg("Build attributes = %s" % llvm2iceatts)
tests_lit/llvm2ice_tests/8bit.pnacl.ll
; This tries to be a comprehensive test of i8 operations.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
define internal i32 @add8Bit(i32 %a, i32 %b) {
entry:
......@@ -58,7 +56,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: mul8Bit
; CHECK: mul {{[abcd]l|byte ptr}}
; CHECK: mul {{[abcd]l|BYTE PTR}}
define internal i32 @mul8BitConst(i32 %a) {
entry:
......@@ -69,8 +67,8 @@ entry:
}
; CHECK-LABEL: mul8BitConst
; 8-bit imul only accepts r/m, not imm
; CHECK: mov {{.*}}, 56
; CHECK: mul {{[abcd]l|byte ptr}}
; CHECK: mov {{.*}},0x38
; CHECK: mul {{[abcd]l|BYTE PTR}}
define internal i32 @udiv8Bit(i32 %a, i32 %b) {
entry:
......@@ -81,7 +79,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: udiv8Bit
; CHECK: div {{[abcd]l|byte ptr}}
; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @udiv8BitConst(i32 %a) {
entry:
......@@ -91,7 +89,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: udiv8BitConst
; CHECK: div {{[abcd]l|byte ptr}}
; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @urem8Bit(i32 %a, i32 %b) {
entry:
......@@ -102,7 +100,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: urem8Bit
; CHECK: div {{[abcd]l|byte ptr}}
; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @urem8BitConst(i32 %a) {
entry:
......@@ -112,7 +110,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: urem8BitConst
; CHECK: div {{[abcd]l|byte ptr}}
; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @sdiv8Bit(i32 %a, i32 %b) {
......@@ -124,7 +122,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: sdiv8Bit
; CHECK: idiv {{[abcd]l|byte ptr}}
; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @sdiv8BitConst(i32 %a) {
entry:
......@@ -134,7 +132,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: sdiv8BitConst
; CHECK: idiv {{[abcd]l|byte ptr}}
; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @srem8Bit(i32 %a, i32 %b) {
entry:
......@@ -145,7 +143,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: srem8Bit
; CHECK: idiv {{[abcd]l|byte ptr}}
; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @srem8BitConst(i32 %a) {
entry:
......@@ -155,7 +153,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: srem8BitConst
; CHECK: idiv {{[abcd]l|byte ptr}}
; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @shl8Bit(i32 %a, i32 %b) {
entry:
......@@ -166,7 +164,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: shl8Bit
; CHECK: shl {{[abd]l|byte ptr}}, cl
; CHECK: shl {{[abd]l|BYTE PTR}},cl
define internal i32 @shl8BitConst(i32 %a, i32 %b) {
entry:
......@@ -176,7 +174,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: shl8BitConst
; CHECK: shl {{[abcd]l|byte ptr}}, 6
; CHECK: shl {{[abcd]l|BYTE PTR}},0x6
define internal i32 @lshr8Bit(i32 %a, i32 %b) {
entry:
......@@ -187,7 +185,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: lshr8Bit
; CHECK: shr {{[abd]l|byte ptr}}, cl
; CHECK: shr {{[abd]l|BYTE PTR}},cl
define internal i32 @lshr8BitConst(i32 %a, i32 %b) {
entry:
......@@ -197,7 +195,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: lshr8BitConst
; CHECK: shr {{[abcd]l|byte ptr}}, 6
; CHECK: shr {{[abcd]l|BYTE PTR}},0x6
define internal i32 @ashr8Bit(i32 %a, i32 %b) {
entry:
......@@ -208,7 +206,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: ashr8Bit
; CHECK: sar {{[abd]l|byte ptr}}, cl
; CHECK: sar {{[abd]l|BYTE PTR}},cl
define internal i32 @ashr8BitConst(i32 %a, i32 %b) {
entry:
......@@ -218,7 +216,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: ashr8BitConst
; CHECK: sar {{[abcd]l|byte ptr}}, 6
; CHECK: sar {{[abcd]l|BYTE PTR}},0x6
define internal i32 @icmp8Bit(i32 %a, i32 %b) {
entry:
......@@ -229,7 +227,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: icmp8Bit
; CHECK: cmp {{[abcd]l|byte ptr}}
; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitConst(i32 %a) {
entry:
......@@ -239,7 +237,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: icmp8BitConst
; CHECK: cmp {{[abcd]l|byte ptr}}
; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitConstSwapped(i32 %a) {
entry:
......@@ -249,7 +247,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: icmp8BitConstSwapped
; CHECK: cmp {{[abcd]l|byte ptr}}
; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitMem(i32 %a, i32 %b_iptr) {
entry:
......@@ -261,7 +259,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: icmp8BitMem
; CHECK: cmp {{[abcd]l|byte ptr}}
; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitMemSwapped(i32 %a, i32 %b_iptr) {
entry:
......@@ -273,7 +271,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: icmp8BitMemSwapped
; CHECK: cmp {{[abcd]l|byte ptr}}
; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @selectI8Var(i32 %a, i32 %b) {
entry:
......@@ -324,9 +322,9 @@ target:
}
; CHECK-LABEL: testPhi8
; This assumes there will be some copy from an 8-bit register / stack slot.
; CHECK-DAG: mov {{.*}}, {{[a-d]}}l
; CHECK-DAG: mov {{.*}}, byte ptr
; CHECK-DAG: mov byte ptr {{.*}}
; CHECK-DAG: mov {{.*}},{{[a-d]}}l
; CHECK-DAG: mov {{.*}},BYTE PTR
; CHECK-DAG: mov BYTE PTR {{.*}}
@global8 = internal global [1 x i8] c"\01", align 4
......@@ -338,7 +336,7 @@ entry:
ret i32 %ret_ext
}
; CHECK-LABEL: load_i8
; CHECK: mov {{[a-d]l}}, byte ptr
; CHECK: mov {{[a-d]l}},BYTE PTR
define i32 @load_i8_global(i32 %addr_arg) {
entry:
......@@ -348,7 +346,7 @@ entry:
ret i32 %ret_ext
}
; CHECK-LABEL: load_i8_global
; CHECK: mov {{[a-d]l}}, byte ptr
; CHECK: mov {{[a-d]l}},BYTE PTR
define void @store_i8(i32 %addr_arg, i32 %val) {
entry:
......@@ -358,7 +356,7 @@ entry:
ret void
}
; CHECK-LABEL: store_i8
; CHECK: mov byte ptr {{.*}}, {{[a-d]l}}
; CHECK: mov BYTE PTR {{.*}},{{[a-d]l}}
define void @store_i8_const(i32 %addr_arg) {
entry:
......@@ -367,4 +365,4 @@ entry:
ret void
}
; CHECK-LABEL: store_i8_const
; CHECK: mov byte ptr {{.*}}, 123
; CHECK: mov BYTE PTR {{.*}},0x7b
tests_lit/llvm2ice_tests/address-mode-opt.ll
; This file checks support for address mode optimization.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
define float @load_arg_plus_200000(float* %arg) {
entry:
......@@ -15,8 +12,8 @@ entry:
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_arg_plus_200000:
; CHECK: movss xmm0, dword ptr [eax + 200000]
; CHECK-LABEL: load_arg_plus_200000
; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
}
define float @load_200000_plus_arg(float* %arg) {
......@@ -26,8 +23,8 @@ entry:
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_200000_plus_arg:
; CHECK: movss xmm0, dword ptr [eax + 200000]
; CHECK-LABEL: load_200000_plus_arg
; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
}
define float @load_arg_minus_200000(float* %arg) {
......@@ -37,8 +34,8 @@ entry:
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_arg_minus_200000:
; CHECK: movss xmm0, dword ptr [eax - 200000]
; CHECK-LABEL: load_arg_minus_200000
; CHECK: movss xmm0,DWORD PTR [eax-0x30d40]
}
define float @load_200000_minus_arg(float* %arg) {
......@@ -48,8 +45,8 @@ entry:
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_200000_minus_arg:
; CHECK: movss xmm0, dword ptr [e{{..}}]
; CHECK-LABEL: load_200000_minus_arg
; CHECK: movss xmm0,DWORD PTR [e{{..}}]
}
define <8 x i16> @load_mul_v8i16_mem(<8 x i16> %arg0, i32 %arg1_iptr) {
......@@ -59,8 +56,8 @@ entry:
%arg1 = load <8 x i16>* %addr_ptr, align 2
%res_vec = mul <8 x i16> %arg0, %arg1
ret <8 x i16> %res_vec
; CHECK-LABEL: load_mul_v8i16_mem:
; CHECK: pmullw xmm{{.*}}, xmmword ptr [e{{.*}} - 200000]
; CHECK-LABEL: load_mul_v8i16_mem
; CHECK: pmullw xmm{{.*}},XMMWORD PTR [e{{.*}}-0x30d40]
}
define <4 x i32> @load_mul_v4i32_mem(<4 x i32> %arg0, i32 %arg1_iptr) {
......@@ -70,12 +67,12 @@ entry:
%arg1 = load <4 x i32>* %addr_ptr, align 4
%res = mul <4 x i32> %arg0, %arg1
ret <4 x i32> %res
; CHECK-LABEL: load_mul_v4i32_mem:
; CHECK: pmuludq xmm{{.*}}, xmmword ptr [e{{.*}} - 200000]
; CHECK-LABEL: load_mul_v4i32_mem
; CHECK: pmuludq xmm{{.*}},XMMWORD PTR [e{{.*}}-0x30d40]
; CHECK: pmuludq
;
; SSE41-LABEL: load_mul_v4i32_mem:
; SSE41: pmulld xmm{{.*}}, xmmword ptr [e{{.*}} - 200000]
; SSE41-LABEL: load_mul_v4i32_mem
; SSE41: pmulld xmm{{.*}},XMMWORD PTR [e{{.*}}-0x30d40]
}
define float @address_mode_opt_chaining(float* %arg) {
......@@ -86,8 +83,8 @@ entry:
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
; CHECK-LABEL: address_mode_opt_chaining:
; CHECK: movss xmm0, dword ptr [eax + 8]
; CHECK-LABEL: address_mode_opt_chaining
; CHECK: movss xmm0,DWORD PTR [eax+0x8]
}
define float @address_mode_opt_chaining_overflow(float* %arg) {
......@@ -98,9 +95,9 @@ entry:
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
; CHECK-LABEL: address_mode_opt_chaining_overflow:
; CHECK: 2147483640
; CHECK: movss xmm0, dword ptr [{{.*}} + 2147483643]
; CHECK-LABEL: address_mode_opt_chaining_overflow
; CHECK: 0x7ffffff8
; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x7ffffffb]
}
define float @address_mode_opt_chaining_overflow_sub(float* %arg) {
......@@ -111,9 +108,9 @@ entry:
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
; CHECK-LABEL: address_mode_opt_chaining_overflow_sub:
; CHECK: 2147483640
; CHECK: movss xmm0, dword ptr [{{.*}} - 2147483643]
; CHECK-LABEL: address_mode_opt_chaining_overflow_sub
; CHECK: 0x7ffffff8
; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x7ffffffb]
}
define float @address_mode_opt_chaining_no_overflow(float* %arg) {
......@@ -124,8 +121,8 @@ entry:
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
; CHECK-LABEL: address_mode_opt_chaining_no_overflow:
; CHECK: movss xmm0, dword ptr [{{.*}} + 3]
; CHECK-LABEL: address_mode_opt_chaining_no_overflow
; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x3]
}
define float @address_mode_opt_add_pos_min_int(float* %arg) {
......@@ -135,8 +132,8 @@ entry:
%addr1.ptr = inttoptr i32 %addr1.int to float*
%addr1.load = load float* %addr1.ptr, align 4
ret float %addr1.load
; CHECK-LABEL: address_mode_opt_add_pos_min_int:
; CHECK: movss xmm0, dword ptr [{{.*}} - 2147483648]
; CHECK-LABEL: address_mode_opt_add_pos_min_int
; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
}
define float @address_mode_opt_sub_min_int(float* %arg) {
......@@ -146,6 +143,6 @@ entry:
%addr1.ptr = inttoptr i32 %addr1.int to float*
%addr1.load = load float* %addr1.ptr, align 4
ret float %addr1.load
; CHECK-LABEL: address_mode_opt_sub_min_int:
; CHECK: movss xmm0, dword ptr [{{.*}} - 2147483648]
; CHECK-LABEL: address_mode_opt_sub_min_int
; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
}
tests_lit/llvm2ice_tests/align-spill-locations.ll
; This checks to ensure that Subzero aligns spill slots.
; RUN: %p2i -i %s --args --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; The location of the stack slot for a variable is inferred from the
; return sequence.
......@@ -21,9 +19,9 @@ entry:
block:
call void @ForceXmmSpills()
ret <4 x i32> %vec.global
; CHECK-LABEL: align_global_vector:
; CHECK: movups xmm0, xmmword ptr [esp]
; CHECK-NEXT: add esp, 28
; CHECK-LABEL: align_global_vector
; CHECK: movups xmm0,XMMWORD PTR [esp]
; CHECK-NEXT: add esp,0x1c
; CHECK-NEXT: ret
}
......@@ -34,9 +32,9 @@ block:
%vec.local = insertelement <4 x i32> undef, i32 %arg, i32 0
call void @ForceXmmSpills()
ret <4 x i32> %vec.local
; CHECK-LABEL: align_local_vector:
; CHECK: movups xmm0, xmmword ptr [esp]
; CHECK-NEXT: add esp, 28
; CHECK-LABEL: align_local_vector
; CHECK: movups xmm0,XMMWORD PTR [esp]
; CHECK-NEXT: add esp,0x1c
; CHECK-NEXT: ret
}
......@@ -50,9 +48,9 @@ entry:
block:
call void @ForceXmmSpillsAndUseAlloca(i8* %alloc)
ret <4 x i32> %vec.global
; CHECK-LABEL: align_global_vector_ebp_based:
; CHECK: movups xmm0, xmmword ptr [ebp - 24]
; CHECK-NEXT: mov esp, ebp
; CHECK-LABEL: align_global_vector_ebp_based
; CHECK: movups xmm0,XMMWORD PTR [ebp-0x18]
; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
; CHECK: ret
}
......@@ -63,9 +61,9 @@ entry:
%vec.local = insertelement <4 x i32> undef, i32 %arg, i32 0
call void @ForceXmmSpillsAndUseAlloca(i8* %alloc)
ret <4 x i32> %vec.local
; CHECK-LABEL: align_local_vector_ebp_based:
; CHECK: movups xmm0, xmmword ptr [ebp - 24]
; CHECK-NEXT: mov esp, ebp
; CHECK-LABEL: align_local_vector_ebp_based
; CHECK: movups xmm0,XMMWORD PTR [ebp-0x18]
; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
; CHECK: ret
}
......@@ -79,11 +77,11 @@ block:
%vec.local = insertelement <4 x i32> undef, i32 undef, i32 0
call void @ForceXmmSpillsAndUseFloat(float %float.global)
ret <4 x i32> %vec.local
; CHECK-LABEL: align_local_vector_and_global_float:
; CHECK: cvtsi2ss xmm0, eax
; CHECK-NEXT: movss dword ptr [esp + {{12|28}}], xmm0
; CHECK: movups xmm0, xmmword ptr [{{esp|esp \+ 16}}]
; CHECK-NEXT: add esp, 44
; CHECK-LABEL: align_local_vector_and_global_float
; CHECK: cvtsi2ss xmm0,eax
; CHECK-NEXT: movss DWORD PTR [esp+{{0xc|0x1c}}],xmm0
; CHECK: movups xmm0,XMMWORD PTR [{{esp|esp\+0x10}}]
; CHECK-NEXT: add esp,0x2c
; CHECK-NEXT: ret
}
......
tests_lit/llvm2ice_tests/alloc.ll
; This is a basic test of the alloca instruction.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
define void @fixed_416_align_16(i32 %n) {
entry:
......@@ -14,11 +12,11 @@ entry:
call void @f1(i32 %__2)
ret void
}
; CHECK-LABEL: fixed_416_align_16:
; CHECK: sub esp, 416
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f1
; CHECK-LABEL: fixed_416_align_16
; CHECK: sub esp,0x1a0
; CHECK: sub esp,0x10
; CHECK: mov DWORD PTR [esp],eax
; CHECK: call {{.*}} R_{{.*}} f1
define void @fixed_416_align_32(i32 %n) {
entry:
......@@ -27,12 +25,12 @@ entry:
call void @f1(i32 %__2)
ret void
}
; CHECK-LABEL: fixed_416_align_32:
; CHECK: and esp, -32
; CHECK: sub esp, 416
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f1
; CHECK-LABEL: fixed_416_align_32
; CHECK: and esp,0xffffffe0
; CHECK: sub esp,0x1a0
; CHECK: sub esp,0x10
; CHECK: mov DWORD PTR [esp],eax
; CHECK: call {{.*}} R_{{.*}} f1
define void @fixed_351_align_16(i32 %n) {
entry:
......@@ -41,11 +39,11 @@ entry:
call void @f1(i32 %__2)
ret void
}
; CHECK-LABEL: fixed_351_align_16:
; CHECK: sub esp, 352
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f1
; CHECK-LABEL: fixed_351_align_16
; CHECK: sub esp,0x160
; CHECK: sub esp,0x10
; CHECK: mov DWORD PTR [esp],eax
; CHECK: call {{.*}} R_{{.*}} f1
define void @fixed_351_align_32(i32 %n) {
entry:
......@@ -54,17 +52,14 @@ entry:
call void @f1(i32 %__2)
ret void
}
; CHECK-LABEL: fixed_351_align_32:
; CHECK: and esp, -32
; CHECK: sub esp, 352
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f1
; CHECK-LABEL: fixed_351_align_32
; CHECK: and esp,0xffffffe0
; CHECK: sub esp,0x160
; CHECK: sub esp,0x10
; CHECK: mov DWORD PTR [esp],eax
; CHECK: call {{.*}} R_{{.*}} f1
define void @f1(i32 %ignored) {
entry:
ret void
}
declare void @f1(i32 %ignored)
define void @variable_n_align_16(i32 %n) {
entry:
......@@ -73,14 +68,14 @@ entry:
call void @f2(i32 %__2)
ret void
}
; CHECK-LABEL: variable_n_align_16:
; CHECK: mov eax, dword ptr [ebp + 8]
; CHECK: add eax, 15
; CHECK: and eax, -16
; CHECK: sub esp, eax
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f2
; CHECK-LABEL: variable_n_align_16
; CHECK: mov eax,DWORD PTR [ebp+0x8]
; CHECK: add eax,0xf
; CHECK: and eax,0xfffffff0
; CHECK: sub esp,eax
; CHECK: sub esp,0x10
; CHECK: mov DWORD PTR [esp],eax
; CHECK: call {{.*}} R_{{.*}} f2
define void @variable_n_align_32(i32 %n) {
entry:
......@@ -90,15 +85,15 @@ entry:
ret void
}
; In -O2, the order of the CHECK-DAG lines in the output is switched.
; CHECK-LABEL: variable_n_align_32:
; CHECK-DAG: and esp, -32
; CHECK-DAG: mov eax, dword ptr [ebp + 8]
; CHECK: add eax, 31
; CHECK: and eax, -32
; CHECK: sub esp, eax
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f2
; CHECK-LABEL: variable_n_align_32
; CHECK-DAG: and esp,0xffffffe0
; CHECK-DAG: mov eax,DWORD PTR [ebp+0x8]
; CHECK: add eax,0x1f
; CHECK: and eax,0xffffffe0
; CHECK: sub esp,eax
; CHECK: sub esp,0x10
; CHECK: mov DWORD PTR [esp],eax
; CHECK: call {{.*}} R_{{.*}} f2
; Test alloca with default (0) alignment.
define void @align0(i32 %n) {
......@@ -109,11 +104,8 @@ entry:
ret void
}
; CHECK-LABEL: align0
; CHECK: add [[REG:.*]], 15
; CHECK: and [[REG]], -16
; CHECK: sub esp, [[REG]]
; CHECK: add [[REG:.*]],0xf
; CHECK: and [[REG]],0xfffffff0
; CHECK: sub esp,[[REG]]
define void @f2(i32 %ignored) {
entry:
ret void
}
declare void @f2(i32 %ignored)
\ No newline at end of file
tests_lit/llvm2ice_tests/bitcast.ll
; Trivial smoke test of bitcast between integer and FP types.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
define internal i32 @cast_f2i(float %f) {
entry:
......@@ -22,7 +20,7 @@ entry:
ret float %v0
}
; CHECK-LABEL: cast_i2f
; CHECK: fld dword ptr
; CHECK: fld DWORD PTR
; CHECK: ret
define internal i64 @cast_d2ll(double %d) {
......@@ -40,7 +38,7 @@ entry:
ret i64 %v0
}
; CHECK-LABEL: cast_d2ll_const
; CHECK: movsd xmm{{.*}}, qword ptr
; CHECK: movsd xmm{{.*}},QWORD PTR
; CHECK: mov edx
; CHECK: ret
......@@ -50,7 +48,7 @@ entry:
ret double %v0
}
; CHECK-LABEL: cast_ll2d
; CHECK: fld qword ptr
; CHECK: fld QWORD PTR
; CHECK: ret
define internal double @cast_ll2d_const() {
......@@ -59,7 +57,7 @@ entry:
ret double %v0
}
; CHECK-LABEL: cast_ll2d_const
; CHECK: mov {{.*}}, 1942892530
; CHECK: mov {{.*}}, 2874
; CHECK: fld qword ptr
; CHECK: mov {{.*}},0x73ce2ff2
; CHECK: mov {{.*}},0xb3a
; CHECK: fld QWORD PTR
; CHECK: ret
tests_lit/llvm2ice_tests/branch-opt.ll
; Tests the branch optimizations under O2 (against a lack of
; optimizations under Om1).
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=O2 %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OM1 %s
declare void @dummy()
......@@ -47,7 +43,7 @@ target:
ret void
}
; O2-LABEL: testCondFallthroughToNextBlock
; O2: cmp {{.*}}, 123
; O2: cmp {{.*}},0x7b
; O2-NEXT: jge
; O2-NOT: j
; O2: call
......@@ -56,7 +52,7 @@ target:
; O2: ret
; OM1-LABEL: testCondFallthroughToNextBlock
; OM1: cmp {{.*}}, 123
; OM1: cmp {{.*}},0x7b
; OM1: jge
; OM1: cmp
; OM1: jne
......@@ -82,7 +78,7 @@ target:
ret void
}
; O2-LABEL: testCondTargetNextBlock
; O2: cmp {{.*}}, 123
; O2: cmp {{.*}},0x7b
; O2-NEXT: jl
; O2-NOT: j
; O2: call
......@@ -91,7 +87,7 @@ target:
; O2: ret
; OM1-LABEL: testCondTargetNextBlock
; OM1: cmp {{.*}}, 123
; OM1: cmp {{.*}},0x7b
; OM1: jge
; OM1: cmp
; OM1: jne
......
tests_lit/llvm2ice_tests/callindirect.pnacl.ll
......@@ -2,12 +2,9 @@
; should be to the same operand, whether it's in a register or on the
; stack.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
......
tests_lit/llvm2ice_tests/cmp-opt.ll
; Simple test of non-fused compare/branch.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
define void @testBool(i32 %a, i32 %b) {
......
tests_lit/llvm2ice_tests/convert.ll
; Simple test of signed and unsigned integer conversions.
; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
; have [0] == i8v, [2] == i16v, [4] == i32v, [8] == i64v, etc.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
@i8v = internal global [1 x i8] zeroinitializer, align 1
@i16v = internal global [2 x i8] zeroinitializer, align 2
......@@ -35,16 +30,16 @@ entry:
ret void
}
; CHECK-LABEL: from_int8
; CHECK: mov {{.*}}, byte ptr [
; CHECK: movsx e{{.*}}, {{[a-d]l|byte ptr}}
; CHECK: mov word ptr [
; CHECK: mov {{.*}},BYTE PTR
; CHECK: movsx e{{.*}},{{[a-d]l|BYTE PTR}}
; CHECK: mov WORD PTR
; CHECK: movsx
; CHECK: mov dword ptr [
; CHECK: mov DWORD PTR
; CHECK: movsx
; CHECK: sar {{.*}}, 31
; CHECK: sar {{.*}},0x1f
; This appears to be a bug in llvm-mc. It should be i64v and i64+4.
; CHECK-DAG: [.bss]
; CHECK-DAG: [.bss]
; CHECK-DAG: .bss
; CHECK-DAG: .bss
define void @from_int16() {
entry:
......@@ -62,13 +57,13 @@ entry:
ret void
}
; CHECK-LABEL: from_int16
; CHECK: mov {{.*}}, word ptr [
; CHECK: [.bss]
; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
; CHECK: [.bss]
; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
; CHECK: sar {{.*}}, 31
; CHECK: [.bss]
; CHECK: mov {{.*}},WORD PTR
; CHECK: .bss
; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
; CHECK: .bss
; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
; CHECK: sar {{.*}},0x1f
; CHECK: .bss
define void @from_int32() {
entry:
......@@ -86,11 +81,11 @@ entry:
ret void
}
; CHECK-LABEL: from_int32
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: sar {{.*}}, 31
; CHECK: [.bss]
; CHECK: .bss
; CHECK: .bss
; CHECK: .bss
; CHECK: sar {{.*}},0x1f
; CHECK: .bss
define void @from_int64() {
entry:
......@@ -108,10 +103,10 @@ entry:
ret void
}
; CHECK-LABEL: from_int64
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: .bss
; CHECK: .bss
; CHECK: .bss
; CHECK: .bss
define void @from_uint8() {
......@@ -130,14 +125,14 @@ entry:
ret void
}
; CHECK-LABEL: from_uint8
; CHECK: [.bss]
; CHECK: movzx e{{.*}}, {{[a-d]l|byte ptr}}
; CHECK: [.bss]
; CHECK: .bss
; CHECK: movzx e{{.*}},{{[a-d]l|BYTE PTR}}
; CHECK: .bss
; CHECK: movzx
; CHECK: [.bss]
; CHECK: .bss
; CHECK: movzx
; CHECK: mov {{.*}}, 0
; CHECK: [.bss]
; CHECK: mov {{.*}},0x0
; CHECK: .bss
define void @from_uint16() {
entry:
......@@ -155,13 +150,13 @@ entry:
ret void
}
; CHECK-LABEL: from_uint16
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
; CHECK: [.bss]
; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
; CHECK: mov {{.*}}, 0
; CHECK: [.bss]
; CHECK: .bss
; CHECK: .bss
; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
; CHECK: .bss
; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
; CHECK: mov {{.*}},0x0
; CHECK: .bss
define void @from_uint32() {
entry:
......@@ -179,11 +174,11 @@ entry:
ret void
}
; CHECK-LABEL: from_uint32
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: mov {{.*}}, 0
; CHECK: [.bss]
; CHECK: .bss
; CHECK: .bss
; CHECK: .bss
; CHECK: mov {{.*}},0x0
; CHECK: .bss
define void @from_uint64() {
entry:
......@@ -201,7 +196,7 @@ entry:
ret void
}
; CHECK-LABEL: from_uint64
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: [.bss]
; CHECK: .bss
; CHECK: .bss
; CHECK: .bss
; CHECK: .bss
tests_lit/llvm2ice_tests/div_legalization.ll
; This is a regression test that idiv and div operands are legalized
; (they cannot be constants and can only be reg/mem for x86).
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
define i32 @Sdiv_const8_b(i8 %a) {
; CHECK-LABEL: Sdiv_const8_b
entry:
%div = sdiv i8 %a, 12
; CHECK: mov {{.*}}, 12
; CHECK-NOT: idiv 12
; CHECK: mov {{.*}},0xc
; CHECK-NOT: idiv 0xc
%div_ext = sext i8 %div to i32
ret i32 %div_ext
}
......@@ -22,8 +20,8 @@ define i32 @Sdiv_const16_b(i16 %a) {
; CHECK-LABEL: Sdiv_const16_b
entry:
%div = sdiv i16 %a, 1234
; CHECK: mov {{.*}}, 1234
; CHECK-NOT: idiv 1234
; CHECK: mov {{.*}},0x4d2
; CHECK-NOT: idiv 0x4d2
%div_ext = sext i16 %div to i32
ret i32 %div_ext
}
......@@ -32,8 +30,8 @@ define i32 @Sdiv_const32_b(i32 %a) {
; CHECK-LABEL: Sdiv_const32_b
entry:
%div = sdiv i32 %a, 1234
; CHECK: mov {{.*}}, 1234
; CHECK-NOT: idiv 1234
; CHECK: mov {{.*}},0x4d2
; CHECK-NOT: idiv 0x4d2
ret i32 %div
}
......@@ -41,8 +39,8 @@ define i32 @Srem_const_b(i32 %a) {
; CHECK-LABEL: Srem_const_b
entry:
%rem = srem i32 %a, 2345
; CHECK: mov {{.*}}, 2345
; CHECK-NOT: idiv 2345
; CHECK: mov {{.*}},0x929
; CHECK-NOT: idiv 0x929
ret i32 %rem
}
......@@ -50,8 +48,8 @@ define i32 @Udiv_const_b(i32 %a) {
; CHECK-LABEL: Udiv_const_b
entry:
%div = udiv i32 %a, 3456
; CHECK: mov {{.*}}, 3456
; CHECK-NOT: div 3456
; CHECK: mov {{.*}},0xd80
; CHECK-NOT: div 0xd80
ret i32 %div
}
......@@ -59,7 +57,7 @@ define i32 @Urem_const_b(i32 %a) {
; CHECK-LABEL: Urem_const_b
entry:
%rem = urem i32 %a, 4567
; CHECK: mov {{.*}}, 4567
; CHECK-NOT: div 4567
; CHECK: mov {{.*}},0x11d7
; CHECK-NOT: div 0x11d7
ret i32 %rem
}
tests_lit/llvm2ice_tests/ebp_args.ll
......@@ -3,9 +3,8 @@
; adjustment was incorrectly added to the stack/frame offset for
; ebp-based frames.
; RUN: %p2i -i %s --args -Om1 --target=x8632 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
declare i32 @memcpy_helper2(i32 %buf, i32 %buf2, i32 %n)
......@@ -13,9 +12,9 @@ define i32 @memcpy_helper(i32 %buf, i32 %n) {
entry:
%buf2 = alloca i8, i32 128, align 4
%n.arg_trunc = trunc i32 %n to i8
%arg_ext = zext i8 %n.arg_trunc to i32
%arg.ext = zext i8 %n.arg_trunc to i32
%buf2.asint = ptrtoint i8* %buf2 to i32
%call = call i32 @memcpy_helper2(i32 %buf, i32 %buf2.asint, i32 %arg_ext)
%call = call i32 @memcpy_helper2(i32 %buf, i32 %buf2.asint, i32 %arg.ext)
ret i32 %call
}
......@@ -23,21 +22,21 @@ entry:
; and stack slot assignment code, and may need to be relaxed if the
; lowering code changes.
; CHECK-LABEL: memcpy_helper:
; CHECK-LABEL: memcpy_helper
; CHECK: push ebp
; CHECK: mov ebp, esp
; CHECK: sub esp, 24
; CHECK: sub esp, 128
; CHECK: mov dword ptr [ebp - 4], esp
; CHECK: mov eax, dword ptr [ebp + 12]
; CHECK: mov dword ptr [ebp - 8], eax
; CHECK: movzx eax, byte ptr [ebp - 8]
; CHECK: mov dword ptr [ebp - 12], eax
; CHECK: sub esp, 16
; CHECK: mov eax, dword ptr [ebp + 8]
; CHECK: mov dword ptr [esp], eax
; CHECK: mov eax, dword ptr [ebp - 4]
; CHECK: mov dword ptr [esp + 4], eax
; CHECK: mov eax, dword ptr [ebp - 12]
; CHECK: mov dword ptr [esp + 8], eax
; CHECK: call memcpy_helper2
; CHECK: mov ebp,esp
; CHECK: sub esp,0x18
; CHECK: sub esp,0x80
; CHECK: mov DWORD PTR [ebp-0x4],esp
; CHECK: mov eax,DWORD PTR [ebp+0xc]
; CHECK: mov DWORD PTR [ebp-0x8],eax
; CHECK: movzx eax,BYTE PTR [ebp-0x8]
; CHECK: mov DWORD PTR [ebp-0xc],eax
; CHECK: sub esp,0x10
; CHECK: mov eax,DWORD PTR [ebp+0x8]
; CHECK: mov DWORD PTR [esp],eax
; CHECK: mov eax,DWORD PTR [ebp-0x4]
; CHECK: mov DWORD PTR [esp+0x4],eax
; CHECK: mov eax,DWORD PTR [ebp-0xc]
; CHECK: mov DWORD PTR [esp+0x8],eax
; CHECK: call {{.*}} R_{{.*}} memcpy_helper2
tests_lit/llvm2ice_tests/elf_container.ll
......@@ -14,7 +14,7 @@
; Add a run that shows relocations in code inline.
; RUN: %p2i -i %s --args -O2 --verbose none -filetype=obj -o %t \
; RUN: && llvm-objdump -d -r -x86-asm-syntax=intel %t \
; RUN: && objdump -w -d -r -Mintel %t \
; RUN: | FileCheck --check-prefix=TEXT-RELOCS %s
; Use intrinsics to test external calls.
......@@ -53,10 +53,8 @@ entry:
ret float %f
}
; TEXT-RELOCS-LABEL: returnFloatConst
; TEXT-RELOCS: movss
; TEXT-RELOCS-NEXT: R_386_32 .L$float$0
; TEXT-RELOCS: addss
; TEXT-RELOCS-NEXT: R_386_32 .L$float$1
; TEXT-RELOCS: movss {{.*}} R_386_32 .L$float$0
; TEXT-RELOCS: addss {{.*}} R_386_32 .L$float$1
define internal double @returnDoubleConst() {
entry:
......@@ -65,12 +63,9 @@ entry:
ret double %d2
}
; TEXT-RELOCS-LABEL: returnDoubleConst
; TEXT-RELOCS: movsd
; TEXT-RELOCS-NEXT: R_386_32 .L$double$0
; TEXT-RELOCS: addsd
; TEXT-RELOCS-NEXT: R_386_32 .L$double$1
; TEXT-RELOCS: addsd
; TEXT-RELOCS-NEXT: R_386_32 .L$double$2
; TEXT-RELOCS: movsd {{.*}} R_386_32 .L$double$0
; TEXT-RELOCS: addsd {{.*}} R_386_32 .L$double$1
; TEXT-RELOCS: addsd {{.*}} R_386_32 .L$double$2
; Test intrinsics that call out to external functions.
define internal void @test_memcpy(i32 %iptr_dst, i32 %len) {
......@@ -82,8 +77,7 @@ entry:
ret void
}
; TEXT-RELOCS-LABEL: test_memcpy
; TEXT-RELOCS: mov
; TEXT-RELOCS: R_386_32 bytes
; TEXT-RELOCS: mov {{.*}} R_386_32 bytes
define internal void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
entry:
......@@ -114,16 +108,14 @@ define internal i32 @test_ret_fp() {
ret i32 %r
}
; TEXT-RELOCS-LABEL: test_ret_fp
; TEXT-RELOCS-NEXT: mov
; TEXT-RELOCS-NEXT: R_386_32 returnFloatConst
; TEXT-RELOCS-NEXT: mov {{.*}} R_386_32 returnFloatConst
define internal i32 @test_ret_global_pointer() {
%r = ptrtoint [7 x i8]* @bytes to i32
ret i32 %r
}
; TEXT-RELOCS-LABEL: test_ret_global_pointer
; TEXT-RELOCS-NEXT: mov
; TEXT-RELOCS-NEXT: R_386_32 bytes
; TEXT-RELOCS-NEXT: mov {{.*}} R_386_32 bytes
; Test defining a non-internal function.
define void @_start(i32) {
......
tests_lit/llvm2ice_tests/fpcall.ll
......@@ -3,18 +3,12 @@
; particular, the top-of-stack must be popped regardless of whether
; its value is used.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck %s
define float @dummy() {
entry:
ret float 0.000000e+00
}
; CHECK-LABEL: dummy
declare float @dummy()
; The call is ignored, but the top of the FP stack still needs to be
; popped.
......@@ -24,7 +18,7 @@ entry:
ret i32 0
}
; CHECK-LABEL: ignored_fp_call
; CHECK: call dummy
; CHECK: call {{.*}} R_{{.*}} dummy
; CHECK: fstp
; The top of the FP stack is popped and subsequently used.
......@@ -35,7 +29,7 @@ entry:
ret i32 %ret
}
; CHECK-LABEL: converted_fp_call
; CHECK: call dummy
; CHECK: call {{.*}} R_{{.*}} dummy
; CHECK: fstp
; CHECK: cvttss2si
......@@ -48,6 +42,6 @@ entry:
ret float %fp
}
; CHECK-LABEL: returned_fp_call
; CHECK: call dummy
; CHECK: call {{.*}} R_{{.*}} dummy
; CHECK: fstp
; CHECK: fld
tests_lit/llvm2ice_tests/fpconst.pnacl.ll
......@@ -6,12 +6,10 @@
; number in a reasonable number of digits". See
; http://llvm.org/docs/LangRef.html#simple-constants .
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -s -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -s -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble --dis-flags=-s -i %s --args -O2 \
; RUN: --verbose none | FileCheck %s
; RUN: %p2i --assemble --disassemble --dis-flags=-s -i %s --args -Om1 \
; RUN: --verbose none | FileCheck %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
......@@ -549,4 +547,4 @@ return: ; preds = %entry, %sw.bb65, %s
; CHECK-LABEL: .rodata.cst8
; CHECK: 00000000 0000e03f
; CHECK-NOT: 00000000 0000e03f
; CHECK-LABEL: .shstrtab
; CHECK-LABEL: .text
tests_lit/llvm2ice_tests/function_aligned.ll
......@@ -3,9 +3,8 @@
; but typically you want to align functions anyway.
; Also, we are currently using hlts for non-executable padding.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck %s
define void @foo() {
ret void
......
tests_lit/llvm2ice_tests/globalinit.pnacl.ll
......@@ -8,14 +8,10 @@
; Test -filetype=iasm and try to cross reference instructions w/ the
; symbol table.
; RUN: %p2i -i %s --args --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -r --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i --assemble --disassemble -i %s --args --verbose none \
; RUN: | FileCheck --check-prefix=IAS %s
; RUN: %p2i -i %s --args --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -t --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SYMTAB %s
; RUN: %p2i --assemble --disassemble --dis-flags=-t -i %s --args \
; RUN: --verbose none | FileCheck --check-prefix=SYMTAB %s
@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
; CHECK: .type PrimitiveInit,@object
......@@ -121,46 +117,39 @@ entry:
; CHECK: movl $ArrayInitPartial,
; CHECK: movl $ArrayUninit,
; llvm-objdump does not indicate what symbol the mov/relocation applies to
; so we grep for "mov {{.*}}, OFFSET", along with "OFFSET {{.*}} symbol" in
; the symbol table as a sanity check. NOTE: The symbol table sorting has no
; relation to the code's references.
; objdump does not indicate what symbol the mov/relocation applies to
; so we grep for "mov {{.*}}, OFFSET, sec", along with
; "OFFSET {{.*}} sec {{.*}} symbol" in the symbol table as a sanity check.
; NOTE: The symbol table sorting has no relation to the code's references.
; IAS-LABEL: main
; SYMTAB-LABEL: SYMBOL TABLE
; SYMTAB-DAG: 00000000 {{.*}} .data {{.*}} PrimitiveInit
; IAS: mov {{.*}}, .data
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x0 {{.*}} .data
; IAS: call
; SYMTAB-DAG: 00000000 {{.*}} .rodata {{.*}} PrimitiveInitConst
; IAS: mov {{.*}}, .rodata
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x0 {{.*}} .rodata
; IAS: call
; SYMTAB-DAG: 00000000 {{.*}} .bss {{.*}} PrimitiveInitStatic
; IAS: mov {{.*}}, .bss
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x0 {{.*}} .bss
; IAS: call
; SYMTAB-DAG: 00000004 {{.*}} .bss {{.*}} PrimitiveUninit
; IAS: mov {{.*}}, .bss
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x4 {{.*}} .bss
; IAS: call
; SYMTAB-DAG: 00000004{{.*}}.data{{.*}}ArrayInit
; IAS: mov {{.*}}, .data
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x4 {{.*}} .data
; IAS: call
; SYMTAB-DAG: 00000018 {{.*}} .data {{.*}} ArrayInitPartial
; IAS: mov {{.*}}, .data
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x18 {{.*}} .data
; IAS: call
; SYMTAB-DAG: 00000008 {{.*}} .bss {{.*}} ArrayUninit
; IAS: mov {{.*}}, .bss
; IAS-NEXT: R_386_32
; IAS: mov {{.*}},0x8 {{.*}} .bss
; IAS: call
......
tests_lit/llvm2ice_tests/mangle.ll
......@@ -4,10 +4,10 @@
; REQUIRES: allow_dump
; RUN: %p2i -i %s --args --verbose none -ffunction-sections | FileCheck %s
; TODO(stichnot): The following line causes this test to fail.
; RUIN: %p2i -i %s --args --verbose none \
; RUIN: | llvm-mc -triple=i686-none-nacl -filetype=obj
; RUIN: %p2i --assemble --disassemble -i %s --args --verbose none \
; RUIN: | FileCheck %s
; RUN: %p2i -i %s --args --verbose none --prefix Subzero -ffunction-sections \
; RUN: | FileCheck --check-prefix=MANGLE %s
; RUN: | FileCheck --check-prefix=MANGLE %s
define internal void @FuncC(i32 %i) {
entry:
......
tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
; This tests the optimization of atomic cmpxchg w/ following cmp + branches.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=O2 %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OM1 %s
declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
......@@ -36,16 +32,14 @@ done:
ret i32 %succeeded_first_try
}
; O2-LABEL: test_atomic_cmpxchg_loop
; O2: lock
; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2-NEXT: j{{e|ne}}
; Make sure the call isn't accidentally deleted.
; O2: call
;
; Check that the unopt version does have a cmp
; OM1-LABEL: test_atomic_cmpxchg_loop
; OM1: lock
; OM1-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; OM1: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; OM1: cmp
; OM1: je
; OM1: call
......@@ -67,8 +61,7 @@ done:
ret i32 %old
}
; O2-LABEL: test_atomic_cmpxchg_loop2
; O2: lock
; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2-NOT: cmp
; O2: jne
......@@ -90,8 +83,7 @@ done:
ret i32 %succeeded_first_try
}
; O2-LABEL: test_atomic_cmpxchg_loop_const
; O2: lock
; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2-NEXT: j{{e|ne}}
; This is a case where the flags cannot be reused (compare is for some
......@@ -112,8 +104,7 @@ done:
ret i32 %old
}
; O2-LABEL: test_atomic_cmpxchg_no_opt
; O2: lock
; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2: cmp
; O2: jle
......@@ -136,8 +127,7 @@ done:
ret i32 %r
}
; O2-LABEL: test_atomic_cmpxchg_no_opt2
; O2: lock
; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2: mov {{.*}}
; O2: cmp
; O2: je
tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
......@@ -3,12 +3,8 @@
; (unlike the non-"all" variety of nacl.atomic.fence, which only
; applies to atomic load/stores).
;
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -r -symbolize -x86-asm-syntax=intel - | FileCheck %s
; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
; have 0 == g32_a, 4 == g32_b, 8 == g32_c, 12 == g32_d
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
declare void @llvm.nacl.atomic.fence.all()
declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
......@@ -45,21 +41,18 @@ entry:
}
; CHECK-LABEL: test_fused_load_add_a
; alloca store
; CHECK: mov {{.*}}, esp
; CHECK: mov dword ptr {{.*}}, 999
; CHECK: mov {{.*}},esp
; CHECK: mov DWORD PTR {{.*}},0x3e7
; atomic store (w/ its own mfence)
; The load + add are optimized into one everywhere.
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; CHECK: mfence
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mfence
; CHECK: mov dword ptr
; CHECK: mov DWORD PTR
; Test with the fence moved up a bit.
define i32 @test_fused_load_add_b() {
......@@ -88,22 +81,19 @@ entry:
}
; CHECK-LABEL: test_fused_load_add_b
; alloca store
; CHECK: mov {{.*}}, esp
; CHECK: mov dword ptr {{.*}}, 999
; CHECK: mov {{.*}},esp
; CHECK: mov DWORD PTR {{.*}},0x3e7
; atomic store (w/ its own mfence)
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; CHECK: mfence
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; CHECK: mfence
; Load + add can still be optimized into one instruction
; because it is not separated by a fence.
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; Test with the fence splitting a load/add.
define i32 @test_fused_load_add_c() {
......@@ -132,24 +122,21 @@ entry:
}
; CHECK-LABEL: test_fused_load_add_c
; alloca store
; CHECK: mov {{.*}}, esp
; CHECK: mov dword ptr {{.*}}, 999
; CHECK: mov {{.*}},esp
; CHECK: mov DWORD PTR {{.*}},0x3e7
; atomic store (w/ its own mfence)
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; CHECK: mfence
; This load + add are no longer optimized into one,
; though perhaps it should be legal as long as
; the load stays on the same side of the fence.
; CHECK: mov {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mfence
; CHECK: add {{.*}}, 1
; CHECK: mov dword ptr
; CHECK: add {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov dword ptr
; CHECK: add {{.*}},0x1
; CHECK: mov DWORD PTR
; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mov DWORD PTR
; Test where a bunch of i8 loads could have been fused into one
......@@ -187,12 +174,11 @@ entry:
ret i32 %b1234
}
; CHECK-LABEL: could_have_fused_loads
; CHECK: mov {{.*}}, byte ptr
; CHECK-NEXT: R_386_32
; CHECK: mov {{.*}}, byte ptr
; CHECK: mov {{.*}}, byte ptr
; CHECK: mov {{.*}},BYTE PTR
; CHECK: mov {{.*}},BYTE PTR
; CHECK: mov {{.*}},BYTE PTR
; CHECK: mfence
; CHECK: mov {{.*}}, byte ptr
; CHECK: mov {{.*}},BYTE PTR
; Test where an identical load from two branches could have been hoisted
......@@ -212,10 +198,8 @@ branch2:
}
; CHECK-LABEL: could_have_hoisted_loads
; CHECK: jne {{.*}}
; CHECK: mov {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov {{.*}},DWORD PTR {{.*}}.bss
; CHECK: ret
; CHECK: mfence
; CHECK: mov {{.*}}, dword ptr [.bss]
; CHECK-NEXT: R_386_32
; CHECK: mov {{.*}},DWORD PTR {{.*}}.bss
; CHECK: ret
tests_lit/llvm2ice_tests/nop-insertion.ll
......@@ -18,7 +18,7 @@ define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
entry:
%res = mul <4 x i32> %a, %b
ret <4 x i32> %res
; PROB50-LABEL: mul_v4i32:
; PROB50-LABEL: mul_v4i32
; PROB50: nop # variant = 3
; PROB50: subl $60, %esp
; PROB50: nop # variant = 4
......@@ -41,7 +41,7 @@ entry:
; PROB50: nop # variant = 0
; PROB50: ret
; PROB90-LABEL: mul_v4i32:
; PROB90-LABEL: mul_v4i32
; PROB90: nop # variant = 3
; PROB90: subl $60, %esp
; PROB90: nop # variant = 4
......@@ -71,7 +71,7 @@ entry:
; PROB90: nop # variant = 3
; PROB90: ret
; MAXNOPS2-LABEL: mul_v4i32:
; MAXNOPS2-LABEL: mul_v4i32
; MAXNOPS2: subl $60, %esp
; MAXNOPS2: nop # variant = 4
; MAXNOPS2: movups %xmm0, 32(%esp)
......
tests_lit/llvm2ice_tests/phi.ll
......@@ -2,9 +2,9 @@
; it tests that it does the right thing when it tries to enable
; compare/branch fusing.
; RUN: %p2i -i %s --args -O2 --verbose none --phi-edge-split=0 \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: --phi-edge-split=0 \
; RUN: | FileCheck %s
define internal i32 @testPhi1(i32 %arg) {
entry:
......@@ -20,15 +20,15 @@ target:
; Test that compare/branch fusing does not happen, and Phi lowering is
; put in the right place.
; CHECK-LABEL: testPhi1
; CHECK: cmp {{.*}}, 0
; CHECK: mov {{.*}}, 1
; CHECK: cmp {{.*}},0x0
; CHECK: mov {{.*}},0x1
; CHECK: jg
; CHECK: mov {{.*}}, 0
; CHECK: mov {{.*}},0x0
; CHECK: mov [[PHI:.*]],
; CHECK: cmp {{.*}}, 0
; CHECK: cmp {{.*}},0x0
; CHECK: je
; CHECK: mov [[PHI]], 0
; CHECK: movzx {{.*}}, [[PHI]]
; CHECK: mov [[PHI]],0x0
; CHECK: movzx {{.*}},[[PHI]]
define internal i32 @testPhi2(i32 %arg) {
entry:
......@@ -42,11 +42,11 @@ target:
}
; Test that compare/branch fusing and Phi lowering happens as expected.
; CHECK-LABEL: testPhi2
; CHECK: mov {{.*}}, 12345
; CHECK: cmp {{.*}}, 0
; CHECK: mov {{.*}},0x3039
; CHECK: cmp {{.*}},0x0
; CHECK-NEXT: jle
; CHECK: mov [[PHI:.*]], 54321
; CHECK: mov {{.*}}, [[PHI]]
; CHECK: mov [[PHI:.*]],0xd431
; CHECK: mov {{.*}},[[PHI]]
; Test that address mode inference doesn't extend past
; multi-definition, non-SSA Phi temporaries.
......@@ -77,14 +77,14 @@ exit:
;
; testPhi3:
; .LtestPhi3$entry:
; mov eax, dword ptr [esp+4]
; mov eax, DWORD PTR [esp+4]
; mov ecx, eax
; .LtestPhi3$body:
; mov ecx, dword ptr [ecx+1000]
; mov ecx, DWORD PTR [ecx+1000]
; cmp ecx, 0
; jne .LtestPhi3$body
; .LtestPhi3$exit:
; mov dword ptr [ecx+1000], eax
; mov DWORD PTR [ecx+1000], eax
; ret
;
; This is bad because the final store address is supposed to be the
......@@ -93,10 +93,10 @@ exit:
; CHECK-LABEL: testPhi3
; CHECK: push [[EBX:.*]]
; CHECK: mov {{.*}}, dword ptr [esp
; CHECK: mov {{.*}},DWORD PTR [esp
; CHECK: mov
; CHECK: mov {{.*}}, dword ptr [[ADDR:.*1000]]
; CHECK: cmp {{.*}}, 0
; CHECK: mov {{.*}},DWORD PTR [[ADDR:.*0x3e8]]
; CHECK: cmp {{.*}},0x0
; CHECK: jne
; CHECK: mov dword ptr [[ADDR]]
; CHECK: mov DWORD PTR [[ADDR]]
; CHECK: pop [[EBX]]
tests_lit/llvm2ice_tests/randomize-regalloc.ll
......@@ -2,81 +2,77 @@
; of this test will change with changes to the random number generator
; implementation.
; RUN: %p2i -i %s --args -O2 -sz-seed=1 -randomize-regalloc \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -O2 -sz-seed=1 \
; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=CHECK_1
; RUN: %p2i -i %s --args -Om1 -sz-seed=1 -randomize-regalloc \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -sz-seed=1 \
; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=OPTM1_1
; Same tests but with a different seed, just to verify randomness.
; RUN: %p2i -i %s --args -O2 -sz-seed=123 -randomize-regalloc \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -O2 -sz-seed=123 \
; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=CHECK_123
; RUN: %p2i -i %s --args -Om1 -sz-seed=123 -randomize-regalloc \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -sz-seed=123 \
; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=OPTM1_123
define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
entry:
%res = mul <4 x i32> %a, %b
ret <4 x i32> %res
; OPTM1_1-LABEL: mul_v4i32:
; OPTM1_1: sub esp, 60
; OPTM1_1-NEXT: movups xmmword ptr [esp + 32], xmm0
; OPTM1_1-NEXT: movups xmmword ptr [esp + 16], xmm1
; OPTM1_1-NEXT: movups xmm0, xmmword ptr [esp + 32]
; OPTM1_1-NEXT: pshufd xmm7, xmmword ptr [esp + 32], 49
; OPTM1_1-NEXT: pshufd xmm4, xmmword ptr [esp + 16], 49
; OPTM1_1-NEXT: pmuludq xmm0, xmmword ptr [esp + 16]
; OPTM1_1-NEXT: pmuludq xmm7, xmm4
; OPTM1_1-NEXT: shufps xmm0, xmm7, -120
; OPTM1_1-NEXT: pshufd xmm0, xmm0, -40
; OPTM1_1-NEXT: movups xmmword ptr [esp], xmm0
; OPTM1_1-NEXT: movups xmm0, xmmword ptr [esp]
; OPTM1_1-NEXT: add esp, 60
; OPTM1_1-LABEL: mul_v4i32
; OPTM1_1: sub esp,0x3c
; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
; OPTM1_1-NEXT: pshufd xmm7,XMMWORD PTR [esp+0x20],0x31
; OPTM1_1-NEXT: pshufd xmm4,XMMWORD PTR [esp+0x10],0x31
; OPTM1_1-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
; OPTM1_1-NEXT: pmuludq xmm7,xmm4
; OPTM1_1-NEXT: shufps xmm0,xmm7,0x88
; OPTM1_1-NEXT: pshufd xmm0,xmm0,0xd8
; OPTM1_1-NEXT: movups XMMWORD PTR [esp],xmm0
; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp]
; OPTM1_1-NEXT: add esp,0x3c
; OPTM1_1-NEXT: ret
; CHECK_1-LABEL: mul_v4i32:
; CHECK_1: movups xmm6, xmm0
; CHECK_1-NEXT: pshufd xmm0, xmm0, 49
; CHECK_1-NEXT: pshufd xmm5, xmm1, 49
; CHECK_1-NEXT: pmuludq xmm6, xmm1
; CHECK_1-NEXT: pmuludq xmm0, xmm5
; CHECK_1-NEXT: shufps xmm6, xmm0, -120
; CHECK_1-NEXT: pshufd xmm6, xmm6, -40
; CHECK_1-NEXT: movups xmm0, xmm6
; CHECK_1-LABEL: mul_v4i32
; CHECK_1: movups xmm6,xmm0
; CHECK_1-NEXT: pshufd xmm0,xmm0,0x31
; CHECK_1-NEXT: pshufd xmm5,xmm1,0x31
; CHECK_1-NEXT: pmuludq xmm6,xmm1
; CHECK_1-NEXT: pmuludq xmm0,xmm5
; CHECK_1-NEXT: shufps xmm6,xmm0,0x88
; CHECK_1-NEXT: pshufd xmm6,xmm6,0xd8
; CHECK_1-NEXT: movups xmm0,xmm6
; CHECK_1-NEXT: ret
; OPTM1_123-LABEL: mul_v4i32:
; OPTM1_123: sub esp, 60
; OPTM1_123-NEXT: movups xmmword ptr [esp + 32], xmm0
; OPTM1_123-NEXT: movups xmmword ptr [esp + 16], xmm1
; OPTM1_123-NEXT: movups xmm0, xmmword ptr [esp + 32]
; OPTM1_123-NEXT: pshufd xmm2, xmmword ptr [esp + 32], 49
; OPTM1_123-NEXT: pshufd xmm6, xmmword ptr [esp + 16], 49
; OPTM1_123-NEXT: pmuludq xmm0, xmmword ptr [esp + 16]
; OPTM1_123-NEXT: pmuludq xmm2, xmm6
; OPTM1_123-NEXT: shufps xmm0, xmm2, -120
; OPTM1_123-NEXT: pshufd xmm0, xmm0, -40
; OPTM1_123-NEXT: movups xmmword ptr [esp], xmm0
; OPTM1_123-NEXT: movups xmm0, xmmword ptr [esp]
; OPTM1_123-NEXT: add esp, 60
; OPTM1_123-LABEL: mul_v4i32
; OPTM1_123: sub esp,0x3c
; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
; OPTM1_123-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x20],0x31
; OPTM1_123-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x10],0x31
; OPTM1_123-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
; OPTM1_123-NEXT: pmuludq xmm2,xmm6
; OPTM1_123-NEXT: shufps xmm0,xmm2,0x88
; OPTM1_123-NEXT: pshufd xmm0,xmm0,0xd8
; OPTM1_123-NEXT: movups XMMWORD PTR [esp],xmm0
; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp]
; OPTM1_123-NEXT: add esp,0x3c
; OPTM1_123-NEXT: ret
; CHECK_123-LABEL: mul_v4i32:
; CHECK_123: movups xmm3, xmm0
; CHECK_123-NEXT: pshufd xmm0, xmm0, 49
; CHECK_123-NEXT: pshufd xmm7, xmm1, 49
; CHECK_123-NEXT: pmuludq xmm3, xmm1
; CHECK_123-NEXT: pmuludq xmm0, xmm7
; CHECK_123-NEXT: shufps xmm3, xmm0, -120
; CHECK_123-NEXT: pshufd xmm3, xmm3, -40
; CHECK_123-NEXT: movups xmm0, xmm3
; CHECK_123-LABEL: mul_v4i32
; CHECK_123: movups xmm3,xmm0
; CHECK_123-NEXT: pshufd xmm0,xmm0,0x31
; CHECK_123-NEXT: pshufd xmm7,xmm1,0x31
; CHECK_123-NEXT: pmuludq xmm3,xmm1
; CHECK_123-NEXT: pmuludq xmm0,xmm7
; CHECK_123-NEXT: shufps xmm3,xmm0,0x88
; CHECK_123-NEXT: pshufd xmm3,xmm3,0xd8
; CHECK_123-NEXT: movups xmm0,xmm3
; CHECK_123-NEXT: ret
}
......
tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll
; This file checks that SimpleCoalescing of local stack slots is not done
; when calling a function with the "returns twice" attribute.
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
; Setjmp is a function with the "returns twice" attribute.
declare i32 @llvm.nacl.setjmp(i8*)
......@@ -28,11 +27,11 @@ NonZero:
}
; CHECK-LABEL: call_returns_twice
; CHECK: add [[REG1:.*]], 12345
; CHECK: mov dword ptr [esp + [[OFF:.*]]], [[REG1]]
; CHECK: add [[REG2:.*]], 54321
; CHECK: add [[REG1:.*]],0x3039
; CHECK: mov DWORD PTR [esp+[[OFF:.*]]],[[REG1]]
; CHECK: add [[REG2:.*]],0xd431
; There should not be sharing of the stack slot.
; CHECK-NOT: mov dword ptr [esp + [[OFF]]], [[REG2]]
; CHECK-NOT: mov DWORD PTR [esp + [[OFF]]], [[REG2]]
define i32 @no_call_returns_twice(i32 %iptr_jmpbuf, i32 %x) {
entry:
......@@ -50,11 +49,11 @@ NonZero:
}
; CHECK-LABEL: no_call_returns_twice
; CHECK: add [[REG1:.*]], 12345
; CHECK: mov dword ptr [esp + [[OFF:.*]]], [[REG1]]
; CHECK: add [[REG2:.*]], 54321
; CHECK: add [[REG1:.*]],0x3039
; CHECK: mov DWORD PTR [esp+[[OFF:.*]]],[[REG1]]
; CHECK: add [[REG2:.*]],0xd431
; Now there should be sharing of the stack slot (OFF is the same).
; Commenting out after disabling simple coalescing for -Om1.
; TODO(stichnot): Add it back if/when we add a flag to enable simple
; coalescing.
; xCHECK: mov dword ptr [esp + [[OFF]]], [[REG2]]
; xCHECK: mov DWORD PTR [esp + [[OFF]]], [[REG2]]
tests_lit/llvm2ice_tests/sdiv.ll
; This checks the correctness of the lowering code for the small
; integer variants of sdiv and srem.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
define i32 @sdiv_i8(i32 %a.i32, i32 %b.i32) {
entry:
......@@ -15,7 +13,7 @@ entry:
%res = sdiv i8 %a, %b
%res.i32 = zext i8 %res to i32
ret i32 %res.i32
; CHECK-LABEL: sdiv_i8:
; CHECK-LABEL: sdiv_i8
; CHECK: cbw
; CHECK: idiv
}
......@@ -27,7 +25,7 @@ entry:
%res = sdiv i16 %a, %b
%res.i32 = zext i16 %res to i32
ret i32 %res.i32
; CHECK-LABEL: sdiv_i16:
; CHECK-LABEL: sdiv_i16
; CHECK: cwd
; CHECK: idiv
}
......@@ -36,7 +34,7 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
entry:
%res = sdiv i32 %a, %b
ret i32 %res
; CHECK-LABEL: sdiv_i32:
; CHECK-LABEL: sdiv_i32
; CHECK: cdq
; CHECK: idiv
}
......@@ -48,7 +46,7 @@ entry:
%res = srem i8 %a, %b
%res.i32 = zext i8 %res to i32
ret i32 %res.i32
; CHECK-LABEL: srem_i8:
; CHECK-LABEL: srem_i8
; CHECK: cbw
; CHECK: idiv
}
......@@ -60,7 +58,7 @@ entry:
%res = srem i16 %a, %b
%res.i32 = zext i16 %res to i32
ret i32 %res.i32
; CHECK-LABEL: srem_i16:
; CHECK-LABEL: srem_i16
; CHECK: cwd
; CHECK: idiv
}
......@@ -69,7 +67,7 @@ define i32 @srem_i32(i32 %a, i32 %b) {
entry:
%res = srem i32 %a, %b
ret i32 %res
; CHECK-LABEL: srem_i32:
; CHECK-LABEL: srem_i32
; CHECK: cdq
; CHECK: idiv
}
tests_lit/llvm2ice_tests/select-opt.ll
......@@ -3,12 +3,10 @@
; regardless of the optimization level, so there are no special OPTM1
; match lines.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
define void @testSelect(i32 %a, i32 %b) {
entry:
......@@ -21,21 +19,15 @@ entry:
ret void
}
define void @useInt(i32 %x) {
entry:
call void @useIntHelper(i32 %x)
ret void
}
declare void @useIntHelper(i32)
declare void @useInt(i32 %x)
; CHECK-LABEL: testSelect
; CHECK: cmp
; CHECK: cmp
; CHECK: call useInt
; CHECK: call {{.*}} R_{{.*}} useInt
; CHECK: cmp
; CHECK: cmp
; CHECK: call useInt
; CHECK: call {{.*}} R_{{.*}} useInt
; CHECK: ret
; Check for valid addressing mode in the cmp instruction when the
......@@ -46,7 +38,7 @@ entry:
ret i32 %cond
}
; CHECK-LABEL: testSelectImm32
; CHECK-NOT: cmp {{[0-9]+}},
; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
; Check for valid addressing mode in the cmp instruction when the
; operand is an immediate. There is a different x86-32 lowering
......@@ -57,4 +49,4 @@ entry:
ret i64 %cond
}
; CHECK-LABEL: testSelectImm64
; CHECK-NOT: cmp {{[0-9]+}},
; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
tests_lit/llvm2ice_tests/shift.ll
; This is a test of C-level conversion operations that clang lowers
; into pairs of shifts.
; RUN: %p2i -i %s --no-local-syms --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --no-local-syms --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --no-local-syms --args -O2 \
; RUN: --verbose none | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --no-local-syms --args -Om1 \
; RUN: --verbose none | FileCheck %s
@i1 = internal global [4 x i8] zeroinitializer, align 4
@i2 = internal global [4 x i8] zeroinitializer, align 4
......@@ -23,8 +21,8 @@ entry:
ret void
}
; CHECK-LABEL: conv1
; CHECK: shl {{.*}}, 24
; CHECK: sar {{.*}}, 24
; CHECK: shl {{.*}},0x18
; CHECK: sar {{.*}},0x18
define void @conv2() {
entry:
......@@ -37,5 +35,5 @@ entry:
ret void
}
; CHECK-LABEL: conv2
; CHECK: shl {{.*}}, 16
; CHECK: sar {{.*}}, 16
; CHECK: shl {{.*}},0x10
; CHECK: sar {{.*}},0x10
tests_lit/llvm2ice_tests/simple-loop.ll
; This tests a simple loop that sums the elements of an input array.
; The O2 check patterns represent the best code currently achieved.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
define i32 @simple_loop(i32 %a, i32 %n) {
......@@ -32,22 +29,22 @@ for.end:
}
; CHECK-LABEL: simple_loop
; CHECK: mov ecx, dword ptr [esp{{.*}}+{{.*}}{{[0-9]+}}]
; CHECK: cmp ecx, 0
; CHECK: mov ecx,DWORD PTR [esp{{.*}}+0x{{[0-9a-f]+}}]
; CHECK: cmp ecx,0x0
; CHECK-NEXT: j{{le|g}} {{[0-9]}}
; Check for the combination of address mode inference, register
; allocation, and load/arithmetic fusing.
; CHECK: add e{{..}}, dword ptr [e{{..}} + 4*[[IREG:e..]]]
; CHECK: [[L:[0-9a-f]+]]{{.*}} add e{{..}},DWORD PTR [e{{..}}+[[IREG:e..]]*4]
; Check for incrementing of the register-allocated induction variable.
; CHECK-NEXT: add [[IREG]], 1
; CHECK-NEXT: add [[IREG]],0x1
; Check for comparing the induction variable against the loop size.
; CHECK-NEXT: cmp [[IREG]],
; CHECK-NEXT: jl -{{[0-9]}}
; CHECK-NEXT: jl [[L]]
;
; There's nothing remarkable under Om1 to test for, since Om1 generates
; such atrocious code (by design).
; OPTM1-LABEL: simple_loop
; OPTM1: cmp {{.*}}, 0
; OPTM1: cmp {{.*}},0x0
; OPTM1: jg
; OPTM1: ret
tests_lit/llvm2ice_tests/switch-opt.ll
......@@ -2,9 +2,8 @@
; same label which also results in phi instructions with multiple
; entries for the same incoming edge.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
define i32 @testSwitch(i32 %a) {
entry:
......@@ -49,7 +48,7 @@ sw.default:
ret i32 20
}
; CHECK-LABEL: testSwitchImm
; CHECK-NOT: cmp {{[0-9]*}},
; CHECK-NOT: cmp 0x{{[0-9a-f]*}},
; Test for correct 64-bit lowering.
define internal i32 @testSwitch64(i64 %a) {
......@@ -78,21 +77,21 @@ return: ; preds = %sw.default, %sw.bb3
ret i32 %retval.0
}
; CHECK-LABEL: testSwitch64
; CHECK: cmp {{.*}}, 123
; CHECK: cmp {{.*}},0x7b
; CHECK-NEXT: jne
; CHECK-NEXT: cmp {{.*}}, 0
; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
; CHECK: cmp {{.*}}, 234
; CHECK: cmp {{.*}},0xea
; CHECK-NEXT: jne
; CHECK-NEXT: cmp {{.*}}, 0
; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
; CHECK: cmp {{.*}}, 345
; CHECK: cmp {{.*}},0x159
; CHECK-NEXT: jne
; CHECK-NEXT: cmp {{.*}}, 0
; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
; CHECK: cmp {{.*}}, 878082192
; CHECK: cmp {{.*}},0x34567890
; CHECK-NEXT: jne
; CHECK-NEXT: cmp {{.*}}, 18
; CHECK-NEXT: cmp {{.*}},0x12
; CHECK-NEXT: je
; Similar to testSwitchImm, make sure proper addressing modes are
......@@ -108,7 +107,7 @@ sw.default:
ret i32 20
}
; CHECK-LABEL: testSwitchImm64
; CHECK: cmp {{.*}}, 1
; CHECK: cmp {{.*}},0x1
; CHECK-NEXT: jne
; CHECK-NEXT: cmp {{.*}}, 0
; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
tests_lit/llvm2ice_tests/test_i1.ll
; Tests various aspects of i1 related lowering.
; RUN: %p2i -i %s -a -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s -a -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
; RUN: | FileCheck %s
; Test that and with true uses immediate 1, not -1.
define internal i32 @testAndTrue(i32 %arg) {
......@@ -16,7 +14,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testAndTrue
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; Test that or with true uses immediate 1, not -1.
define internal i32 @testOrTrue(i32 %arg) {
......@@ -27,7 +25,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testOrTrue
; CHECK: or {{.*}}, 1
; CHECK: or {{.*}},0x1
; Test that xor with true uses immediate 1, not -1.
define internal i32 @testXorTrue(i32 %arg) {
......@@ -38,7 +36,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testXorTrue
; CHECK: xor {{.*}}, 1
; CHECK: xor {{.*}},0x1
; Test that trunc to i1 masks correctly.
define internal i32 @testTrunc(i32 %arg) {
......@@ -48,7 +46,7 @@ entry:
ret i32 %result
}
; CHECK-LABEL: testTrunc
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; Test zext to i8.
define internal i32 @testZextI8(i32 %arg) {
......@@ -60,9 +58,9 @@ entry:
}
; CHECK-LABEL: testZextI8
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the zext i1 instruction (NOTE: no mov need between i1 and i8).
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; Test zext to i16.
define internal i32 @testZextI16(i32 %arg) {
......@@ -74,10 +72,10 @@ entry:
}
; CHECK-LABEL: testZextI16
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the zext i1 instruction (note 32-bit reg is used because it's shorter).
; CHECK: movzx [[REG:e.*]], {{[a-d]l|byte ptr}}
; CHECK: and [[REG]], 1
; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}}
; CHECK: and [[REG]],0x1
; Test zext to i32.
define internal i32 @testZextI32(i32 %arg) {
......@@ -88,10 +86,10 @@ entry:
}
; CHECK-LABEL: testZextI32
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the zext i1 instruction
; CHECK: movzx
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; Test zext to i64.
define internal i64 @testZextI64(i32 %arg) {
......@@ -102,11 +100,11 @@ entry:
}
; CHECK-LABEL: testZextI64
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the zext i1 instruction
; CHECK: movzx
; CHECK: and {{.*}}, 1
; CHECK: mov {{.*}}, 0
; CHECK: and {{.*}},0x1
; CHECK: mov {{.*}},0x0
; Test sext to i8.
define internal i32 @testSextI8(i32 %arg) {
......@@ -118,10 +116,10 @@ entry:
}
; CHECK-LABEL: testSextI8
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the sext i1 instruction
; CHECK: shl [[REG:.*]], 7
; CHECK-NEXT: sar [[REG]], 7
; CHECK: shl [[REG:.*]],0x7
; CHECK-NEXT: sar [[REG]],0x7
; Test sext to i16.
define internal i32 @testSextI16(i32 %arg) {
......@@ -133,11 +131,11 @@ entry:
}
; CHECK-LABEL: testSextI16
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the sext i1 instruction
; CHECK: movzx e[[REG:.*]], {{[a-d]l|byte ptr}}
; CHECK-NEXT: shl [[REG]], 15
; CHECK-NEXT: sar [[REG]], 15
; CHECK: movzx e[[REG:.*]],{{[a-d]l|BYTE PTR}}
; CHECK-NEXT: shl [[REG]],0xf
; CHECK-NEXT: sar [[REG]],0xf
; Test sext to i32.
define internal i32 @testSextI32(i32 %arg) {
......@@ -148,11 +146,11 @@ entry:
}
; CHECK-LABEL: testSextI32
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the sext i1 instruction
; CHECK: movzx [[REG:.*]],
; CHECK-NEXT: shl [[REG]], 31
; CHECK-NEXT: sar [[REG]], 31
; CHECK-NEXT: shl [[REG]],0x1f
; CHECK-NEXT: sar [[REG]],0x1f
; Test sext to i64.
define internal i64 @testSextI64(i32 %arg) {
......@@ -163,11 +161,11 @@ entry:
}
; CHECK-LABEL: testSextI64
; match the trunc instruction
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; match the sext i1 instruction
; CHECK: movzx [[REG:.*]],
; CHECK-NEXT: shl [[REG]], 31
; CHECK-NEXT: sar [[REG]], 31
; CHECK-NEXT: shl [[REG]],0x1f
; CHECK-NEXT: sar [[REG]],0x1f
; Test fptosi float to i1.
define internal i32 @testFptosiFloat(float %arg) {
......@@ -178,10 +176,10 @@ entry:
}
; CHECK-LABEL: testFptosiFloat
; CHECK: cvttss2si
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; CHECK: movzx [[REG:.*]],
; CHECK-NEXT: shl [[REG]], 31
; CHECK-NEXT: sar [[REG]], 31
; CHECK-NEXT: shl [[REG]],0x1f
; CHECK-NEXT: sar [[REG]],0x1f
; Test fptosi double to i1.
define internal i32 @testFptosiDouble(double %arg) {
......@@ -192,7 +190,7 @@ entry:
}
; CHECK-LABEL: testFptosiDouble
; CHECK: cvttsd2si
; CHECK: and {{.*}}, 1
; CHECK: and {{.*}},0x1
; CHECK: movzx [[REG:.*]],
; CHECK-NEXT: shl [[REG]], 31
; CHECK-NEXT: sar [[REG]], 31
; CHECK-NEXT: shl [[REG]],0x1f
; CHECK-NEXT: sar [[REG]],0x1f
tests_lit/llvm2ice_tests/undef.ll
; This test checks that undef values are represented as zero.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck %s
define i32 @undef_i32() {
entry:
ret i32 undef
; CHECK-LABEL: undef_i32
; CHECK: mov eax, 0
; CHECK: mov eax,0x0
}
define i64 @undef_i64() {
entry:
ret i64 undef
; CHECK-LABEL: undef_i64
; CHECK-DAG: mov eax, 0
; CHECK-DAG: mov edx, 0
; CHECK-DAG: mov eax,0x0
; CHECK-DAG: mov edx,0x0
; CHECK: ret
}
......@@ -33,7 +29,7 @@ define float @undef_float() {
entry:
ret float undef
; CHECK-LABEL: undef_float
; CHECK: fld dword ptr [.L$float$0]
; CHECK: fld DWORD PTR {{.*}} .L$float$0
}
define <4 x i1> @undef_v4i1() {
......@@ -186,7 +182,7 @@ entry:
%val = insertelement <4 x float> %arg, float undef, i32 0
ret <4 x float> %val
; CHECK-LABEL: vector_insertelement_arg2
; CHECK: movss {{.*}}, dword ptr [.L$float$0]
; CHECK: movss {{.*}},DWORD PTR {{.*}} .L$float$0
}
define float @vector_extractelement_v4f32_index_0() {
......
tests_lit/llvm2ice_tests/unreachable.ll
; This tests the basic structure of the Unreachable instruction.
; RUN: %p2i -i %s -a -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s -a -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
; RUN: | FileCheck %s
define internal i32 @divide(i32 %num, i32 %den) {
entry:
......@@ -22,7 +20,7 @@ return: ; preds = %entry
; CHECK-LABEL: divide
; CHECK: cmp
; CHECK: call ice_unreachable
; CHECK: call {{.*}} R_{{.*}} ice_unreachable
; CHECK: cdq
; CHECK: idiv
; CHECK: ret
tests_lit/llvm2ice_tests/vector-bitcast.ll
; This file tests bitcasts of vector type. For most operations, these
; should be lowered to a no-op on -O2.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
define <16 x i8> @test_bitcast_v16i8_to_v16i8(<16 x i8> %arg) {
......@@ -32,7 +29,7 @@ entry:
%res = bitcast <16 x i8> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v16i8_to_v4i32:
; CHECK-LABEL: test_bitcast_v16i8_to_v4i32
; CHECK-NEXT: ret
}
......@@ -41,7 +38,7 @@ entry:
%res = bitcast <16 x i8> %arg to <4 x float>
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v16i8_to_v4f32:
; CHECK-LABEL: test_bitcast_v16i8_to_v4f32
; CHECK-NEXT: ret
}
......@@ -50,7 +47,7 @@ entry:
%res = bitcast <8 x i16> %arg to <16 x i8>
ret <16 x i8> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v16i8:
; CHECK-LABEL: test_bitcast_v8i16_to_v16i8
; CHECK-NEXT: ret
}
......@@ -59,7 +56,7 @@ entry:
%res = bitcast <8 x i16> %arg to <8 x i16>
ret <8 x i16> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v8i16:
; CHECK-LABEL: test_bitcast_v8i16_to_v8i16
; CHECK-NEXT: ret
}
......@@ -68,7 +65,7 @@ entry:
%res = bitcast <8 x i16> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v4i32:
; CHECK-LABEL: test_bitcast_v8i16_to_v4i32
; CHECK-NEXT: ret
}
......@@ -77,7 +74,7 @@ entry:
%res = bitcast <8 x i16> %arg to <4 x float>
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v4f32:
; CHECK-LABEL: test_bitcast_v8i16_to_v4f32
; CHECK-NEXT: ret
}
......@@ -86,7 +83,7 @@ entry:
%res = bitcast <4 x i32> %arg to <16 x i8>
ret <16 x i8> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v16i8:
; CHECK-LABEL: test_bitcast_v4i32_to_v16i8
; CHECK-NEXT: ret
}
......@@ -95,7 +92,7 @@ entry:
%res = bitcast <4 x i32> %arg to <8 x i16>
ret <8 x i16> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v8i16:
; CHECK-LABEL: test_bitcast_v4i32_to_v8i16
; CHECK-NEXT: ret
}
......@@ -104,7 +101,7 @@ entry:
%res = bitcast <4 x i32> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v4i32:
; CHECK-LABEL: test_bitcast_v4i32_to_v4i32
; CHECK-NEXT: ret
}
......@@ -113,7 +110,7 @@ entry:
%res = bitcast <4 x i32> %arg to <4 x float>
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v4f32:
; CHECK-LABEL: test_bitcast_v4i32_to_v4f32
; CHECK-NEXT: ret
}
......@@ -122,7 +119,7 @@ entry:
%res = bitcast <4 x float> %arg to <16 x i8>
ret <16 x i8> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v16i8:
; CHECK-LABEL: test_bitcast_v4f32_to_v16i8
; CHECK-NEXT: ret
}
......@@ -131,7 +128,7 @@ entry:
%res = bitcast <4 x float> %arg to <8 x i16>
ret <8 x i16> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v8i16:
; CHECK-LABEL: test_bitcast_v4f32_to_v8i16
; CHECK-NEXT: ret
}
......@@ -140,7 +137,7 @@ entry:
%res = bitcast <4 x float> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v4i32:
; CHECK-LABEL: test_bitcast_v4f32_to_v4i32
; CHECK-NEXT: ret
}
......@@ -149,7 +146,7 @@ entry:
%res = bitcast <4 x float> %arg to <4 x float>
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v4f32:
; CHECK-LABEL: test_bitcast_v4f32_to_v4f32
; CHECK-NEXT: ret
}
......@@ -158,10 +155,10 @@ entry:
%res = bitcast <8 x i1> %arg to i8
ret i8 %res
; CHECK-LABEL: test_bitcast_v8i1_to_i8:
; CHECK: call Sz_bitcast_v8i1_to_i8
; CHECK-LABEL: test_bitcast_v8i1_to_i8
; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_v8i1_to_i8
; OPTM1-LABEL: test_bitcast_v8i1_to_i8:
; OPTM1-LABEL: test_bitcast_v8i1_to_i8
; OPMT1: call -4
}
......@@ -170,10 +167,10 @@ entry:
%res = bitcast <16 x i1> %arg to i16
ret i16 %res
; CHECK-LABEL: test_bitcast_v16i1_to_i16:
; CHECK: call Sz_bitcast_v16i1_to_i16
; CHECK-LABEL: test_bitcast_v16i1_to_i16
; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_v16i1_to_i16
; OPTM1-LABEL: test_bitcast_v16i1_to_i16:
; OPTM1-LABEL: test_bitcast_v16i1_to_i16
; OPMT1: call -4
}
......@@ -183,11 +180,11 @@ entry:
%res = bitcast i8 %arg.trunc to <8 x i1>
ret <8 x i1> %res
; CHECK-LABEL: test_bitcast_i8_to_v8i1:
; CHECK: call Sz_bitcast_i8_to_v8i1
; CHECK-LABEL: test_bitcast_i8_to_v8i1
; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_i8_to_v8i1
; OPTM1-LABEL: test_bitcast_i8_to_v8i1:
; OPTM1: call Sz_bitcast_i8_to_v8i1
; OPTM1-LABEL: test_bitcast_i8_to_v8i1
; OPTM1: call {{.*}} R_{{.*}} Sz_bitcast_i8_to_v8i1
}
define <16 x i1> @test_bitcast_i16_to_v16i1(i32 %arg) {
......@@ -196,9 +193,9 @@ entry:
%res = bitcast i16 %arg.trunc to <16 x i1>
ret <16 x i1> %res
; CHECK-LABEL: test_bitcast_i16_to_v16i1:
; CHECK: call Sz_bitcast_i16_to_v16i1
; CHECK-LABEL: test_bitcast_i16_to_v16i1
; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_i16_to_v16i1
; OPTM1-LABEL: test_bitcast_i16_to_v16i1:
; OPTM1: call Sz_bitcast_i16_to_v16i1
; OPTM1-LABEL: test_bitcast_i16_to_v16i1
; OPTM1: call {{.*}} R_{{.*}} Sz_bitcast_i16_to_v16i1
}
tests_lit/llvm2ice_tests/vector-cast.ll
; This file tests casting / conversion operations that apply to vector types.
; bitcast operations are in vector-bitcast.ll.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
; sext operations
......@@ -15,7 +13,7 @@ entry:
%res = sext <16 x i1> %arg to <16 x i8>
ret <16 x i8> %res
; CHECK-LABEL: test_sext_v16i1_to_v16i8:
; CHECK-LABEL: test_sext_v16i1_to_v16i8
; CHECK: pxor
; CHECK: pcmpeqb
; CHECK: psubb
......@@ -29,9 +27,9 @@ entry:
%res = sext <8 x i1> %arg to <8 x i16>
ret <8 x i16> %res
; CHECK-LABEL: test_sext_v8i1_to_v8i16:
; CHECK: psllw {{.*}}, 15
; CHECK: psraw {{.*}}, 15
; CHECK-LABEL: test_sext_v8i1_to_v8i16
; CHECK: psllw {{.*}},0xf
; CHECK: psraw {{.*}},0xf
}
define <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
......@@ -39,9 +37,9 @@ entry:
%res = sext <4 x i1> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_sext_v4i1_to_v4i32:
; CHECK: pslld {{.*}}, 31
; CHECK: psrad {{.*}}, 31
; CHECK-LABEL: test_sext_v4i1_to_v4i32
; CHECK: pslld {{.*}},0x1f
; CHECK: psrad {{.*}},0x1f
}
; zext operations
......@@ -51,7 +49,7 @@ entry:
%res = zext <16 x i1> %arg to <16 x i8>
ret <16 x i8> %res
; CHECK-LABEL: test_zext_v16i1_to_v16i8:
; CHECK-LABEL: test_zext_v16i1_to_v16i8
; CHECK: pxor
; CHECK: pcmpeqb
; CHECK: psubb
......@@ -63,7 +61,7 @@ entry:
%res = zext <8 x i1> %arg to <8 x i16>
ret <8 x i16> %res
; CHECK-LABEL: test_zext_v8i1_to_v8i16:
; CHECK-LABEL: test_zext_v8i1_to_v8i16
; CHECK: pxor
; CHECK: pcmpeqw
; CHECK: psubw
......@@ -75,7 +73,7 @@ entry:
%res = zext <4 x i1> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_zext_v4i1_to_v4i32:
; CHECK-LABEL: test_zext_v4i1_to_v4i32
; CHECK: pxor
; CHECK: pcmpeqd
; CHECK: psubd
......@@ -89,7 +87,7 @@ entry:
%res = trunc <16 x i8> %arg to <16 x i1>
ret <16 x i1> %res
; CHECK-LABEL: test_trunc_v16i8_to_v16i1:
; CHECK-LABEL: test_trunc_v16i8_to_v16i1
; CHECK: pxor
; CHECK: pcmpeqb
; CHECK: psubb
......@@ -101,7 +99,7 @@ entry:
%res = trunc <8 x i16> %arg to <8 x i1>
ret <8 x i1> %res
; CHECK-LABEL: test_trunc_v8i16_to_v8i1:
; CHECK-LABEL: test_trunc_v8i16_to_v8i1
; CHECK: pxor
; CHECK: pcmpeqw
; CHECK: psubw
......@@ -113,7 +111,7 @@ entry:
%res = trunc <4 x i32> %arg to <4 x i1>
ret <4 x i1> %res
; CHECK-LABEL: test_trunc_v4i32_to_v4i1:
; CHECK-LABEL: test_trunc_v4i32_to_v4i1
; CHECK: pxor
; CHECK: pcmpeqd
; CHECK: psubd
......@@ -127,7 +125,7 @@ entry:
%res = fptosi <4 x float> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_fptosi_v4f32_to_v4i32:
; CHECK-LABEL: test_fptosi_v4f32_to_v4i32
; CHECK: cvttps2dq
}
......@@ -136,8 +134,8 @@ entry:
%res = fptoui <4 x float> %arg to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: test_fptoui_v4f32_to_v4i32:
; CHECK: call Sz_fptoui_v4f32
; CHECK-LABEL: test_fptoui_v4f32_to_v4i32
; CHECK: call {{.*}} R_{{.*}} Sz_fptoui_v4f32
}
; [su]itofp operations
......@@ -147,7 +145,7 @@ entry:
%res = sitofp <4 x i32> %arg to <4 x float>
ret <4 x float> %res
; CHECK-LABEL: test_sitofp_v4i32_to_v4f32:
; CHECK-LABEL: test_sitofp_v4i32_to_v4f32
; CHECK: cvtdq2ps
}
......@@ -156,6 +154,6 @@ entry:
%res = uitofp <4 x i32> %arg to <4 x float>
ret <4 x float> %res
; CHECK-LABEL: test_uitofp_v4i32_to_v4f32:
; CHECK: call Sz_uitofp_v4i32
; CHECK-LABEL: test_uitofp_v4i32_to_v4f32
; CHECK: call {{.*}} R_{{.*}} Sz_uitofp_v4i32
}
tests_lit/llvm2ice_tests/vector-fcmp.ll
; This file checks support for comparing vector values with the fcmp
; instruction.
; RUN: %p2i -i %s -a -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s -a -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
; RUN: | FileCheck %s
; Check that sext elimination occurs when the result of the comparison
; instruction is alrady sign extended. Sign extension to 4 x i32 uses
......@@ -16,7 +14,7 @@ entry:
%res.trunc = fcmp oeq <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: sextElimination:
; CHECK-LABEL: sextElimination
; CHECK: cmpeqps
; CHECK-NOT: pslld
}
......@@ -26,7 +24,7 @@ entry:
%res.trunc = fcmp false <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpFalseVector:
; CHECK-LABEL: fcmpFalseVector
; CHECK: pxor
}
......@@ -35,7 +33,7 @@ entry:
%res.trunc = fcmp oeq <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOeqVector:
; CHECK-LABEL: fcmpOeqVector
; CHECK: cmpeqps
}
......@@ -44,7 +42,7 @@ entry:
%res.trunc = fcmp oge <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOgeVector:
; CHECK-LABEL: fcmpOgeVector
; CHECK: cmpleps
}
......@@ -53,7 +51,7 @@ entry:
%res.trunc = fcmp ogt <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOgtVector:
; CHECK-LABEL: fcmpOgtVector
; CHECK: cmpltps
}
......@@ -62,7 +60,7 @@ entry:
%res.trunc = fcmp ole <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOleVector:
; CHECK-LABEL: fcmpOleVector
; CHECK: cmpleps
}
......@@ -71,7 +69,7 @@ entry:
%res.trunc = fcmp olt <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOltVector:
; CHECK-LABEL: fcmpOltVector
; CHECK: cmpltps
}
......@@ -80,7 +78,7 @@ entry:
%res.trunc = fcmp one <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOneVector:
; CHECK-LABEL: fcmpOneVector
; CHECK: cmpneqps
; CHECK: cmpordps
; CHECK: pand
......@@ -91,7 +89,7 @@ entry:
%res.trunc = fcmp ord <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpOrdVector:
; CHECK-LABEL: fcmpOrdVector
; CHECK: cmpordps
}
......@@ -100,7 +98,7 @@ entry:
%res.trunc = fcmp true <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpTrueVector:
; CHECK-LABEL: fcmpTrueVector
; CHECK: pcmpeqd
}
......@@ -109,7 +107,7 @@ entry:
%res.trunc = fcmp ueq <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUeqVector:
; CHECK-LABEL: fcmpUeqVector
; CHECK: cmpeqps
; CHECK: cmpunordps
; CHECK: por
......@@ -120,7 +118,7 @@ entry:
%res.trunc = fcmp uge <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUgeVector:
; CHECK-LABEL: fcmpUgeVector
; CHECK: cmpnltps
}
......@@ -129,7 +127,7 @@ entry:
%res.trunc = fcmp ugt <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUgtVector:
; CHECK-LABEL: fcmpUgtVector
; CHECK: cmpnleps
}
......@@ -138,7 +136,7 @@ entry:
%res.trunc = fcmp ule <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUleVector:
; CHECK-LABEL: fcmpUleVector
; CHECK: cmpnltps
}
......@@ -147,7 +145,7 @@ entry:
%res.trunc = fcmp ult <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUltVector:
; CHECK-LABEL: fcmpUltVector
; CHECK: cmpnleps
}
......@@ -156,7 +154,7 @@ entry:
%res.trunc = fcmp une <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUneVector:
; CHECK-LABEL: fcmpUneVector
; CHECK: cmpneqps
}
......@@ -165,6 +163,6 @@ entry:
%res.trunc = fcmp uno <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
; CHECK-LABEL: fcmpUnoVector:
; CHECK-LABEL: fcmpUnoVector
; CHECK: cmpunordps
}
tests_lit/llvm2ice_tests/vector-ops.ll
; This checks support for insertelement and extractelement.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
; insertelement operations
......@@ -21,23 +15,23 @@ define <4 x float> @insertelement_v4f32_0(<4 x float> %vec, float %elt) {
entry:
%res = insertelement <4 x float> %vec, float %elt, i32 0
ret <4 x float> %res
; CHECK-LABEL: insertelement_v4f32_0:
; CHECK-LABEL: insertelement_v4f32_0
; CHECK: movss
; SSE41-LABEL: insertelement_v4f32_0:
; SSE41: insertps {{.*}}, {{.*}}, 0
; SSE41-LABEL: insertelement_v4f32_0
; SSE41: insertps {{.*}},{{.*}},0x0
}
define <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
entry:
%res = insertelement <4 x i32> %vec, i32 %elt, i32 0
ret <4 x i32> %res
; CHECK-LABEL: insertelement_v4i32_0:
; CHECK-LABEL: insertelement_v4i32_0
; CHECK: movd xmm{{.*}},
; CHECK: movss
; SSE41-LABEL: insertelement_v4i32_0:
; SSE41: pinsrd {{.*}}, {{.*}}, 0
; SSE41-LABEL: insertelement_v4i32_0
; SSE41: pinsrd {{.*}},{{.*}},0x0
}
......@@ -45,24 +39,24 @@ define <4 x float> @insertelement_v4f32_1(<4 x float> %vec, float %elt) {
entry:
%res = insertelement <4 x float> %vec, float %elt, i32 1
ret <4 x float> %res
; CHECK-LABEL: insertelement_v4f32_1:
; CHECK-LABEL: insertelement_v4f32_1
; CHECK: shufps
; CHECK: shufps
; SSE41-LABEL: insertelement_v4f32_1:
; SSE41: insertps {{.*}}, {{.*}}, 16
; SSE41-LABEL: insertelement_v4f32_1
; SSE41: insertps {{.*}},{{.*}},0x10
}
define <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
entry:
%res = insertelement <4 x i32> %vec, i32 %elt, i32 1
ret <4 x i32> %res
; CHECK-LABEL: insertelement_v4i32_1:
; CHECK-LABEL: insertelement_v4i32_1
; CHECK: shufps
; CHECK: shufps
; SSE41-LABEL: insertelement_v4i32_1:
; SSE41: pinsrd {{.*}}, {{.*}}, 1
; SSE41-LABEL: insertelement_v4i32_1
; SSE41: pinsrd {{.*}},{{.*}},0x1
}
define <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
......@@ -70,10 +64,10 @@ entry:
%elt = trunc i32 %elt.arg to i16
%res = insertelement <8 x i16> %vec, i16 %elt, i32 1
ret <8 x i16> %res
; CHECK-LABEL: insertelement_v8i16:
; CHECK-LABEL: insertelement_v8i16
; CHECK: pinsrw
; SSE41-LABEL: insertelement_v8i16:
; SSE41-LABEL: insertelement_v8i16
; SSE41: pinsrw
}
......@@ -82,12 +76,12 @@ entry:
%elt = trunc i32 %elt.arg to i8
%res = insertelement <16 x i8> %vec, i8 %elt, i32 1
ret <16 x i8> %res
; CHECK-LABEL: insertelement_v16i8:
; CHECK-LABEL: insertelement_v16i8
; CHECK: movups
; CHECK: lea
; CHECK: mov
; SSE41-LABEL: insertelement_v16i8:
; SSE41-LABEL: insertelement_v16i8
; SSE41: pinsrb
}
......@@ -96,11 +90,11 @@ entry:
%elt = trunc i32 %elt.arg to i1
%res = insertelement <4 x i1> %vec, i1 %elt, i32 0
ret <4 x i1> %res
; CHECK-LABEL: insertelement_v4i1_0:
; CHECK-LABEL: insertelement_v4i1_0
; CHECK: movss
; SSE41-LABEL: insertelement_v4i1_0:
; SSE41: pinsrd {{.*}}, {{.*}}, 0
; SSE41-LABEL: insertelement_v4i1_0
; SSE41: pinsrd {{.*}},{{.*}},0x0
}
define <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
......@@ -108,12 +102,12 @@ entry:
%elt = trunc i32 %elt.arg to i1
%res = insertelement <4 x i1> %vec, i1 %elt, i32 1
ret <4 x i1> %res
; CHECK-LABEL: insertelement_v4i1_1:
; CHECK-LABEL: insertelement_v4i1_1
; CHECK: shufps
; CHECK: shufps
; SSE41-LABEL: insertelement_v4i1_1:
; SSE41: pinsrd {{.*}}, {{.*}}, 1
; SSE41-LABEL: insertelement_v4i1_1
; SSE41: pinsrd {{.*}},{{.*}},0x1
}
define <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
......@@ -121,10 +115,10 @@ entry:
%elt = trunc i32 %elt.arg to i1
%res = insertelement <8 x i1> %vec, i1 %elt, i32 1
ret <8 x i1> %res
; CHECK-LABEL: insertelement_v8i1:
; CHECK-LABEL: insertelement_v8i1
; CHECK: pinsrw
; SSE41-LABEL: insertelement_v8i1:
; SSE41-LABEL: insertelement_v8i1
; SSE41: pinsrw
}
......@@ -133,12 +127,12 @@ entry:
%elt = trunc i32 %elt.arg to i1
%res = insertelement <16 x i1> %vec, i1 %elt, i32 1
ret <16 x i1> %res
; CHECK-LABEL: insertelement_v16i1:
; CHECK-LABEL: insertelement_v16i1
; CHECK: movups
; CHECK: lea
; CHECK: mov
; SSE41-LABEL: insertelement_v16i1:
; SSE41-LABEL: insertelement_v16i1
; SSE41: pinsrb
}
......@@ -148,10 +142,10 @@ define float @extractelement_v4f32(<4 x float> %vec) {
entry:
%res = extractelement <4 x float> %vec, i32 1
ret float %res
; CHECK-LABEL: extractelement_v4f32:
; CHECK-LABEL: extractelement_v4f32
; CHECK: pshufd
; SSE41-LABEL: extractelement_v4f32:
; SSE41-LABEL: extractelement_v4f32
; SSE41: pshufd
}
......@@ -159,11 +153,11 @@ define i32 @extractelement_v4i32(<4 x i32> %vec) {
entry:
%res = extractelement <4 x i32> %vec, i32 1
ret i32 %res
; CHECK-LABEL: extractelement_v4i32:
; CHECK-LABEL: extractelement_v4i32
; CHECK: pshufd
; CHECK: movd {{.*}}, xmm
; CHECK: movd {{.*}},xmm
; SSE41-LABEL: extractelement_v4i32:
; SSE41-LABEL: extractelement_v4i32
; SSE41: pextrd
}
......@@ -172,10 +166,10 @@ entry:
%res = extractelement <8 x i16> %vec, i32 1
%res.ext = zext i16 %res to i32
ret i32 %res.ext
; CHECK-LABEL: extractelement_v8i16:
; CHECK-LABEL: extractelement_v8i16
; CHECK: pextrw
; SSE41-LABEL: extractelement_v8i16:
; SSE41-LABEL: extractelement_v8i16
; SSE41: pextrw
}
......@@ -184,12 +178,12 @@ entry:
%res = extractelement <16 x i8> %vec, i32 1
%res.ext = zext i8 %res to i32
ret i32 %res.ext
; CHECK-LABEL: extractelement_v16i8:
; CHECK-LABEL: extractelement_v16i8
; CHECK: movups
; CHECK: lea
; CHECK: mov
; SSE41-LABEL: extractelement_v16i8:
; SSE41-LABEL: extractelement_v16i8
; SSE41: pextrb
}
......@@ -198,10 +192,10 @@ entry:
%res = extractelement <4 x i1> %vec, i32 1
%res.ext = zext i1 %res to i32
ret i32 %res.ext
; CHECK-LABEL: extractelement_v4i1:
; CHECK-LABEL: extractelement_v4i1
; CHECK: pshufd
; SSE41-LABEL: extractelement_v4i1:
; SSE41-LABEL: extractelement_v4i1
; SSE41: pextrd
}
......@@ -210,10 +204,10 @@ entry:
%res = extractelement <8 x i1> %vec, i32 1
%res.ext = zext i1 %res to i32
ret i32 %res.ext
; CHECK-LABEL: extractelement_v8i1:
; CHECK-LABEL: extractelement_v8i1
; CHECK: pextrw
; SSE41-LABEL: extractelement_v8i1:
; SSE41-LABEL: extractelement_v8i1
; SSE41: pextrw
}
......@@ -222,11 +216,11 @@ entry:
%res = extractelement <16 x i1> %vec, i32 1
%res.ext = zext i1 %res to i32
ret i32 %res.ext
; CHECK-LABEL: extractelement_v16i1:
; CHECK-LABEL: extractelement_v16i1
; CHECK: movups
; CHECK: lea
; CHECK: mov
; SSE41-LABEL: extractelement_v16i1:
; SSE41-LABEL: extractelement_v16i1
; SSE41: pextrb
}
tests_lit/llvm2ice_tests/vector-select.ll
; This file tests support for the select instruction with vector valued inputs.
; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
define <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2) {
entry:
%res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2
ret <16 x i8> %res
; CHECK-LABEL: test_select_v16i8:
; CHECK-LABEL: test_select_v16i8
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v16i8:
; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v16i8
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2) {
entry:
%res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2
ret <16 x i1> %res
; CHECK-LABEL: test_select_v16i1:
; CHECK-LABEL: test_select_v16i1
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v16i1:
; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v16i1
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2) {
entry:
%res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2
ret <8 x i16> %res
; CHECK-LABEL: test_select_v8i16:
; CHECK-LABEL: test_select_v8i16
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v8i16:
; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v8i16
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2) {
entry:
%res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
ret <8 x i1> %res
; CHECK-LABEL: test_select_v8i1:
; CHECK-LABEL: test_select_v8i1
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v8i1:
; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v8i1
; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2) {
entry:
%res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2
ret <4 x i32> %res
; CHECK-LABEL: test_select_v4i32:
; CHECK-LABEL: test_select_v4i32
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v4i32:
; SSE41: pslld xmm0, 31
; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v4i32
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <4 x float> @test_select_v4f32(<4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) {
entry:
%res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2
ret <4 x float> %res
; CHECK-LABEL: test_select_v4f32:
; CHECK-LABEL: test_select_v4f32
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v4f32:
; SSE41: pslld xmm0, 31
; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v4f32
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2) {
entry:
%res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2
ret <4 x i1> %res
; CHECK-LABEL: test_select_v4i1:
; CHECK-LABEL: test_select_v4i1
; CHECK: pand
; CHECK: pandn
; CHECK: por
; SSE41-LABEL: test_select_v4i1:
; SSE41: pslld xmm0, 31
; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
; SSE41-LABEL: test_select_v4i1
; SSE41: pslld xmm0,0x1f
; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
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