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swiftshader
Commit bb0a5fe3 by John Porto
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Subzero. Changes the Register Allocator so that it is aware of register

aliases. BUG= R=jvoung@chromium.org, stichnot@chromium.org Review URL: https://codereview.chromium.org/1319203005.
parent 8f98cdd2
Showing with 100 additions and 45 deletions
src/IceRegAlloc.h
......@@ -96,6 +96,7 @@ private:
Cfg *const Func;
GlobalContext *const Ctx;
TargetLowering *const Target;
OrderedRanges Unhandled;
/// UnhandledPrecolored is a subset of Unhandled, specially collected for
......@@ -108,6 +109,9 @@ private:
/// currently assigned to. It can be greater than 1 as a result of
/// AllowOverlap inference.
llvm::SmallVector<int32_t, REGS_SIZE> RegUses;
// TODO(jpp): for some architectures a SmallBitVector might not be big enough.
// Evaluate what the performance impact on those architectures is.
llvm::SmallVector<const llvm::SmallBitVector *, REGS_SIZE> RegAliases;
bool FindPreference = false;
bool FindOverlap = false;
......
src/IceTargetLowering.h
......@@ -211,6 +211,8 @@ public:
virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
RegSetMask Exclude) const = 0;
virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const = 0;
virtual const llvm::SmallBitVector &getAliasesForRegister(SizeT) const = 0;
void regAlloc(RegAllocKind Kind);
virtual void
......
src/IceTargetLoweringARM32.cpp
......@@ -187,6 +187,8 @@ TargetARM32::TargetARM32(Cfg *Func)
Float32Registers[RegARM32::val] = isFP32; \
Float64Registers[RegARM32::val] = isFP64; \
VectorRegisters[RegARM32::val] = isVec128; \
RegisterAliases[RegARM32::val].resize(RegARM32::Reg_NUM); \
RegisterAliases[RegARM32::val].set(RegARM32::val); \
ScratchRegs[RegARM32::val] = scratch;
REGARM32_TABLE;
#undef X
......
src/IceTargetLoweringARM32.h
......@@ -68,6 +68,9 @@ public:
const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
return TypeToRegisterSet[Ty];
}
const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
return RegisterAliases[Reg];
}
bool hasFramePointer() const override { return UsesFramePointer; }
SizeT getFrameOrStackReg() const override {
return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp;
......@@ -434,7 +437,9 @@ protected:
bool NeedsStackAlignment = false;
bool MaybeLeafFunc = true;
size_t SpillAreaSizeBytes = 0;
// TODO(jpp): std::array instead of array.
llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
llvm::SmallBitVector ScratchRegs;
llvm::SmallBitVector RegsUsed;
VarList PhysicalRegisters[IceType_NUM];
......
src/IceTargetLoweringMIPS32.cpp
......@@ -56,6 +56,8 @@ TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {
IntegerRegisters[RegMIPS32::val] = isInt; \
FloatRegisters[RegMIPS32::val] = isFP; \
VectorRegisters[RegMIPS32::val] = isFP; \
RegisterAliases[RegMIPS32::val].resize(RegMIPS32::Reg_NUM); \
RegisterAliases[RegMIPS32::val].set(RegMIPS32::val); \
ScratchRegs[RegMIPS32::val] = scratch;
REGMIPS32_TABLE;
#undef X
......
src/IceTargetLoweringMIPS32.h
......@@ -44,6 +44,9 @@ public:
const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
return TypeToRegisterSet[Ty];
}
const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
return RegisterAliases[Reg];
}
bool hasFramePointer() const override { return UsesFramePointer; }
SizeT getFrameOrStackReg() const override {
return UsesFramePointer ? RegMIPS32::Reg_FP : RegMIPS32::Reg_SP;
......@@ -128,6 +131,7 @@ protected:
bool UsesFramePointer = false;
bool NeedsStackAlignment = false;
llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
llvm::SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM];
llvm::SmallBitVector ScratchRegs;
llvm::SmallBitVector RegsUsed;
VarList PhysicalRegisters[IceType_NUM];
......
src/IceTargetLoweringX8632Traits.h
......@@ -25,6 +25,8 @@
#include "IceTargetLoweringX8632.def"
#include "IceTargetLowering.h"
#include <array>
namespace Ice {
class TargetX8632;
......@@ -312,20 +314,43 @@ template <> struct MachineTraits<TargetX8632> {
}
}
static void initRegisterSet(llvm::SmallBitVector *IntegerRegisters,
llvm::SmallBitVector *IntegerRegistersI8,
llvm::SmallBitVector *FloatRegisters,
llvm::SmallBitVector *VectorRegisters,
llvm::SmallBitVector *ScratchRegs) {
static void initRegisterSet(
std::array<llvm::SmallBitVector, IceType_NUM> *TypeToRegisterSet,
std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases,
llvm::SmallBitVector *ScratchRegs) {
llvm::SmallBitVector IntegerRegisters(RegisterSet::Reg_NUM);
llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM);
ScratchRegs->resize(RegisterSet::Reg_NUM);
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
(*IntegerRegisters)[RegisterSet::val] = isInt; \
(*IntegerRegistersI8)[RegisterSet::val] = isI8; \
(*FloatRegisters)[RegisterSet::val] = isFP; \
(*VectorRegisters)[RegisterSet::val] = isFP; \
(IntegerRegisters)[RegisterSet::val] = isInt; \
(IntegerRegistersI8)[RegisterSet::val] = isI8; \
(FloatRegisters)[RegisterSet::val] = isFP; \
(VectorRegisters)[RegisterSet::val] = isFP; \
(*RegisterAliases)[RegisterSet::val].resize(RegisterSet::Reg_NUM); \
(*RegisterAliases)[RegisterSet::val].set(RegisterSet::val); \
(*ScratchRegs)[RegisterSet::val] = scratch;
REGX8632_TABLE;
#undef X
(*TypeToRegisterSet)[IceType_void] = InvalidRegisters;
(*TypeToRegisterSet)[IceType_i1] = IntegerRegistersI8;
(*TypeToRegisterSet)[IceType_i8] = IntegerRegistersI8;
(*TypeToRegisterSet)[IceType_i16] = IntegerRegisters;
(*TypeToRegisterSet)[IceType_i32] = IntegerRegisters;
(*TypeToRegisterSet)[IceType_i64] = IntegerRegisters;
(*TypeToRegisterSet)[IceType_f32] = FloatRegisters;
(*TypeToRegisterSet)[IceType_f64] = FloatRegisters;
(*TypeToRegisterSet)[IceType_v4i1] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v8i1] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v16i1] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v16i8] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v8i16] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v4i32] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v4f32] = VectorRegisters;
}
static llvm::SmallBitVector
......
src/IceTargetLoweringX8664Traits.h
......@@ -25,6 +25,8 @@
#include "IceTargetLowering.h"
#include "IceTargetLoweringX8664.def"
#include <array>
namespace Ice {
class TargetX8664;
......@@ -325,20 +327,44 @@ template <> struct MachineTraits<TargetX8664> {
}
}
static void initRegisterSet(llvm::SmallBitVector *IntegerRegisters,
llvm::SmallBitVector *IntegerRegistersI8,
llvm::SmallBitVector *FloatRegisters,
llvm::SmallBitVector *VectorRegisters,
llvm::SmallBitVector *ScratchRegs) {
static void initRegisterSet(
std::array<llvm::SmallBitVector, IceType_NUM> *TypeToRegisterSet,
std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases,
llvm::SmallBitVector *ScratchRegs) {
llvm::SmallBitVector IntegerRegisters(RegisterSet::Reg_NUM);
llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM);
ScratchRegs->resize(RegisterSet::Reg_NUM);
#define X(val, encode, name64, name32, name16, name8, scratch, preserved, \
stackptr, frameptr, isInt, isFP) \
(*IntegerRegisters)[RegisterSet::val] = isInt; \
(*IntegerRegistersI8)[RegisterSet::val] = isInt; \
(*FloatRegisters)[RegisterSet::val] = isFP; \
(*VectorRegisters)[RegisterSet::val] = isFP; \
(IntegerRegisters)[RegisterSet::val] = isInt; \
(IntegerRegistersI8)[RegisterSet::val] = isInt; \
(FloatRegisters)[RegisterSet::val] = isFP; \
(VectorRegisters)[RegisterSet::val] = isFP; \
(*RegisterAliases)[RegisterSet::val].resize(RegisterSet::Reg_NUM); \
(*RegisterAliases)[RegisterSet::val].set(RegisterSet::val); \
(*ScratchRegs)[RegisterSet::val] = scratch;
REGX8664_TABLE;
#undef X
(*TypeToRegisterSet)[IceType_void] = InvalidRegisters;
(*TypeToRegisterSet)[IceType_i1] = IntegerRegistersI8;
(*TypeToRegisterSet)[IceType_i8] = IntegerRegistersI8;
(*TypeToRegisterSet)[IceType_i16] = IntegerRegisters;
(*TypeToRegisterSet)[IceType_i32] = IntegerRegisters;
(*TypeToRegisterSet)[IceType_i64] = IntegerRegisters;
(*TypeToRegisterSet)[IceType_f32] = FloatRegisters;
(*TypeToRegisterSet)[IceType_f64] = FloatRegisters;
(*TypeToRegisterSet)[IceType_v4i1] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v8i1] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v16i1] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v16i8] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v8i16] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v4i32] = VectorRegisters;
(*TypeToRegisterSet)[IceType_v4f32] = VectorRegisters;
}
static llvm::SmallBitVector
......
src/IceTargetLoweringX86Base.h
......@@ -23,6 +23,7 @@
#include "IceTargetLowering.h"
#include "IceUtils.h"
#include <array>
#include <type_traits>
#include <utility>
......@@ -75,6 +76,12 @@ public:
const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
return TypeToRegisterSet[Ty];
}
const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override {
assert(Reg < Traits::RegisterSet::Reg_NUM);
return RegisterAliases[Reg];
}
bool hasFramePointer() const override { return IsEbpBasedFrame; }
SizeT getFrameOrStackReg() const override {
return IsEbpBasedFrame ? Traits::RegisterSet::Reg_ebp
......@@ -680,10 +687,12 @@ protected:
bool IsEbpBasedFrame = false;
bool NeedsStackAlignment = false;
size_t SpillAreaSizeBytes = 0;
llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
std::array<llvm::SmallBitVector, IceType_NUM> TypeToRegisterSet;
std::array<llvm::SmallBitVector, Traits::RegisterSet::Reg_NUM>
RegisterAliases;
llvm::SmallBitVector ScratchRegs;
llvm::SmallBitVector RegsUsed;
VarList PhysicalRegisters[IceType_NUM];
std::array<VarList, IceType_NUM> PhysicalRegisters;
/// Randomize a given immediate operand
Operand *randomizeOrPoolImmediate(Constant *Immediate,
......
src/IceTargetLoweringX86BaseImpl.h
......@@ -281,31 +281,7 @@ TargetX86Base<Machine>::TargetX86Base(Cfg *Func)
}
// TODO: Don't initialize IntegerRegisters and friends every time. Instead,
// initialize in some sort of static initializer for the class.
llvm::SmallBitVector IntegerRegisters(Traits::RegisterSet::Reg_NUM);
llvm::SmallBitVector IntegerRegistersI8(Traits::RegisterSet::Reg_NUM);
llvm::SmallBitVector FloatRegisters(Traits::RegisterSet::Reg_NUM);
llvm::SmallBitVector VectorRegisters(Traits::RegisterSet::Reg_NUM);
llvm::SmallBitVector InvalidRegisters(Traits::RegisterSet::Reg_NUM);
ScratchRegs.resize(Traits::RegisterSet::Reg_NUM);
Traits::initRegisterSet(&IntegerRegisters, &IntegerRegistersI8,
&FloatRegisters, &VectorRegisters, &ScratchRegs);
TypeToRegisterSet[IceType_void] = InvalidRegisters;
TypeToRegisterSet[IceType_i1] = IntegerRegistersI8;
TypeToRegisterSet[IceType_i8] = IntegerRegistersI8;
TypeToRegisterSet[IceType_i16] = IntegerRegisters;
TypeToRegisterSet[IceType_i32] = IntegerRegisters;
TypeToRegisterSet[IceType_i64] = IntegerRegisters;
TypeToRegisterSet[IceType_f32] = FloatRegisters;
TypeToRegisterSet[IceType_f64] = FloatRegisters;
TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
Traits::initRegisterSet(&TypeToRegisterSet, &RegisterAliases, &ScratchRegs);
}
template <class Machine> void TargetX86Base<Machine>::translateO2() {
......
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