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Commit bd385e46 by Jan Voung
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Lift register and condition code enums out into their own file.

Lift the enums out of IceInstX8632.h and IceTargetLoweringX8632.h. This will later allow the assembler to share the enum values and use them as encodings where appropriate. E.g., to avoid having a separate enum in: https://codereview.chromium.org/476323004/diff/680001/src/assembler_constants_ia32.h The "all registers" enum is retained, but separate GPRRegister and XmmRegister enums are created with tags "Encoded_Reg_foo" to represent the encoded value of register "foo". Functions are added to convert from the "all registers" namespace to the encoded ones. Re-order the BrCond so that they match the encoding according to the "Instruction Subcode" in B.1 of the Intel Manuals. BUG=none R=stichnot@chromium.org Review URL: https://codereview.chromium.org/582113003
parent 89906a5e
Showing with 244 additions and 94 deletions
src/IceConditionCodesX8632.h 0 → 100644
//===- subzero/src/IceConditionCodesX8632.h - Condition Codes ---*- C++ -*-===//
//
// The Subzero Code Generator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the condition codes for x86-32.
//
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICECONDITIONCODESX8632_H
#define SUBZERO_SRC_ICECONDITIONCODESX8632_H
#include "IceDefs.h"
#include "IceInstX8632.def"
namespace Ice {
class CondX86 {
public:
// An enum of condition codes used for branches and cmov. The enum value
// should match the value used to encode operands in binary instructions.
enum BrCond {
#define X(tag, encode, opp, dump, emit) tag encode,
ICEINSTX8632BR_TABLE
#undef X
Br_None
};
// An enum of condition codes relevant to the CMPPS instruction. The enum
// value should match the value used to encode operands in binary
// instructions.
enum CmppsCond {
#define X(tag, emit) tag,
ICEINSTX8632CMPPS_TABLE
#undef X
Cmpps_Invalid
};
};
} // end of namespace Ice
#endif // SUBZERO_SRC_ICECONDITIONCODESX8632_H
src/IceInstX8632.cpp
......@@ -14,8 +14,10 @@
#include "IceCfg.h"
#include "IceCfgNode.h"
#include "IceConditionCodesX8632.h"
#include "IceInst.h"
#include "IceInstX8632.h"
#include "IceRegistersX8632.h"
#include "IceTargetLoweringX8632.h"
#include "IceOperand.h"
......@@ -24,12 +26,12 @@ namespace Ice {
namespace {
const struct InstX8632BrAttributes_ {
InstX8632::BrCond Opposite;
CondX86::BrCond Opposite;
const char *DisplayString;
const char *EmitString;
} InstX8632BrAttributes[] = {
#define X(tag, opp, dump, emit) \
{ InstX8632::opp, dump, emit } \
#define X(tag, encode, opp, dump, emit) \
{ CondX86::opp, dump, emit } \
,
ICEINSTX8632BR_TABLE
#undef X
......@@ -131,8 +133,7 @@ IceString InstX8632Label::getName(const Cfg *Func) const {
InstX8632Br::InstX8632Br(Cfg *Func, const CfgNode *TargetTrue,
const CfgNode *TargetFalse,
const InstX8632Label *Label,
InstX8632::BrCond Condition)
const InstX8632Label *Label, CondX86::BrCond Condition)
: InstX8632(Func, InstX8632::Br, 0, NULL), Condition(Condition),
TargetTrue(TargetTrue), TargetFalse(TargetFalse), Label(Label) {}
......@@ -151,7 +152,7 @@ bool InstX8632Br::optimizeBranch(const CfgNode *NextNode) {
return false;
// Unconditional branch to the next node can be removed.
if (Condition == Br_None && getTargetFalse() == NextNode) {
if (Condition == CondX86::Br_None && getTargetFalse() == NextNode) {
assert(getTargetTrue() == NULL);
setDeleted();
return true;
......@@ -166,7 +167,7 @@ bool InstX8632Br::optimizeBranch(const CfgNode *NextNode) {
// (which was already tested above), then invert the branch
// condition, swap the targets, and set new fallthrough to NULL.
if (getTargetTrue() == NextNode) {
assert(Condition != Br_None);
assert(Condition != CondX86::Br_None);
Condition = InstX8632BrAttributes[Condition].Opposite;
TargetTrue = getTargetFalse();
TargetFalse = NULL;
......@@ -182,7 +183,7 @@ InstX8632Call::InstX8632Call(Cfg *Func, Variable *Dest, Operand *CallTarget)
}
InstX8632Cmov::InstX8632Cmov(Cfg *Func, Variable *Dest, Operand *Source,
InstX8632::BrCond Condition)
CondX86::BrCond Condition)
: InstX8632(Func, InstX8632::Cmov, 2, Dest), Condition(Condition) {
// The final result is either the original Dest, or Source, so mark
// both as sources.
......@@ -191,7 +192,7 @@ InstX8632Cmov::InstX8632Cmov(Cfg *Func, Variable *Dest, Operand *Source,
}
InstX8632Cmpps::InstX8632Cmpps(Cfg *Func, Variable *Dest, Operand *Source,
InstX8632Cmpps::CmppsCond Condition)
CondX86::CmppsCond Condition)
: InstX8632(Func, InstX8632::Cmpps, 2, Dest), Condition(Condition) {
addSource(Dest);
addSource(Source);
......@@ -202,7 +203,7 @@ InstX8632Cmpxchg::InstX8632Cmpxchg(Cfg *Func, Operand *DestOrAddr,
bool Locked)
: InstX8632Lockable(Func, InstX8632::Cmpxchg, 3,
llvm::dyn_cast<Variable>(DestOrAddr), Locked) {
assert(Eax->getRegNum() == TargetX8632::Reg_eax);
assert(Eax->getRegNum() == RegX8632::Reg_eax);
addSource(DestOrAddr);
addSource(Eax);
addSource(Desired);
......@@ -213,10 +214,10 @@ InstX8632Cmpxchg8b::InstX8632Cmpxchg8b(Cfg *Func, OperandX8632 *Addr,
Variable *Ecx, Variable *Ebx,
bool Locked)
: InstX8632Lockable(Func, InstX8632::Cmpxchg, 5, NULL, Locked) {
assert(Edx->getRegNum() == TargetX8632::Reg_edx);
assert(Eax->getRegNum() == TargetX8632::Reg_eax);
assert(Ecx->getRegNum() == TargetX8632::Reg_ecx);
assert(Ebx->getRegNum() == TargetX8632::Reg_ebx);
assert(Edx->getRegNum() == RegX8632::Reg_edx);
assert(Eax->getRegNum() == RegX8632::Reg_eax);
assert(Ecx->getRegNum() == RegX8632::Reg_ecx);
assert(Ebx->getRegNum() == RegX8632::Reg_ebx);
addSource(Addr);
addSource(Edx);
addSource(Eax);
......@@ -347,7 +348,7 @@ void InstX8632Br::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t";
if (Condition == Br_None) {
if (Condition == CondX86::Br_None) {
Str << "jmp";
} else {
Str << InstX8632BrAttributes[Condition].EmitString;
......@@ -356,7 +357,7 @@ void InstX8632Br::emit(const Cfg *Func) const {
if (Label) {
Str << "\t" << Label->getName(Func) << "\n";
} else {
if (Condition == Br_None) {
if (Condition == CondX86::Br_None) {
Str << "\t" << getTargetFalse()->getAsmName() << "\n";
} else {
Str << "\t" << getTargetTrue()->getAsmName() << "\n";
......@@ -371,7 +372,7 @@ void InstX8632Br::dump(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
Str << "br ";
if (Condition == Br_None) {
if (Condition == CondX86::Br_None) {
Str << "label %"
<< (Label ? Label->getName(Func) : getTargetFalse()->getName());
return;
......@@ -422,7 +423,7 @@ void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func,
bool EmittedSrc1 = false;
if (ShiftHack) {
Variable *ShiftReg = llvm::dyn_cast<Variable>(Inst->getSrc(1));
if (ShiftReg && ShiftReg->getRegNum() == TargetX8632::Reg_ecx) {
if (ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx) {
Str << "cl";
EmittedSrc1 = true;
}
......@@ -611,7 +612,7 @@ void emitVariableBlendInst(const char *Opcode, const Inst *Inst,
assert(Inst->getSrcSize() == 3);
assert(llvm::isa<Variable>(Inst->getSrc(2)));
assert(llvm::cast<Variable>(Inst->getSrc(2))->getRegNum() ==
TargetX8632::Reg_xmm0);
RegX8632::Reg_xmm0);
Str << "\t" << Opcode << "\t";
Inst->getDest()->emit(Func);
Str << ", ";
......@@ -640,7 +641,7 @@ template <> void InstX8632Imul::emit(const Cfg *Func) const {
// The 8-bit version of imul only allows the form "imul r/m8".
Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
(void)Src0;
assert(Src0 && Src0->getRegNum() == TargetX8632::Reg_eax);
assert(Src0 && Src0->getRegNum() == RegX8632::Reg_eax);
Str << "\timul\t";
getSrc(1)->emit(Func);
Str << "\n";
......@@ -662,21 +663,21 @@ template <> void InstX8632Cbwdq::emit(const Cfg *Func) const {
assert(getSrcSize() == 1);
Operand *Src0 = getSrc(0);
assert(llvm::isa<Variable>(Src0));
assert(llvm::cast<Variable>(Src0)->getRegNum() == TargetX8632::Reg_eax);
assert(llvm::cast<Variable>(Src0)->getRegNum() == RegX8632::Reg_eax);
switch (Src0->getType()) {
default:
llvm_unreachable("unexpected source type!");
break;
case IceType_i8:
assert(getDest()->getRegNum() == TargetX8632::Reg_eax);
assert(getDest()->getRegNum() == RegX8632::Reg_eax);
Str << "\tcbw\n";
break;
case IceType_i16:
assert(getDest()->getRegNum() == TargetX8632::Reg_edx);
assert(getDest()->getRegNum() == RegX8632::Reg_edx);
Str << "\tcwd\n";
break;
case IceType_i32:
assert(getDest()->getRegNum() == TargetX8632::Reg_edx);
assert(getDest()->getRegNum() == RegX8632::Reg_edx);
Str << "\tcdq\n";
break;
}
......@@ -686,9 +687,8 @@ void InstX8632Mul::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 2);
assert(llvm::isa<Variable>(getSrc(0)));
assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() ==
TargetX8632::Reg_eax);
assert(getDest()->getRegNum() == TargetX8632::Reg_eax); // TODO: allow edx?
assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
assert(getDest()->getRegNum() == RegX8632::Reg_eax); // TODO: allow edx?
Str << "\tmul\t";
getSrc(1)->emit(Func);
Str << "\n";
......@@ -712,7 +712,7 @@ void InstX8632Shld::emit(const Cfg *Func) const {
Str << ", ";
if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
(void)ShiftReg;
assert(ShiftReg->getRegNum() == TargetX8632::Reg_ecx);
assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
Str << "cl";
} else {
getSrc(2)->emit(Func);
......@@ -738,7 +738,7 @@ void InstX8632Shrd::emit(const Cfg *Func) const {
Str << ", ";
if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
(void)ShiftReg;
assert(ShiftReg->getRegNum() == TargetX8632::Reg_ecx);
assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
Str << "cl";
} else {
getSrc(2)->emit(Func);
......@@ -756,7 +756,7 @@ void InstX8632Shrd::dump(const Cfg *Func) const {
void InstX8632Cmov::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t";
assert(Condition != Br_None);
assert(Condition != CondX86::Br_None);
assert(getDest()->hasReg());
Str << "cmov" << InstX8632BrAttributes[Condition].DisplayString << "\t";
getDest()->emit(Func);
......@@ -777,7 +777,7 @@ void InstX8632Cmov::dump(const Cfg *Func) const {
void InstX8632Cmpps::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 2);
assert(Condition < Cmpps_Invalid);
assert(Condition < CondX86::Cmpps_Invalid);
Str << "\t";
Str << "cmp" << InstX8632CmppsAttributes[Condition].EmitString << "ps"
<< "\t";
......@@ -789,7 +789,7 @@ void InstX8632Cmpps::emit(const Cfg *Func) const {
void InstX8632Cmpps::dump(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrDump();
assert(Condition < Cmpps_Invalid);
assert(Condition < CondX86::Cmpps_Invalid);
dumpDest(Func);
Str << " = cmp" << InstX8632CmppsAttributes[Condition].EmitString << "ps"
<< "\t";
......
src/IceInstX8632.def
......@@ -16,8 +16,8 @@
#define SUBZERO_SRC_ICEINSTX8632_DEF
// NOTE: esp is not considered isInt, to avoid register allocating it.
#define REGX8632_TABLE \
/* val, init, name, name16, name8, scratch, preserved, stackptr, \
#define REGX8632_GPR_TABLE \
/* val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP */ \
X(Reg_eax, = 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \
X(Reg_ecx, = Reg_eax + 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \
......@@ -26,9 +26,10 @@
X(Reg_esp, = Reg_eax + 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 0, 0) \
X(Reg_ebp, = Reg_eax + 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \
X(Reg_esi, = Reg_eax + 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \
X(Reg_edi, = Reg_eax + 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0) \
X(Reg_ah, = Reg_edi + 1, "???", "" , "ah", 0, 0, 0, 0, 1, 0, 0) \
X(Reg_xmm0, = Reg_ah + 1, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_edi, = Reg_eax + 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0)
#define REGX8632_XMM_TABLE \
X(Reg_xmm0, = 0, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
......@@ -36,9 +37,41 @@
X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
//#define X(val, init, name, name16, name8, scratch, preserved, stackptr,
//#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
// frameptr, isI8, isInt, isFP)
// We also provide a combined table, so that there is a namespace where
// all of the registers are considered and have distinct numberings.
// This is in contrast to the above, where the "encode" is based on how
// the register numbers will be encoded in binaries and values can overlap.
#define REGX8632_TABLE \
/* val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP */ \
REGX8632_GPR_TABLE \
X(Reg_ah, = Reg_eax + 4, "???", "" , "ah", 0, 0, 0, 0, 1, 0, 0) \
REGX8632_XMM_TABLE
//#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
// frameptr, isI8, isInt, isFP)
#define REGX8632_TABLE_BOUNDS \
/* val, init */ \
X(Reg_GPR_First, = Reg_eax) \
X(Reg_GPR_Last, = Reg_edi) \
X(Reg_XMM_First, = Reg_xmm0) \
X(Reg_XMM_Last, = Reg_xmm7) \
//define X(val, init)
// We also need the encodings for the Byte registers (other info overlaps
// what is in the REGX8632_GPR_TABLE).
#define REGX8632_BYTEREG_TABLE \
/* val, encode */ \
X(Reg_al, = 0) \
X(Reg_cl, = 1) \
X(Reg_dl, = 2) \
X(Reg_bl, = 3) \
X(Reg_ah, = 4)
//#define X(val, encode)
// X86 segment registers.
#define SEG_REGX8632_TABLE \
/* enum value, name */ \
......@@ -51,20 +84,24 @@
//#define X(val, name)
#define ICEINSTX8632BR_TABLE \
/* enum value, opposite, dump, emit */ \
X(Br_a, Br_be, "a", "ja") \
X(Br_ae, Br_b, "ae", "jae") \
X(Br_b, Br_ae, "b", "jb") \
X(Br_be, Br_a, "be", "jbe") \
X(Br_e, Br_ne, "e", "je") \
X(Br_g, Br_le, "g", "jg") \
X(Br_ge, Br_l, "ge", "jge") \
X(Br_l, Br_ge, "l", "jl") \
X(Br_le, Br_g, "le", "jle") \
X(Br_ne, Br_e, "ne", "jne") \
X(Br_np, Br_p, "np", "jnp") \
X(Br_p, Br_np, "p", "jp") \
//#define X(tag, opp, dump, emit)
/* enum value, encode, opposite, dump, emit */ \
X(Br_o, = 0, Br_no, "o", "jo") \
X(Br_no, = 1, Br_o, "no", "jno") \
X(Br_b, = 2, Br_ae, "b", "jb") \
X(Br_ae, = 3, Br_b, "ae", "jae") \
X(Br_e, = 4, Br_ne, "e", "je") \
X(Br_ne, = 5, Br_e, "ne", "jne") \
X(Br_be, = 6, Br_a, "be", "jbe") \
X(Br_a, = 7, Br_be, "a", "ja") \
X(Br_s, = 8, Br_ns, "s", "js") \
X(Br_ns, = 9, Br_s, "ns", "jns") \
X(Br_p, = 10, Br_np, "p", "jp") \
X(Br_np, = 11, Br_p, "np", "jnp") \
X(Br_l, = 12, Br_ge, "l", "jl") \
X(Br_ge, = 13, Br_l, "ge", "jge") \
X(Br_le, = 14, Br_g, "le", "jle") \
X(Br_g, = 15, Br_le, "g", "jg") \
//#define X(tag, encode, opp, dump, emit)
#define ICEINSTX8632CMPPS_TABLE \
/* enum value, emit */ \
......
src/IceInstX8632.h
......@@ -18,6 +18,7 @@
#include "IceDefs.h"
#include "IceInst.h"
#include "IceConditionCodesX8632.h"
#include "IceInstX8632.def"
#include "IceOperand.h"
......@@ -224,13 +225,6 @@ public:
Xor
};
enum BrCond {
#define X(tag, opp, dump, emit) tag,
ICEINSTX8632BR_TABLE
#undef X
Br_None
};
static const char *getWidthString(Type Ty);
virtual void emit(const Cfg *Func) const = 0;
virtual void dump(const Cfg *Func) const;
......@@ -308,7 +302,7 @@ class InstX8632Br : public InstX8632 {
public:
// Create a conditional branch to a node.
static InstX8632Br *create(Cfg *Func, CfgNode *TargetTrue,
CfgNode *TargetFalse, BrCond Condition) {
CfgNode *TargetFalse, CondX86::BrCond Condition) {
const InstX8632Label *NoLabel = NULL;
return new (Func->allocate<InstX8632Br>())
InstX8632Br(Func, TargetTrue, TargetFalse, NoLabel, Condition);
......@@ -318,12 +312,13 @@ public:
const CfgNode *NoCondTarget = NULL;
const InstX8632Label *NoLabel = NULL;
return new (Func->allocate<InstX8632Br>())
InstX8632Br(Func, NoCondTarget, Target, NoLabel, Br_None);
InstX8632Br(Func, NoCondTarget, Target, NoLabel, CondX86::Br_None);
}
// Create a non-terminator conditional branch to a node, with a
// fallthrough to the next instruction in the current node. This is
// used for switch lowering.
static InstX8632Br *create(Cfg *Func, CfgNode *Target, BrCond Condition) {
static InstX8632Br *create(Cfg *Func, CfgNode *Target,
CondX86::BrCond Condition) {
const CfgNode *NoUncondTarget = NULL;
const InstX8632Label *NoLabel = NULL;
return new (Func->allocate<InstX8632Br>())
......@@ -332,7 +327,7 @@ public:
// Create a conditional intra-block branch (or unconditional, if
// Condition==Br_None) to a label in the current block.
static InstX8632Br *create(Cfg *Func, InstX8632Label *Label,
BrCond Condition) {
CondX86::BrCond Condition) {
const CfgNode *NoCondTarget = NULL;
const CfgNode *NoUncondTarget = NULL;
return new (Func->allocate<InstX8632Br>())
......@@ -357,11 +352,11 @@ public:
private:
InstX8632Br(Cfg *Func, const CfgNode *TargetTrue, const CfgNode *TargetFalse,
const InstX8632Label *Label, BrCond Condition);
const InstX8632Label *Label, CondX86::BrCond Condition);
InstX8632Br(const InstX8632Br &) LLVM_DELETED_FUNCTION;
InstX8632Br &operator=(const InstX8632Br &) LLVM_DELETED_FUNCTION;
virtual ~InstX8632Br() {}
BrCond Condition;
CondX86::BrCond Condition;
const CfgNode *TargetTrue;
const CfgNode *TargetFalse;
const InstX8632Label *Label; // Intra-block branch target
......@@ -780,7 +775,7 @@ private:
class InstX8632Cmov : public InstX8632 {
public:
static InstX8632Cmov *create(Cfg *Func, Variable *Dest, Operand *Source,
BrCond Cond) {
CondX86::BrCond Cond) {
return new (Func->allocate<InstX8632Cmov>())
InstX8632Cmov(Func, Dest, Source, Cond);
}
......@@ -789,27 +784,21 @@ public:
static bool classof(const Inst *Inst) { return isClassof(Inst, Cmov); }
private:
InstX8632Cmov(Cfg *Func, Variable *Dest, Operand *Source, BrCond Cond);
InstX8632Cmov(Cfg *Func, Variable *Dest, Operand *Source,
CondX86::BrCond Cond);
InstX8632Cmov(const InstX8632Cmov &) LLVM_DELETED_FUNCTION;
InstX8632Cmov &operator=(const InstX8632Cmov &) LLVM_DELETED_FUNCTION;
virtual ~InstX8632Cmov() {}
BrCond Condition;
CondX86::BrCond Condition;
};
// Cmpps instruction - compare packed singled-precision floating point
// values
class InstX8632Cmpps : public InstX8632 {
public:
enum CmppsCond {
#define X(tag, emit) tag,
ICEINSTX8632CMPPS_TABLE
#undef X
Cmpps_Invalid
};
static InstX8632Cmpps *create(Cfg *Func, Variable *Dest, Operand *Source,
CmppsCond Condition) {
CondX86::CmppsCond Condition) {
return new (Func->allocate<InstX8632Cmpps>())
InstX8632Cmpps(Func, Dest, Source, Condition);
}
......@@ -818,12 +807,13 @@ public:
static bool classof(const Inst *Inst) { return isClassof(Inst, Cmpps); }
private:
InstX8632Cmpps(Cfg *Func, Variable *Dest, Operand *Source, CmppsCond Cond);
InstX8632Cmpps(Cfg *Func, Variable *Dest, Operand *Source,
CondX86::CmppsCond Cond);
InstX8632Cmpps(const InstX8632Cmpps &) LLVM_DELETED_FUNCTION;
InstX8632Cmpps &operator=(const InstX8632Cmpps &) LLVM_DELETED_FUNCTION;
virtual ~InstX8632Cmpps() {}
CmppsCond Condition;
CondX86::CmppsCond Condition;
};
// Cmpxchg instruction - cmpxchg <dest>, <desired> will compare if <dest>
......
src/IceRegistersX8632.h 0 → 100644
//===- subzero/src/IceRegistersX8632.h - Register information ---*- C++ -*-===//
//
// The Subzero Code Generator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the registers and their encodings for x86-32.
//
//===----------------------------------------------------------------------===//
#ifndef SUBZERO_SRC_ICEREGISTERSX8632_H
#define SUBZERO_SRC_ICEREGISTERSX8632_H
#include "IceDefs.h"
#include "IceInstX8632.def"
namespace Ice {
class RegX8632 {
public:
// An enum of every register. The enum value may not match the encoding
// used to binary encode register operands in instructions.
enum AllRegisters {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
val,
REGX8632_TABLE
#undef X
Reg_NUM,
#define X(val, init) val init,
REGX8632_TABLE_BOUNDS
#undef X
};
// An enum of GPR Registers. The enum value does match encoding used
// to binary encode register operands in instructions.
enum GPRRegister {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
Encoded_##val encode,
REGX8632_GPR_TABLE
#undef X
};
// An enum of XMM Registers. The enum value does match encoding used
// to binary encode register operands in instructions.
enum XmmRegister {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
Encoded_##val encode,
REGX8632_XMM_TABLE
#undef X
};
// An enum of Byte Registers. The enum value does match encoding used
// to binary encode register operands in instructions.
enum ByteRegister {
#define X(val, encode) Encoded_##val encode,
REGX8632_BYTEREG_TABLE
#undef X
};
static GPRRegister getEncodedGPR(int32_t RegNum) {
assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last);
return GPRRegister(RegNum - Reg_GPR_First);
}
static XmmRegister getEncodedXmm(int32_t RegNum) {
assert(Reg_XMM_First <= RegNum && RegNum <= Reg_XMM_Last);
return XmmRegister(RegNum - Reg_XMM_First);
}
static ByteRegister getEncodedByteReg(int32_t RegNum) {
assert(RegNum == Reg_ah || (Reg_GPR_First <= RegNum && RegNum <= Reg_ebx));
if (RegNum == Reg_ah)
return Encoded_Reg_ah;
return ByteRegister(RegNum - Reg_GPR_First);
}
};
} // end of namespace Ice
#endif // SUBZERO_SRC_ICEREGISTERSX8632_H
src/IceTargetLoweringX8632.h
......@@ -19,6 +19,7 @@
#include "IceDefs.h"
#include "IceTargetLowering.h"
#include "IceInstX8632.h"
#include "IceRegistersX8632.h"
namespace Ice {
......@@ -39,7 +40,7 @@ public:
}
virtual bool hasFramePointer() const { return IsEbpBasedFrame; }
virtual SizeT getFrameOrStackReg() const {
return IsEbpBasedFrame ? Reg_ebp : Reg_esp;
return IsEbpBasedFrame ? RegX8632::Reg_ebp : RegX8632::Reg_esp;
}
virtual size_t typeWidthInBytesOnStack(Type Ty) const {
// Round up to the next multiple of 4 bytes. In particular, i1,
......@@ -68,15 +69,6 @@ public:
Operand *loOperand(Operand *Operand);
Operand *hiOperand(Operand *Operand);
enum Registers {
#define X(val, init, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
val init,
REGX8632_TABLE
#undef X
Reg_NUM
};
enum X86InstructionSet {
// SSE2 is the PNaCl baseline instruction set.
SSE2,
......@@ -212,7 +204,7 @@ protected:
void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) {
Context.insert(InstX8632Blendvps::create(Func, Dest, Src0, Src1));
}
void _br(InstX8632::BrCond Condition, CfgNode *TargetTrue,
void _br(CondX86::BrCond Condition, CfgNode *TargetTrue,
CfgNode *TargetFalse) {
Context.insert(
InstX8632Br::create(Func, TargetTrue, TargetFalse, Condition));
......@@ -220,10 +212,10 @@ protected:
void _br(CfgNode *Target) {
Context.insert(InstX8632Br::create(Func, Target));
}
void _br(InstX8632::BrCond Condition, CfgNode *Target) {
void _br(CondX86::BrCond Condition, CfgNode *Target) {
Context.insert(InstX8632Br::create(Func, Target, Condition));
}
void _br(InstX8632::BrCond Condition, InstX8632Label *Label) {
void _br(CondX86::BrCond Condition, InstX8632Label *Label) {
Context.insert(InstX8632Br::create(Func, Label, Condition));
}
void _bsf(Variable *Dest, Operand *Src0) {
......@@ -238,14 +230,13 @@ protected:
void _cbwdq(Variable *Dest, Operand *Src0) {
Context.insert(InstX8632Cbwdq::create(Func, Dest, Src0));
}
void _cmov(Variable *Dest, Operand *Src0, InstX8632::BrCond Condition) {
void _cmov(Variable *Dest, Operand *Src0, CondX86::BrCond Condition) {
Context.insert(InstX8632Cmov::create(Func, Dest, Src0, Condition));
}
void _cmp(Operand *Src0, Operand *Src1) {
Context.insert(InstX8632Icmp::create(Func, Src0, Src1));
}
void _cmpps(Variable *Dest, Operand *Src0,
InstX8632Cmpps::CmppsCond Condition) {
void _cmpps(Variable *Dest, Operand *Src0, CondX86::CmppsCond Condition) {
Context.insert(InstX8632Cmpps::create(Func, Dest, Src0, Condition));
}
void _cmpxchg(Operand *DestOrAddr, Variable *Eax, Variable *Desired,
......
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